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/openbmc/u-boot/board/topic/zynq/zynq-topic-miamilite/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x202
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
/openbmc/linux/drivers/video/fbdev/geode/
H A Dlxfb_core.c41 FB_VMODE_NONINTERLACED, 0 },
45 FB_VMODE_NONINTERLACED, 0 },
48 0, FB_VMODE_NONINTERLACED, 0 },
52 FB_VMODE_NONINTERLACED, 0 },
56 FB_VMODE_NONINTERLACED, 0 },
60 FB_VMODE_NONINTERLACED, 0 },
63 0, FB_VMODE_NONINTERLACED, 0 },
66 0, FB_VMODE_NONINTERLACED, 0 },
70 FB_VMODE_NONINTERLACED, 0 },
73 0, FB_VMODE_NONINTERLACED, 0 },
[all …]
/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c39 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
51 { NULL, 87, 1024, 768, 22271, 56, 24, 33, 8, 160, 8, 0,
59 { NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, 0,
63 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
72 { NULL, 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3, 0,
76 { NULL, 89, 1152, 864, 15384, 96, 16, 110, 1, 216, 10, 0,
84 { NULL, 60, 1024, 768, 15384, 168, 8, 29, 3, 144, 6, 0,
88 { NULL, 100, 640, 480, 21834, 96, 32, 36, 8, 96, 6, 0,
[all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/openbmc/linux/drivers/video/fbdev/i810/
H A Di810_dvt.c21 { 25000, 0x0013, 0x0003, 0x40, 0x5F, 0x4F, 0x50, 0x82, 0x51, 0x9D,
22 0x0B, 0x10, 0x40, 0xE9, 0x0B, 0xDF, 0x50, 0xE7, 0x04, 0x02,
23 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22006000,
24 0x22002000, 0x22004000, 0x22006000, 0xC0 },
27 { 28000, 0x0053, 0x0010, 0x40, 0x61, 0x4F, 0x4F, 0x85, 0x52, 0x9A,
28 0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
29 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22005000,
30 0x22002000, 0x22004000, 0x22005000, 0xC0 },
33 { 31000, 0x0013, 0x0002, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x52, 0x97,
34 0x06, 0x0F, 0x40, 0xE8, 0x0B, 0xDF, 0x50, 0xDF, 0x07, 0x02,
[all …]
/openbmc/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Doem310.h55 0x00,0x00,0x00, /* 800x600 */
56 0x0b,0x0b,0x0b, /* 1024x768 */
57 0x08,0x08,0x08, /* 1280x1024 */
58 0x00,0x00,0x00, /* 640x480 (unknown) */
59 0x00,0x00,0x00, /* 1024x600 (unknown) */
60 0x00,0x00,0x00, /* 1152x864 (unknown) */
61 0x08,0x08,0x08, /* 1280x960 (guessed) */
62 0x00,0x00,0x00, /* 1152x768 (unknown) */
63 0x08,0x08,0x08, /* 1400x1050 */
64 0x08,0x08,0x08, /* 1280x768 (guessed) */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
28 description: i2c address of the bridge, 0x0f
48 port@0:
65 - port@0
88 reg = <0x078b8000 0x500>;
91 #size-cells = <0>;
95 reg = <0x0f>;
105 #size-cells = <0>;
107 port@0 {
[all …]
/openbmc/linux/Documentation/admin-guide/media/
H A Drkisp1.rst77 YUV4:2:2 -> YUV4:2:0). They also have cropping capability on the sink pad.
86 This is the isp entity. It is connected to the sensor on sink pad 0 and
88 the CSI-2 protocol. It has a cropping capability on sink pad 0 that is
90 Cropping on sink pad 0 defines the image region from the sensor.
126 In the following example, the sensor connected to pad 0 of 'rkisp1_isp' is
137 "media-ctl" "-d" "platform:rkisp1" "-l" "'imx219 4-0010':0 -> 'rkisp1_isp':0 [1]"
138 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_selfpath':0 [1]"
139 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_mainpath':0 [0]"
141 # set format for imx219 4-0010:0
142 "media-ctl" "-d" "platform:rkisp1" "--set-v4l2" '"imx219 4-0010":0 [fmt:SRGGB10_1X10/1640x1232]'
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra62x.dtsi11 reg = <0 0x800>,
12 <0x1200 0x100>;
16 reg = <0x1000 0x100>;
/openbmc/linux/Documentation/fb/
H A Dviafb.rst26 1440x1050(60 Hz), 1600x1200(60, 75 Hz), 1280x720(60 Hz),
59 - 0 : expansion (default)
63 0 : LCD panel with LSB data format input (default)
67 - 0 : Resolution: 640x480, Channel: single, Dithering: Enable
73 - 6 : Resolution: 1600x1200, Channel: dual, Dithering: Enable
82 - 15: Resolution: 1600x1200, Channel: dual, Dithering: Disable
89 - 0 : No 2D Hardware Acceleration
93 - 0 : viafb_SAMM_ON disable (default)
159 - 0 : No DVI on EPIA - M (default)
172 - 0 : No Dual Edge Panel (default)
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddwmmc.h7 #define DWMCI_CLKSEL 0x09C
12 #define EMMCP_MPSBEGIN0 0x1200
13 #define EMMCP_SEND0 0x1204
14 #define EMMCP_CTRL0 0x120C
16 #define MPSCTRL_SECURE_READ_BIT (0x1<<7)
17 #define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
18 #define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
19 #define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
20 #define MPSCTRL_USE_FUSE_KEY (0x1<<3)
21 #define MPSCTRL_ECB_MODE (0x1<<2)
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dmmconf-fam10h_64.c32 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
33 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
51 /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
52 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
53 #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
76 found = 0; in get_fam10h_pci_mmconf_base()
77 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) { in get_fam10h_pci_mmconf_base()
84 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); in get_fam10h_pci_mmconf_base()
86 vendor = id & 0xffff; in get_fam10h_pci_mmconf_base()
87 device = (id>>16) & 0xffff; in get_fam10h_pci_mmconf_base()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Drealtek,rtl-spi.yaml38 reg = <0x1200 0x100>;
40 #size-cells = <0>;
/openbmc/u-boot/board/topic/zynq/zynq-topic-miamiplus/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
2 0xf8000700 0x1202 // MIO configuration
3 0xf8000704 0x1202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
/openbmc/u-boot/board/topic/zynq/zynq-topic-miami/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
2 0xf8000700 0x1210 // MIO configuration
3 0xf8000704 0x202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x210
10 0xf8000720 0x202
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dnvidia,tegra20-apbdma.txt23 reg = <0x6000a000 0x1200>;
24 interrupts = < 0 136 0x04
25 0 137 0x04
26 0 138 0x04
27 0 139 0x04
28 0 140 0x04
29 0 141 0x04
30 0 142 0x04
31 0 143 0x04
32 0 144 0x04
[all …]
/openbmc/linux/drivers/media/usb/em28xx/
H A Dem28xx-camera.c17 0xb8 >> 1, /* MT9V111, MT9V403 */
18 0xba >> 1, /* MT9M001/011/111/112, MT9V011/012/112, MT9D011 */
19 0x90 >> 1, /* MT9V012/112, MT9D011 (alternative address) */
25 0x42 >> 1, /* OV7725, OV7670/60/48 */
26 0x60 >> 1, /* OV2640, OV9650/53/55 */
35 { 0x0d, 0x00, 0x01, }, /* reset and use defaults */ in em28xx_initialize_mt9m111()
36 { 0x0d, 0x00, 0x00, }, in em28xx_initialize_mt9m111()
37 { 0x0a, 0x00, 0x21, }, in em28xx_initialize_mt9m111()
38 { 0x21, 0x04, 0x00, }, /* full readout spd, no row/col skip */ in em28xx_initialize_mt9m111()
41 for (i = 0; i < ARRAY_SIZE(regs); i++) in em28xx_initialize_mt9m111()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
/openbmc/u-boot/arch/mips/mach-pic32/include/mach/
H A Dpic32.h13 #define PIC32_CFG_BASE 0x1f800000
16 #define CFGCON 0x0000
17 #define DEVID 0x0020
18 #define SYSKEY 0x0030
19 #define PMD1 0x0040
20 #define PMD7 0x00a0
21 #define CFGEBIA 0x00c0
22 #define CFGEBIC 0x00d0
23 #define CFGPG 0x00e0
24 #define CFGMPLL 0x0100
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Ddvi.h12 #define VT1632_DEVICE_ID_REG 0x02
13 #define VT1632_DEVICE_ID 0x92
15 #define GET_DVI_SIZE_BY_SYSTEM_BIOS 0x01
16 #define GET_DVI_SIZE_BY_VGA_BIOS 0x02
17 #define GET_DVI_SZIE_BY_HW_STRAPPING 0x03
21 #define DVI_PANEL_ID0_640X480 0x00
23 #define DVI_PANEL_ID1_800x600 0x01
25 #define DVI_PANEL_ID1_1024x768 0x02
27 #define DVI_PANEL_ID1_1280x768 0x03
29 #define DVI_PANEL_ID1_1280x1024 0x04
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]

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