| /openbmc/u-boot/cmd/aspeed/ |
| H A D | dptest.c | 18 #define MAINVER 0
33 #define DBG_ERR 0x00000001 /* DBG_ERROR */
34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */
35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */
36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */
37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */
38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */
39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */
40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */
41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */
[all …]
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| /openbmc/linux/drivers/mfd/ |
| H A D | wm8994-core.c | 33 .id = 0,
124 if (ret < 0) { in wm8994_suspend()
128 return 0; in wm8994_suspend()
155 if (ret != 0) in wm8994_suspend()
162 if (ret != 0) in wm8994_suspend()
170 if (ret != 0) { in wm8994_suspend()
175 return 0; in wm8994_suspend()
185 return 0; in wm8994_resume()
189 if (ret != 0) { in wm8994_resume()
196 if (ret != 0) { in wm8994_resume()
[all …]
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| /openbmc/linux/drivers/gpu/drm/i915/selftests/ |
| H A D | i915_perf.c | 35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
44 return 0; in alloc_empty_config()
99 0), in test_stream()
158 return 0; in live_sanitycheck()
179 *cs++ = 0; in write_timestamp()
180 *cs++ = 0; in write_timestamp()
181 *cs++ = 0; in write_timestamp()
185 return 0; in write_timestamp()
221 for (i = 0; i < 4; i++) in live_noa_delay()
[all …]
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| /openbmc/linux/drivers/of/unittest-data/ |
| H A D | overlay_bad_add_dup_node.dtso | 18 power_bus = <0x1 0x2>;
25 power_bus_emergency = <0x101 0x102>;
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| /openbmc/u-boot/include/ |
| H A D | micrel.h | 3 #define MII_KSZ9021_EXT_COMMON_CTRL 0x100
4 #define MII_KSZ9021_EXT_STRAP_STATUS 0x101
5 #define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
6 #define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
7 #define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
8 #define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
9 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
10 #define MII_KSZ9021_EXT_ANALOG_TEST 0x107
12 #define MII_KSZ9031_MOD_REG 0x0000
14 #define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
[all …]
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| /openbmc/linux/include/soc/arc/ |
| H A D | timers.h | 12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
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| /openbmc/u-boot/board/renesas/r7780mp/ |
| H A D | r7780mp.h | 13 #define FPGA_BASE 0xa4000000
14 #define FPGA_IRLMSK (FPGA_BASE + 0x00)
15 #define FPGA_IRLMON (FPGA_BASE + 0x02)
16 #define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
17 #define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
18 #define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
19 #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
20 #define FPGA_RSTCTL (FPGA_BASE + 0x0C)
21 #define FPGA_PCIBD (FPGA_BASE + 0x0E)
22 #define FPGA_PCICD (FPGA_BASE + 0x10)
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | ps3gpu.h | 16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
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| /openbmc/openbmc-tools/adcapp/src/ |
| H A D | adc.h | 15 #define READ_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x100,0x3FFF)
16 #define READ_ADC_REF_VOLATGE _IOC(_IOC_WRITE,'K',0x101,0x3FFF)
17 #define READ_ADC_RESOLUTION _IOC(_IOC_WRITE,'K',0x102,0x3FFF)
18 #define ENABLE_EXT_REF_VOLTAGE _IOC(_IOC_WRITE,'K',0x103,0x3FFF)
19 #define DISABLE_EXT_REF_VOLTAGE _IOC(_IOC_WRITE,'K',0x104,0x3FFF)
20 #define ENABLE_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x105,0x3FFF)
21 #define DISABLE_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x106,0x3FFF)
31 #if 0
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| /openbmc/linux/arch/arm/boot/dts/microchip/ |
| H A D | usb_a9g20-dab-mmx.dtsi | 21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | lowlevel_init.S | 36 ldr r0, =0x102
41 MRC p15, 4, R0, c1, c0, 0
42 ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
44 MCR p15, 4, R0, c1, c0, 0
47 .word 0x0
60 smc 0 @ SMC #0 to enter monitor mode
68 mov r6, #0xFF @ Indicate new Task call
69 mov r12, #0x00 @ Secure Service ID in R12
73 smc 0 @ SMC #0 to enter monitor mode
81 mov r12, #0xFE
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap-secure.h | 16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
20 #define API_HAL_RET_VALUE_OK 0x00
21 #define API_HAL_RET_VALUE_FAIL 0x01
24 #define FLAG_START_CRITICAL 0x4
25 #define FLAG_IRQFIQ_MASK 0x3
26 #define FLAG_IRQ_ENABLE 0x2
27 #define FLAG_FIQ_ENABLE 0x1
28 #define NO_FLAG 0x0
33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-data-modul-edm-sbc.dts | 28 reg = <0x0 0x40000000 0 0x40000000>;
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
69 gpio = <&gpio3 6 0>;
78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap4/ |
| H A D | sys_proto.h | 69 #define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102
|
| /openbmc/linux/include/linux/mfd/ |
| H A D | idt82p33_reg.h | 10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
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| /openbmc/linux/sound/soc/qcom/qdsp6/ |
| H A D | q6prm.h | 7 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
9 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
11 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
13 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
15 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
17 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
19 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
21 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
23 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
25 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| H A D | cache.json | 79 "EventCode": "0x34",
85 "EventCode": "0x35",
91 "EventCode": "0x102",
97 "EventCode": "0x103",
103 "EventCode": "0x104",
109 "EventCode": "0x105",
115 "EventCode": "0x106",
121 "EventCode": "0x107",
127 "EventCode": "0x111",
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | meson-gxm.dtsi | 48 reg = <0x0 0x100>;
57 reg = <0x0 0x101>;
66 reg = <0x0 0x102>;
75 reg = <0x0 0x103>;
86 #phy-cells = <0>;
87 reg = <0x0 0x78040 0x0 0x20>;
105 clock-indices = <0 1>;
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| /openbmc/linux/drivers/media/i2c/ |
| H A D | wm8775.c | 40 #define ALC_HOLD 0x85 /* R17: use zero cross detection, ALC hold time 42.6 ms */
41 #define ALC_EN 0x100 /* R17: ALC enable */
50 u8 input; /* Last selected input (0-0xf) */
68 if (reg < 0 || reg >= TOT_REGS) { in wm8775_write()
73 for (i = 0; i < 3; i++) in wm8775_write()
75 (reg << 1) | (val >> 8), val & 0xff) == 0) in wm8775_write()
76 return 0; in wm8775_write()
85 int muted = 0 != state->mute->val; in wm8775_set_audio()
89 /* normalize ( 65535 to 0 -> 255 to 0 (+24dB to -103dB) ) */ in wm8775_set_audio()
95 wm8775_write(sd, R21, 0x0c0 | state->input); in wm8775_set_audio()
[all …]
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| /openbmc/qemu/tests/tcg/s390x/ |
| H A D | vrep.c | 20 if (insn[0] != 0xe7 || insn[5] != 0x4d) { in handle_sigill()
44 S390Vector v3 = {.d[0] = 1, .d[1] = 2}; in main()
49 memset(&act, 0, sizeof(act)); in main()
53 assert(err == 0); in main()
55 assert(vrep(&v1, &v3, 7, 0) == -1); in main()
56 assert(v1.d[0] == 0x0101010101010101ULL); in main()
57 assert(v1.d[1] == 0x0101010101010101ULL); in main()
60 assert(v1.d[0] == 0x0002000200020002ULL); in main()
61 assert(v1.d[1] == 0x0002000200020002ULL); in main()
64 assert(v1.d[0] == 0x0000000100000001ULL); in main()
[all …]
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| /openbmc/linux/drivers/usb/renesas_usbhs/ |
| H A D | rcar3.c | 13 #define LPSTS 0x102
14 #define UGCTRL 0x180 /* 32-bit register */
15 #define UGCTRL2 0x184 /* 32-bit register */
16 #define UGSTS 0x188 /* 32-bit register */
19 #define LPSTS_SUSPM 0x4000
22 #define UGCTRL_PLLRESET 0x00000001
23 #define UGCTRL_CONNECT 0x00000004
27 * Remarks: bit[31:11] and bit[9:6] should be 0
29 #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
30 #define UGCTRL2_USB0SEL_HSUSB 0x00000020
[all …]
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| /openbmc/linux/arch/mips/boot/dts/img/ |
| H A D | pistachio_marduk.dts | 31 reg = <0x00000000 0x10000000>;
64 linux,code = <0x101>; /* BTN_1 */
69 linux,code = <0x102>; /* BTN_2 */
82 pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
85 cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
87 flash@0 {
89 reg = <0>;
136 pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
144 adc-reserved-channels = <0x10>;
153 reg = <0x20>;
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| /openbmc/u-boot/arch/arc/include/asm/ |
| H A D | arcregs.h | 22 * is 0 this means given HW block is absent - this is especially useful because
30 #define ARC_BCR_VERSION_MASK GENMASK(7, 0)
33 #define ARC_AUX_IDENTITY 0x04
34 #define ARC_AUX_STATUS32 0x0a
40 #define ARC_AUX_IC_IVIC 0x10
41 #define ARC_AUX_IC_CTRL 0x11
42 #define ARC_AUX_IC_IVIL 0x19
44 #define ARC_AUX_IC_PTAG 0x1E
46 #define ARC_BCR_IC_BUILD 0x77
47 #define AUX_AUX_CACHE_LIMIT 0x5D
[all …]
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| /openbmc/u-boot/lib/efi_selftest/ |
| H A D | efi_selftest_util.c | 18 {0, L"Null"},
23 {0, NULL},
30 {0x00, L"Null"},
31 {0x01, L"Up"},
32 {0x02, L"Down"},
33 {0x03, L"Right"},
34 {0x04, L"Left"},
35 {0x05, L"Home"},
36 {0x06, L"End"},
37 {0x07, L"Insert"},
[all …]
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