1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b26c2e38SVineet Gupta /* 3b26c2e38SVineet Gupta * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 4b26c2e38SVineet Gupta */ 5b26c2e38SVineet Gupta 6b26c2e38SVineet Gupta #ifndef __SOC_ARC_TIMERS_H 7b26c2e38SVineet Gupta #define __SOC_ARC_TIMERS_H 8b26c2e38SVineet Gupta 9b26c2e38SVineet Gupta #include <soc/arc/aux.h> 10b26c2e38SVineet Gupta 11b26c2e38SVineet Gupta /* Timer related Aux registers */ 12b26c2e38SVineet Gupta #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 13b26c2e38SVineet Gupta #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 14b26c2e38SVineet Gupta #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 15b26c2e38SVineet Gupta #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 16b26c2e38SVineet Gupta #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 17b26c2e38SVineet Gupta #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 18b26c2e38SVineet Gupta 19b26c2e38SVineet Gupta /* CTRL reg bits */ 20*58100c34SRandy Dunlap #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 21*58100c34SRandy Dunlap #define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 22b26c2e38SVineet Gupta 23b26c2e38SVineet Gupta #define ARC_TIMERN_MAX 0xFFFFFFFF 24b26c2e38SVineet Gupta 25b26c2e38SVineet Gupta #define ARC_REG_TIMERS_BCR 0x75 26b26c2e38SVineet Gupta 27b26c2e38SVineet Gupta struct bcr_timer { 28b26c2e38SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 29b26c2e38SVineet Gupta unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 30b26c2e38SVineet Gupta #else 31b26c2e38SVineet Gupta unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 32b26c2e38SVineet Gupta #endif 33b26c2e38SVineet Gupta }; 34b26c2e38SVineet Gupta 35b26c2e38SVineet Gupta #endif 36