Lines Matching +full:0 +full:x102
22 * is 0 this means given HW block is absent - this is especially useful because
30 #define ARC_BCR_VERSION_MASK GENMASK(7, 0)
33 #define ARC_AUX_IDENTITY 0x04
34 #define ARC_AUX_STATUS32 0x0a
40 #define ARC_AUX_IC_IVIC 0x10
41 #define ARC_AUX_IC_CTRL 0x11
42 #define ARC_AUX_IC_IVIL 0x19
44 #define ARC_AUX_IC_PTAG 0x1E
46 #define ARC_BCR_IC_BUILD 0x77
47 #define AUX_AUX_CACHE_LIMIT 0x5D
48 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
51 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
52 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
55 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
56 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
57 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
59 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
60 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
61 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
63 #define ARC_AUX_INTR_VEC_BASE 0x25
66 #define ARC_AUX_DC_IVDC 0x47
67 #define ARC_AUX_DC_CTRL 0x48
69 #define ARC_AUX_DC_IVDL 0x4A
70 #define ARC_AUX_DC_FLSH 0x4B
71 #define ARC_AUX_DC_FLDL 0x4C
73 #define ARC_AUX_DC_PTAG 0x5C
75 #define ARC_BCR_DC_BUILD 0x72
76 #define ARC_BCR_SLC 0xce
77 #define ARC_AUX_SLC_CONFIG 0x901
78 #define ARC_AUX_SLC_CTRL 0x903
79 #define ARC_AUX_SLC_FLUSH 0x904
80 #define ARC_AUX_SLC_INVALIDATE 0x905
81 #define ARC_AUX_SLC_IVDL 0x910
82 #define ARC_AUX_SLC_FLDL 0x912
83 #define ARC_AUX_SLC_RGN_START 0x914
84 #define ARC_AUX_SLC_RGN_START1 0x915
85 #define ARC_AUX_SLC_RGN_END 0x916
86 #define ARC_AUX_SLC_RGN_END1 0x917
87 #define ARC_BCR_CLUSTER 0xcf
90 #define ARC_AUX_MMU_BCR 0x6f
93 #define ARC_AUX_IO_COH_ENABLE 0x500
94 #define ARC_AUX_IO_COH_PARTIAL 0x501
95 #define ARC_AUX_IO_COH_AP0_BASE 0x508
96 #define ARC_AUX_IO_COH_AP0_SIZE 0x509
99 #define ARC_AUX_XY_BUILD 0x79
102 #define ARC_AUX_DSP_BUILD 0x7A
105 #define ARC_AUX_SUBSYS_BUILD 0xF0
116 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)