Searched +full:0 +full:x0200a000 (Results 1 – 11 of 11) sorted by relevance
14 pattern: "^(watchdog|timer)@[0-9a-f]+$"72 facilities. The offset is cpu-offset + (0x10000 * cpu-nr).122 reg = <0x17c10000 0x1000>;124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;138 reg = <0x0200a000 0x100>;142 cpu-offset = <0x80000>;
20 #size-cells = <0>;21 interrupts = <GIC_PPI 14 0x304>;23 cpu@0 {27 reg = <0>;52 reg = <0x0 0x0>;57 interrupts = <GIC_PPI 10 0x304>;64 #clock-cells = <0>;71 #clock-cells = <0>;78 #clock-cells = <0>;103 reg = <0x02000000 0x1000>,[all …]
27 #size-cells = <0>;29 cpu0: cpu@0 {31 reg = <0>;45 #clock-cells = <0>;66 reg = <0x02040000 0x1000>;67 arm,data-latency = <2 2 0>;76 reg = <0x02000000 0x1000>,77 <0x02002000 0x1000>;86 reg = <0x0200a000 0x100>;88 cpu-offset = <0x80000>;[all …]
23 #size-cells = <0>;25 cpu0: cpu@0 {29 reg = <0>;54 polling-delay-passive = <0>;55 polling-delay = <0>;56 thermal-sensors = <&tsens 0>;74 polling-delay-passive = <0>;75 polling-delay = <0>;94 polling-delay-passive = <0>;95 polling-delay = <0>;[all …]
25 reg = <0x80000000 0x200000>;30 reg = <0x8f000000 0x700000>;37 #size-cells = <0>;39 CPU0: cpu@0 {43 reg = <0>;100 memory@0 {102 reg = <0x0 0x0>;111 coefficients = <1199 0>;132 coefficients = <1132 0>;153 coefficients = <1199 0>;[all …]
21 #clock-cells = <0>;27 #clock-cells = <0>;33 #size-cells = <0>;35 CPU0: cpu@0 {38 reg = <0x0>;47 reg = <0x1>;55 reg = <0x2>;63 reg = <0x3>;90 reg = <0x0 0x4a600000 0x0 0x400000>;95 reg = <0x0 0x4aa00000 0x0 0x100000>;[all …]
26 #clock-cells = <0>;32 #size-cells = <0>;34 CPU0: cpu@0 {37 reg = <0x0>;48 reg = <0x1>;59 reg = <0x2>;70 reg = <0x3>;81 reg = <0x100>;92 reg = <0x101>;103 reg = <0x102>;[all …]
24 #clock-cells = <0>;30 #clock-cells = <0>;37 #size-cells = <0>;42 reg = <0x100>;56 reg = <0x101>;70 reg = <0x102>;84 reg = <0x103>;104 CPU_SLEEP_0: cpu-sleep-0 {107 arm,psci-suspend-param = <0x40000003>;161 reg = <0 0x80000000 0 0>;[all …]
25 #clock-cells = <0>;31 #clock-cells = <0>;39 #size-cells = <0>;41 CPU0: cpu@0 {44 reg = <0x0>;54 reg = <0x1>;64 reg = <0x2>;74 reg = <0x3>;84 reg = <0x100>;94 reg = <0x101>;[all …]
29 #clock-cells = <0>;35 #clock-cells = <0>;42 #size-cells = <0>;48 reg = <0x100>;66 reg = <0x101>;79 reg = <0x102>;92 reg = <0x103>;101 CPU4: cpu@0 {105 reg = <0x0>;123 reg = <0x1>;[all …]
26 reg = <0 0x80000000 0 0>;35 reg = <0x0 0x86000000 0x0 0x300000>;41 reg = <0x0 0x86300000 0x0 0x100000>;49 reg = <0x0 0x86400000 0x0 0x100000>;54 reg = <0x0 0x86500000 0x0 0x180000>;59 reg = <0x0 0x86680000 0x0 0x80000>;65 reg = <0x0 0x86700000 0x0 0xe0000>;72 reg = <0x0 0x867e0000 0x0 0x20000>;77 reg = <0x0 0x86800000 0x0 0x2b00000>;82 reg = <0x0 0x89300000 0x0 0x600000>;[all …]