Lines Matching +full:0 +full:x0200a000
25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
104 reg = <0x102>;
114 reg = <0x103>;
153 L2_0: l2-cache-0 {
180 reg = <0 0 0 0>;
198 qcom,ipc = <&apcs 8 0>;
268 reg = <0x0 0x81800000 0x0 0x2000>;
273 reg = <0x0 0x85b00000 0x0 0x800000>;
279 reg = <0x0 0x86300000 0x0 0x100000>;
286 reg = <0x0 0x86400000 0x0 0x400000>;
291 reg = <0x0 0x86c00000 0x0 0x6a00000>;
296 reg = <0x0 0x8d600000 0x0 0x1100000>;
301 reg = <0x0 0x8e700000 0x0 0x700000>;
306 reg = <0 0x90000000 0 0x1000>;
311 reg = <0x0 0x90001000 0x0 0x13ff000>;
316 reg = <0x0 0x91400000 0x0 0x700000>;
321 reg = <0x0 0x92000000 0x0 0x100000>;
327 reg = <0x0 0xf2d00000 0x0 0x180000>;
342 qcom,local-pid = <0>;
366 qcom,local-pid = <0>;
391 qcom,local-pid = <0>;
412 #size-cells = <0>;
417 apps_smsm: apps@0 {
418 reg = <0>;
440 soc: soc@0 {
443 ranges = <0 0 0 0xffffffff>;
448 reg = <0x00060000 0x8000>;
453 reg = <0x00079000 0x180>;
454 #phy-cells = <0>;
469 reg = <0x000e3000 0x1000>;
476 reg = <0x004a9000 0x1000>, /* TM */
477 <0x004a8000 0x1000>; /* SROT */
487 reg = <0x004ab000 0x4>;
492 reg = <0x01000000 0x300000>;
495 gpio-ranges = <&tlmm 0 0 142>;
763 reg = <0x01800000 0x80000>;
770 <&mdss_dsi0_phy 0>,
772 <&mdss_dsi1_phy 0>;
783 reg = <0x01905000 0x20000>;
789 reg = <0x01937000 0x30000>;
794 reg = <0x0193f044 0x4>;
800 reg = <0x01a00000 0x1000>,
801 <0x01ab0000 0x1040>;
828 reg = <0x01a01000 0x89000>;
832 interrupts = <0>;
845 iommus = <&apps_iommu 0x15>;
849 #size-cells = <0>;
851 port@0 {
852 reg = <0>;
869 reg = <0x01a94000 0x400>;
877 assigned-clock-parents = <&mdss_dsi0_phy 0>,
896 #size-cells = <0>;
902 #size-cells = <0>;
904 port@0 {
905 reg = <0>;
921 reg = <0x01a94400 0x100>,
922 <0x01a94500 0x300>,
923 <0x01a94800 0x188>;
929 #phy-cells = <0>;
939 reg = <0x01a96000 0x400>;
947 assigned-clock-parents = <&mdss_dsi1_phy 0>,
969 #size-cells = <0>;
971 port@0 {
972 reg = <0>;
988 reg = <0x01a96400 0x100>,
989 <0x01a96500 0x300>,
990 <0x01a96800 0x188>;
996 #phy-cells = <0>;
1007 ranges = <0 0x01e20000 0x20000>;
1022 reg = <0x14000 0x1000>;
1029 reg = <0x15000 0x1000>;
1036 reg = <0x16000 0x1000>;
1043 reg = <0x0200f000 0x1000>,
1044 <0x02400000 0x800000>,
1045 <0x02c00000 0x800000>,
1046 <0x03800000 0x200000>,
1047 <0x0200a000 0x2100>;
1051 qcom,ee = <0>;
1052 qcom,channel = <0>;
1057 #size-cells = <0>;
1062 reg = <0x04080000 0x100>,
1063 <0x04020000 0x040>;
1067 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1085 qcom,smem-states = <&smp2p_modem_out 0>;
1091 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1106 qcom,smd-edge = <0>;
1116 reg = <0x070f8800 0x400>;
1148 reg = <0x07000000 0xcc00>;
1157 snps,hird-threshold = /bits/ 8 <0x00>;
1166 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1182 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1226 reg = <0x07864900 0x500>, <0x07864000 0x800>;
1242 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1281 reg = <0x07884000 0x1f000>;
1287 qcom,ee = <0>;
1294 reg = <0x078af000 0x200>;
1305 reg = <0x078b5000 0x600>;
1314 pinctrl-0 = <&i2c_1_default>;
1318 #size-cells = <0>;
1325 reg = <0x078b6000 0x600>;
1334 pinctrl-0 = <&i2c_2_default>;
1338 #size-cells = <0>;
1345 reg = <0x078b7000 0x600>;
1354 pinctrl-0 = <&i2c_3_default>;
1358 #size-cells = <0>;
1365 reg = <0x078b8000 0x600>;
1374 pinctrl-0 = <&i2c_4_default>;
1378 #size-cells = <0>;
1385 reg = <0x07ac4000 0x1f000>;
1391 qcom,ee = <0>;
1398 reg = <0x07af5000 0x600>;
1407 pinctrl-0 = <&i2c_5_default>;
1411 #size-cells = <0>;
1418 reg = <0x07af6000 0x600>;
1427 pinctrl-0 = <&i2c_6_default>;
1431 #size-cells = <0>;
1438 reg = <0x07af7000 0x600>;
1447 pinctrl-0 = <&i2c_7_default>;
1451 #size-cells = <0>;
1458 reg = <0x07af8000 0x600>;
1467 pinctrl-0 = <&i2c_8_default>;
1471 #size-cells = <0>;
1478 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1484 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
1494 qcom,smem-states = <&smp2p_wcnss_out 0>;
1498 pinctrl-0 = <&wcnss_pin_a>;
1546 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1551 reg = <0x0b011000 0x1000>;
1557 reg = <0x0b120000 0x1000>;
1563 frame-number = <0>;
1566 reg = <0x0b121000 0x1000>,
1567 <0x0b122000 0x1000>;
1573 reg = <0x0b123000 0x1000>;
1580 reg = <0x0b124000 0x1000>;
1587 reg = <0x0b125000 0x1000>;
1594 reg = <0x0b126000 0x1000>;
1601 reg = <0x0b127000 0x1000>;
1608 reg = <0x0b128000 0x1000>;
1615 reg = <0x0c200000 0x100>;
1617 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1618 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1632 qcom,smem-states = <&smp2p_adsp_out 0>;
1650 #size-cells = <0>;
1663 #size-cells = <0>;
1668 qcom,sd-lines = <0 1>;
1672 qcom,sd-lines = <0 1>;
1676 qcom,sd-lines = <0>;
1692 #size-cells = <0>;
1695 dai@0 {
1696 reg = <0>;
1720 #sound-dai-cells = <0>;