Lines Matching +full:0 +full:x0200a000
26 reg = <0 0x80000000 0 0>;
35 reg = <0x0 0x86000000 0x0 0x300000>;
41 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 reg = <0x0 0x89300000 0x0 0x600000>;
87 reg = <0x0 0x89900000 0x0 0x600000>;
93 reg = <0 0x8ea00000 0 0x100000>;
100 #clock-cells = <0>;
106 #clock-cells = <0>;
113 #size-cells = <0>;
115 CPU0: cpu@0 {
118 reg = <0x0>;
133 reg = <0x1>;
148 reg = <0x2>;
163 reg = <0x3>;
184 CPU_SLEEP_0: cpu-sleep-0 {
187 arm,psci-suspend-param = <0x40000002>;
199 arm,psci-suspend-param = <0x41000012>;
207 arm,psci-suspend-param = <0x41000032>;
242 qcom,dload-mode = <&tcsr 0x6100>;
256 #power-domain-cells = <0>;
262 #power-domain-cells = <0>;
268 #power-domain-cells = <0>;
274 #power-domain-cells = <0>;
280 #power-domain-cells = <0>;
290 qcom,ipc = <&apcs 8 0>;
344 qcom,local-pid = <0>;
369 qcom,local-pid = <0>;
390 #size-cells = <0>;
395 apps_smsm: apps@0 {
396 reg = <0>;
418 soc: soc@0 {
421 ranges = <0 0 0 0xffffffff>;
426 reg = <0x00022000 0x200>;
433 reg = <0x004ab000 0x4>;
438 reg = <0x0005c000 0x1000>;
443 reg = <0xd0 0x1>;
444 bits = <0 7>;
448 reg = <0xd0 0x2>;
453 reg = <0xd1 0x2>;
458 reg = <0xd2 0x1>;
462 reg = <0xd2 0x2>;
466 reg = <0xd3 0x1>;
471 reg = <0xd4 0x1>;
472 bits = <0 5>;
478 reg = <0xd4 0x2>;
483 reg = <0xd5 0x1>;
488 reg = <0xd5 0x2>;
493 reg = <0xd6 0x2>;
498 reg = <0xd7 0x1>;
503 reg = <0xef 0x1>;
510 reg = <0x00060000 0x8000>;
515 reg = <0x00290000 0x10000>;
520 reg = <0x00400000 0x62000>;
529 reg = <0x004a9000 0x1000>, /* TM */
530 <0x004a8000 0x1000>; /* SROT */
555 reg = <0x00500000 0x11000>;
564 reg = <0x00580000 0x14000>;
573 reg = <0x00802000 0x1000>,
574 <0x09280000 0x180000>;
592 /* CTI 0 - TMC connections */
595 reg = <0x00810000 0x1000>;
606 reg = <0x00811000 0x1000>;
618 reg = <0x00820000 0x1000>;
636 reg = <0x00821000 0x1000>;
645 #size-cells = <0>;
649 * 0 - connected to Resource and Power Manger CPU ETM
684 reg = <0x00824000 0x1000>;
693 #size-cells = <0>;
695 port@0 {
696 reg = <0>;
720 reg = <0x00825000 0x1000>;
746 reg = <0x00826000 0x1000>;
764 reg = <0x00841000 0x1000>;
773 #size-cells = <0>;
775 port@0 {
776 reg = <0>;
812 reg = <0x00850000 0x1000>;
821 reg = <0x00852000 0x1000>;
830 reg = <0x00854000 0x1000>;
839 reg = <0x00856000 0x1000>;
847 /* CTI - CPU-0 */
851 reg = <0x00858000 0x1000>;
866 reg = <0x00859000 0x1000>;
881 reg = <0x0085a000 0x1000>;
896 reg = <0x0085b000 0x1000>;
909 reg = <0x0085c000 0x1000>;
930 reg = <0x0085d000 0x1000>;
951 reg = <0x0085e000 0x1000>;
972 reg = <0x0085f000 0x1000>;
993 reg = <0x01000000 0x300000>;
996 gpio-ranges = <&tlmm 0 0 122>;
1486 reg = <0x01800000 0x80000>;
1490 <&mdss_dsi0_phy 0>,
1491 <0>,
1492 <0>,
1493 <0>;
1505 reg = <0x01905000 0x20000>;
1511 reg = <0x01937000 0x30000>;
1517 reg = <0x01a00000 0x1000>,
1518 <0x01ac8000 0x3000>;
1541 reg = <0x01a01000 0x89000>;
1545 interrupts = <0>;
1560 #size-cells = <0>;
1562 port@0 {
1563 reg = <0>;
1574 reg = <0x01a98000 0x25c>;
1582 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1600 #size-cells = <0>;
1604 #size-cells = <0>;
1606 port@0 {
1607 reg = <0>;
1623 reg = <0x01a98300 0xd4>,
1624 <0x01a98500 0x280>,
1625 <0x01a98780 0x30>;
1631 #phy-cells = <0>;
1641 reg = <0x01b0ac00 0x200>,
1642 <0x01b00030 0x4>,
1643 <0x01b0b000 0x200>,
1644 <0x01b00038 0x4>,
1645 <0x01b08000 0x100>,
1646 <0x01b08400 0x100>,
1647 <0x01b0a000 0x500>,
1648 <0x01b00020 0x10>,
1649 <0x01b10000 0x1000>;
1714 #size-cells = <0>;
1716 port@0 {
1717 reg = <0>;
1729 #size-cells = <0>;
1730 reg = <0x01b0c000 0x1000>;
1742 pinctrl-0 = <&cci0_default>;
1745 cci_i2c0: i2c-bus@0 {
1746 reg = <0>;
1749 #size-cells = <0>;
1755 reg = <0x01c00000 0x20000>;
1791 reg = <0x01d00000 0xff000>;
1816 ranges = <0 0x01e20000 0x20000>;
1817 reg = <0x01ef0000 0x3000>;
1826 reg = <0x3000 0x1000>;
1833 reg = <0x4000 0x1000>;
1840 reg = <0x5000 0x1000>;
1850 ranges = <0 0x01f08000 0x10000>;
1859 reg = <0x1000 0x1000>;
1866 reg = <0x2000 0x1000>;
1873 reg = <0x0200f000 0x001000>,
1874 <0x02400000 0x400000>,
1875 <0x02c00000 0x400000>,
1876 <0x03800000 0x200000>,
1877 <0x0200a000 0x002100>;
1881 qcom,ee = <0>;
1882 qcom,channel = <0>;
1884 #size-cells = <0>;
1891 reg = <0x04044000 0x19000>;
1894 qcom,ee = <0>;
1905 reg = <0x04080000 0x100>,
1906 <0x04020000 0x040>;
1911 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1928 qcom,smem-states = <&hexagon_smp2p_out 0>;
1931 resets = <&scm 0>;
1934 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1965 qcom,smd-edge = <0>;
1978 #size-cells = <0>;
1991 reg = <0x07702000 0x4>, <0x07702004 0x4>;
2023 reg = <0x07708000 0x10000>;
2027 #size-cells = <0>;
2032 reg = <0x0771c000 0x400>;
2042 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2052 pinctrl-0 = <&sdc1_default>;
2063 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2073 pinctrl-0 = <&sdc2_default>;
2082 reg = <0x07884000 0x23000>;
2087 qcom,ee = <0>;
2093 reg = <0x078af000 0x200>;
2097 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2100 pinctrl-0 = <&blsp_uart1_default>;
2107 reg = <0x078b0000 0x200>;
2114 pinctrl-0 = <&blsp_uart2_default>;
2121 reg = <0x078b5000 0x500>;
2129 pinctrl-0 = <&blsp_i2c1_default>;
2132 #size-cells = <0>;
2138 reg = <0x078b5000 0x500>;
2146 pinctrl-0 = <&blsp_spi1_default>;
2149 #size-cells = <0>;
2155 reg = <0x078b6000 0x500>;
2163 pinctrl-0 = <&blsp_i2c2_default>;
2166 #size-cells = <0>;
2172 reg = <0x078b6000 0x500>;
2180 pinctrl-0 = <&blsp_spi2_default>;
2183 #size-cells = <0>;
2189 reg = <0x078b7000 0x500>;
2197 pinctrl-0 = <&blsp_i2c3_default>;
2200 #size-cells = <0>;
2206 reg = <0x078b7000 0x500>;
2214 pinctrl-0 = <&blsp_spi3_default>;
2217 #size-cells = <0>;
2223 reg = <0x078b8000 0x500>;
2231 pinctrl-0 = <&blsp_i2c4_default>;
2234 #size-cells = <0>;
2240 reg = <0x078b8000 0x500>;
2248 pinctrl-0 = <&blsp_spi4_default>;
2251 #size-cells = <0>;
2257 reg = <0x078b9000 0x500>;
2265 pinctrl-0 = <&blsp_i2c5_default>;
2268 #size-cells = <0>;
2274 reg = <0x078b9000 0x500>;
2282 pinctrl-0 = <&blsp_spi5_default>;
2285 #size-cells = <0>;
2291 reg = <0x078ba000 0x500>;
2299 pinctrl-0 = <&blsp_i2c6_default>;
2302 #size-cells = <0>;
2308 reg = <0x078ba000 0x500>;
2316 pinctrl-0 = <&blsp_spi6_default>;
2319 #size-cells = <0>;
2325 reg = <0x078d9000 0x200>,
2326 <0x078d9200 0x200>;
2341 ahb-burst-config = <0>;
2351 #phy-cells = <0>;
2354 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2356 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2357 <0x1 0x6b>,
2358 <0x2 0x24>,
2359 <0x3 0x13>;
2366 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2372 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2382 qcom,smem-states = <&wcnss_smp2p_out 0>;
2386 pinctrl-0 = <&wcss_wlan_default>;
2433 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2434 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2435 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2440 reg = <0x0b011000 0x1000>;
2444 #clock-cells = <0>;
2449 reg = <0x0b016000 0x40>;
2450 #clock-cells = <0>;
2460 reg = <0x0b020000 0x1000>;
2464 frame-number = <0>;
2467 reg = <0x0b021000 0x1000>,
2468 <0x0b022000 0x1000>;
2474 reg = <0x0b023000 0x1000>;
2481 reg = <0x0b024000 0x1000>;
2488 reg = <0x0b025000 0x1000>;
2495 reg = <0x0b026000 0x1000>;
2502 reg = <0x0b027000 0x1000>;
2509 reg = <0x0b028000 0x1000>;
2516 reg = <0x0b088000 0x1000>;
2521 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2522 reg = <0x0b089000 0x1000>;
2528 reg = <0x0b098000 0x1000>;
2533 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2534 reg = <0x0b099000 0x1000>;
2540 reg = <0x0b0a8000 0x1000>;
2545 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2546 reg = <0x0b0a9000 0x1000>;
2552 reg = <0x0b0b8000 0x1000>;
2557 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2558 reg = <0x0b0b9000 0x1000>;
2663 thermal-sensors = <&tsens 0>;