Lines Matching +full:0 +full:x0200a000
29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
48 reg = <0x100>;
66 reg = <0x101>;
79 reg = <0x102>;
92 reg = <0x103>;
101 CPU4: cpu@0 {
105 reg = <0x0>;
123 reg = <0x1>;
136 reg = <0x2>;
149 reg = <0x3>;
159 CPU_SLEEP_0: cpu-sleep-0 {
201 /* Boot CPU is cluster 1 core 0 */
230 qcom,dload-mode = <&tcsr 0x6100>;
237 reg = <0x0 0x80000000 0x0 0x0>;
250 qcom,ipc = <&apcs1_mbox 8 0>;
307 reg = <0x0 0x86000000 0x0 0x300000>;
313 reg = <0x0 0x86300000 0x0 0x100000>;
321 reg = <0x0 0x86400000 0x0 0x100000>;
326 reg = <0x0 0x86500000 0x0 0x180000>;
331 reg = <0x0 0x86680000 0x0 0x80000>;
337 reg = <0x0 0x86700000 0x0 0xe0000>;
344 reg = <0x0 0x867e0000 0x0 0x20000>;
349 reg = <0x0 0x86800000 0x0 0x5500000>;
354 reg = <0x0 0x8bd00000 0x0 0x600000>;
359 reg = <0x0 0x8c300000 0x0 0x800000>;
364 reg = <0x0 0x8cb00000 0x0 0x100000>;
377 qcom,local-pid = <0>;
402 qcom,local-pid = <0>;
423 #size-cells = <0>;
428 apps_smsm: apps@0 {
429 reg = <0>;
451 soc: soc@0 {
455 ranges = <0 0 0 0xffffffff>;
459 reg = <0x00022000 0x200>;
466 reg = <0x0005c000 0x1000>;
471 reg = <0xa0 0x1>;
472 bits = <0 8>;
476 reg = <0xa1 0x1>;
477 bits = <0 6>;
481 reg = <0xa1 0x2>;
486 reg = <0xa2 0x2>;
491 reg = <0xa3 0x1>;
496 reg = <0xa4 0x1>;
497 bits = <0 6>;
501 reg = <0xa4 0x2>;
506 reg = <0xa5 0x2>;
511 reg = <0xa6 0x1>;
516 reg = <0xa7 0x1>;
517 bits = <0 8>;
521 reg = <0xd0 0x1>;
522 bits = <0 3>;
526 reg = <0xd0 0x2>;
531 reg = <0xd1 0x1>;
536 reg = <0xd1 0x2>;
541 reg = <0xd2 0x2>;
546 reg = <0xd3 0x2>;
551 reg = <0xd4 0x1>;
556 reg = <0xd4 0x2>;
561 reg = <0xd5 0x2>;
566 reg = <0xd6 0x2>;
571 reg = <0xd7 0x1>;
578 reg = <0x00060000 0x8000>;
583 reg = <0x00400000 0x62000>;
592 reg = <0x004a9000 0x1000>, /* TM */
593 <0x004a8000 0x1000>; /* SROT */
624 reg = <0x004ab000 0x4>;
629 reg = <0x00500000 0x11000>;
638 reg = <0x00580000 0x14080>;
655 reg = <0x01000000 0x300000>;
658 gpio-ranges = <&tlmm 0 0 122>;
1164 reg = <0x01800000 0x80000>;
1168 <&mdss_dsi0_phy 0>,
1169 <0>,
1170 <0>,
1171 <0>;
1186 reg = <0x01905000 0x20000>;
1192 reg = <0x01937000 0x30000>;
1197 reg = <0x01a00000 0x1000>,
1198 <0x01ac8000 0x3000>;
1222 reg = <0x01a01000 0x89000>;
1226 interrupts = <0>;
1245 #size-cells = <0>;
1247 port@0 {
1248 reg = <0>;
1266 reg = <0x01a98000 0x25c>;
1286 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1293 #size-cells = <0>;
1297 #size-cells = <0>;
1299 port@0 {
1300 reg = <0>;
1316 reg = <0x01a98300 0xd4>,
1317 <0x01a98500 0x280>,
1318 <0x01a98780 0x30>;
1328 #phy-cells = <0>;
1335 reg = <0x01aa0000 0x25c>;
1355 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1362 #size-cells = <0>;
1364 port@0 {
1365 reg = <0>;
1381 reg = <0x01aa0300 0xd4>,
1382 <0x01aa0500 0x280>,
1383 <0x01aa0780 0x30>;
1393 #phy-cells = <0>;
1400 reg = <0x01c00000 0x10000>;
1449 reg = <0x01ef0000 0x3000>;
1450 ranges = <0 0x01e20000 0x20000>;
1462 reg = <0x4000 0x1000>;
1469 reg = <0x5000 0x1000>;
1476 ranges = <0 0x1f08000 0x10000>;
1489 reg = <0x1000 0x1000>;
1496 reg = <0x2000 0x1000>;
1503 reg = <0x0200f000 0x001000>,
1504 <0x02400000 0x400000>,
1505 <0x02c00000 0x400000>,
1506 <0x03800000 0x200000>,
1507 <0x0200a000 0x002100>;
1511 qcom,ee = <0>;
1512 qcom,channel = <0>;
1514 #size-cells = <0>;
1521 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1524 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1544 qcom,smem-states = <&hexagon_smp2p_out 0>;
1546 resets = <&scm 0>;
1548 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1562 qcom,smd-edge = <0>;
1572 reg = <0x07702000 0x4>,
1573 <0x07702004 0x4>;
1580 reg = <0x07708000 0x10000>;
1600 #size-cells = <0>;
1606 reg = <0x0771c000 0x400>;
1616 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1627 pinctrl-0 = <&sdc1_default>;
1638 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1649 pinctrl-0 = <&sdc2_default>;
1658 reg = <0x07884000 0x23000>;
1663 qcom,ee = <0>;
1669 reg = <0x078af000 0x200>;
1673 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1675 pinctrl-0 = <&blsp_uart1_default>;
1683 reg = <0x078b0000 0x200>;
1689 pinctrl-0 = <&blsp_uart2_default>;
1697 reg = <0x078b5000 0x500>;
1704 pinctrl-0 = <&blsp_i2c1_default>;
1708 #size-cells = <0>;
1714 reg = <0x078b5000 0x500>;
1721 pinctrl-0 = <&blsp_spi1_default>;
1725 #size-cells = <0>;
1731 reg = <0x078b6000 0x500>;
1738 pinctrl-0 = <&blsp_i2c2_default>;
1742 #size-cells = <0>;
1748 reg = <0x078b6000 0x500>;
1755 pinctrl-0 = <&blsp_spi2_default>;
1759 #size-cells = <0>;
1765 reg = <0x078b7000 0x500>;
1772 pinctrl-0 = <&blsp_i2c3_default>;
1776 #size-cells = <0>;
1782 reg = <0x078b7000 0x500>;
1789 pinctrl-0 = <&blsp_spi3_default>;
1793 #size-cells = <0>;
1799 reg = <0x078b8000 0x500>;
1806 pinctrl-0 = <&blsp_i2c4_default>;
1810 #size-cells = <0>;
1816 reg = <0x078b8000 0x500>;
1823 pinctrl-0 = <&blsp_spi4_default>;
1827 #size-cells = <0>;
1833 reg = <0x078b9000 0x500>;
1840 pinctrl-0 = <&blsp_i2c5_default>;
1844 #size-cells = <0>;
1850 reg = <0x078b9000 0x500>;
1857 pinctrl-0 = <&blsp_spi5_default>;
1861 #size-cells = <0>;
1867 reg = <0x078ba000 0x500>;
1874 pinctrl-0 = <&blsp_i2c6_default>;
1878 #size-cells = <0>;
1884 reg = <0x078ba000 0x500>;
1891 pinctrl-0 = <&blsp_spi6_default>;
1895 #size-cells = <0>;
1901 reg = <0x078d9000 0x200>,
1902 <0x078d9200 0x200>;
1918 ahb-burst-config = <0>;
1930 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1932 #phy-cells = <0>;
1933 qcom,init-seq = /bits/ 8 <0x0 0x44>,
1934 <0x1 0x6b>,
1935 <0x2 0x24>,
1936 <0x3 0x13>;
1944 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1953 reg = <0x0a204000 0x2000>,
1954 <0x0a202000 0x1000>,
1955 <0x0a21b000 0x3000>;
1964 qcom,smem-states = <&wcnss_smp2p_out 0>;
1968 pinctrl-0 = <&wcss_wlan_default>;
2014 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2015 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2018 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2023 reg = <0x0b011000 0x1000>;
2026 #clock-cells = <0>;
2034 reg = <0x0b016000 0x40>;
2035 #clock-cells = <0>;
2040 reg = <0x0b088000 0x1000>;
2044 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2045 reg = <0x0b089000 0x1000>;
2050 reg = <0x0b098000 0x1000>;
2054 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2055 reg = <0x0b099000 0x1000>;
2060 reg = <0x0b0a8000 0x1000>;
2064 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2065 reg = <0x0b0a9000 0x1000>;
2070 reg = <0x0b0b8000 0x1000>;
2074 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2075 reg = <0x0b0b9000 0x1000>;
2080 reg = <0x0b111000 0x1000>;
2083 #clock-cells = <0>;
2089 reg = <0x0b116000 0x40>;
2090 #clock-cells = <0>;
2095 reg = <0x0b120000 0x1000>;
2101 reg = <0x0b121000 0x1000>,
2102 <0x0b122000 0x1000>;
2105 frame-number = <0>;
2109 reg = <0x0b123000 0x1000>;
2116 reg = <0x0b124000 0x1000>;
2123 reg = <0x0b125000 0x1000>;
2130 reg = <0x0b126000 0x1000>;
2137 reg = <0x0b127000 0x1000>;
2144 reg = <0x0b128000 0x1000>;
2153 reg = <0x0b188000 0x1000>;
2157 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2158 reg = <0x0b189000 0x1000>;
2163 reg = <0x0b198000 0x1000>;
2167 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2168 reg = <0x0b199000 0x1000>;
2173 reg = <0x0b1a8000 0x1000>;
2177 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2178 reg = <0x0b1a9000 0x1000>;
2183 reg = <0x0b1b8000 0x1000>;
2187 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2188 reg = <0x0b1b9000 0x1000>;
2193 reg = <0x0b1d0000 0x40>;
2194 #clock-cells = <0>;
2199 reg = <0x0b1d1000 0x1000>;
2202 #clock-cells = <0>;
2223 hysteresis = <0>;
2388 thermal-sensors = <&tsens 0>;