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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dqcom,i2c-geni-qcom.yaml51 pinctrl-0: true
131 reg = <0x00880000 0x4000>;
135 pinctrl-0 = <&qup_i2c0_default>;
138 #size-cells = <0>;
139 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-geni-qcom.yaml87 reg = <0x00880000 0x4000>;
91 pinctrl-0 = <&qup_spi0_default>;
94 #size-cells = <0>;
97 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
98 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
107 reg = <0x00884000 0x4000>;
110 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
114 pinctrl-0 = <&qup_spi1_default>;
117 #size-cells = <0>;
/openbmc/linux/drivers/hid/
H A Dhid-ite.c14 #define QUIRK_TOUCHPAD_ON_OFF_REPORT BIT(0)
22 if (*rsize == 188 && rdesc[162] == 0x81 && rdesc[163] == 0x02) { in ite_report_fixup()
27 if (*rsize == 188 && rdesc[185] == 0x81 && rdesc[186] == 0x02) { in ite_report_fixup()
32 if (*rsize == 210 && rdesc[184] == 0x81 && rdesc[185] == 0x02) { in ite_report_fixup()
50 (usage->hid & HID_USAGE_PAGE) == 0x00880000) { in ite_input_mapping()
51 if (usage->hid == 0x00880078) { in ite_input_mapping()
56 if (usage->hid == 0x00880079) { in ite_input_mapping()
64 return 0; in ite_input_mapping()
73 return 0; in ite_event()
78 * The ITE8595 always reports 0 as value for the rfkill button. Luckily in ite_event()
[all …]
/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg20 ; |------24|------16|-------8|-------0|
24 ;PLL0CFG0 = 0x00180001
25 ;PLL0CFG1 = 0x00000205
28 PLL0CFG0 = 0x00180001
29 PLL0CFG1 = 0x00000205
30 PERIPHCLKCFG = 0x00000051
35 ; |------24|------16|-------8|-------0|
39 PLL1CFG0 = 0x18010001
40 PLL1CFG1 = 0x00000002
46 ; SPI: |------24|------16|-------8|-------0|
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h11 #define CONFIG_SYS_IMMR 0x01000000
12 #define CONFIG_SYS_DCSRBAR 0x20000000
13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
[all …]
/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_ops.c26 0,
27 0,
28 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
29 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
30 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
31 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
32 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
33 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
34 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
35 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_plat.c15 * 1. L2 filter should be set at binary header to 0xD000000,
17 * 2. U-Boot modifies internal registers base to 0xf100000,
18 * and than should update L2 filter accordingly to 0xf000000 (3.75 GB)
20 #define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xC0000000 /* temporary limit l2 filter to 3gb (LSP issue) */
21 #define ADDRESS_FILTERING_END_REGISTER 0x8c04
27 #define TSEN_CONTROL_LSB_REG 0xE4070
28 #define TSEN_CONTROL_LSB_TC_TRIM_OFFSET 0
29 #define TSEN_CONTROL_LSB_TC_TRIM_MASK (0x7 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET)
30 #define TSEN_CONTROL_MSB_REG 0xE4074
32 #define TSEN_CONTROL_MSB_RST_MASK (0x1 << TSEN_CONTROL_MSB_RST_OFFSET)
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8180x.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 CPU0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm670.dtsi32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0 0x0>;
41 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
86 reg = <0x0 0x200>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x300>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_combios.c134 uint16_t offset = 0, check_offset; in combios_get_table_offset()
137 return 0; in combios_get_table_offset()
142 check_offset = 0xc; in combios_get_table_offset()
145 check_offset = 0x14; in combios_get_table_offset()
148 check_offset = 0x2a; in combios_get_table_offset()
151 check_offset = 0x2c; in combios_get_table_offset()
154 check_offset = 0x2e; in combios_get_table_offset()
157 check_offset = 0x30; in combios_get_table_offset()
160 check_offset = 0x32; in combios_get_table_offset()
163 check_offset = 0x34; in combios_get_table_offset()
[all …]
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/openbmc/qemu/include/
H A Delf.h22 #define PT_NULL 0
29 #define PT_LOOS 0x60000000
30 #define PT_HIOS 0x6fffffff
31 #define PT_LOPROC 0x70000000
32 #define PT_HIPROC 0x7fffffff
34 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
35 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
37 #define PT_MIPS_REGINFO 0x70000000
38 #define PT_MIPS_RTPROC 0x70000001
39 #define PT_MIPS_OPTIONS 0x70000002
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv50.c23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
[all …]