Lines Matching +full:0 +full:x00880000
22 #define PT_NULL 0
29 #define PT_LOOS 0x60000000
30 #define PT_HIOS 0x6fffffff
31 #define PT_LOPROC 0x70000000
32 #define PT_HIPROC 0x7fffffff
34 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
35 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
37 #define PT_MIPS_REGINFO 0x70000000
38 #define PT_MIPS_RTPROC 0x70000001
39 #define PT_MIPS_OPTIONS 0x70000002
40 #define PT_MIPS_ABIFLAGS 0x70000003
44 #define EF_MIPS_ARCH 0xf0000000
47 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
48 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
49 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
50 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
51 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
52 #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
53 #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
54 #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */
55 #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */
56 #define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
57 #define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
60 #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
61 #define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */
63 #define EF_MIPS_NOREORDER 0x00000001
64 #define EF_MIPS_PIC 0x00000002
65 #define EF_MIPS_CPIC 0x00000004
66 #define EF_MIPS_ABI2 0x00000020
67 #define EF_MIPS_OPTIONS_FIRST 0x00000080
68 #define EF_MIPS_32BITMODE 0x00000100
69 #define EF_MIPS_ABI 0x0000f000
70 #define EF_MIPS_FP64 0x00000200
71 #define EF_MIPS_NAN2008 0x00000400
74 #define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */
75 #define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */
76 #define EF_MIPS_MACH_4010 0x00820000 /* LSI R4010 */
77 #define EF_MIPS_MACH_4100 0x00830000 /* NEC VR4100 */
78 #define EF_MIPS_MACH_4650 0x00850000 /* MIPS R4650 */
79 #define EF_MIPS_MACH_4120 0x00870000 /* NEC VR4120 */
80 #define EF_MIPS_MACH_4111 0x00880000 /* NEC VR4111/VR4181 */
81 #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
82 #define EF_MIPS_MACH_OCTEON 0x008b0000 /* Cavium Networks Octeon */
83 #define EF_MIPS_MACH_XLR 0x008c0000 /* RMI Xlr */
84 #define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */
85 #define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */
86 #define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */
87 #define EF_MIPS_MACH_5900 0x00920000 /* Toshiba/Sony R5900 */
88 #define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */
89 #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */
90 #define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */
91 #define EF_MIPS_MACH_LS2F 0x00a10000 /* ST Microelectronics Loongson 2F */
92 #define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
93 #define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
97 #define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */
98 #define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
99 #define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */
100 #define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */
101 #define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */
102 #define MIPS_ABI_FP_XX 0x5 /* -mfpxx */
103 #define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
104 #define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
110 /* - 0 for MIPS V and below, */
123 #define ET_NONE 0
128 #define ET_LOPROC 0xff00
129 #define ET_HIPROC 0xffff
132 #define EM_NONE 0
192 #define EM_ALPHA 0x9026
195 #define EM_CYGNUS_V850 0x9080
200 #define EM_S390_OLD 0xA390
205 #define EM_MICROBLAZE_OLD 0xBAAB
211 #define EF_AVR_MACH 0x7F /* Mask for AVR e_flags to get core type */
214 #define DT_NULL 0
245 #define DT_LOOS 0x6000000d
246 #define DT_HIOS 0x6ffff000
247 #define DT_LOPROC 0x70000000
248 #define DT_HIPROC 0x7fffffff
252 #define DT_VALRNGLO 0x6ffffd00
253 #define DT_VALRNGHI 0x6ffffdff
257 #define DT_ADDRRNGLO 0x6ffffe00
258 #define DT_ADDRRNGHI 0x6ffffeff
260 #define DT_VERSYM 0x6ffffff0
261 #define DT_RELACOUNT 0x6ffffff9
262 #define DT_RELCOUNT 0x6ffffffa
263 #define DT_FLAGS_1 0x6ffffffb
264 #define DT_VERDEF 0x6ffffffc
265 #define DT_VERDEFNUM 0x6ffffffd
266 #define DT_VERNEED 0x6ffffffe
267 #define DT_VERNEEDNUM 0x6fffffff
269 #define DT_MIPS_RLD_VERSION 0x70000001
270 #define DT_MIPS_TIME_STAMP 0x70000002
271 #define DT_MIPS_ICHECKSUM 0x70000003
272 #define DT_MIPS_IVERSION 0x70000004
273 #define DT_MIPS_FLAGS 0x70000005
274 #define RHF_NONE 0
277 #define DT_MIPS_BASE_ADDRESS 0x70000006
278 #define DT_MIPS_CONFLICT 0x70000008
279 #define DT_MIPS_LIBLIST 0x70000009
280 #define DT_MIPS_LOCAL_GOTNO 0x7000000a
281 #define DT_MIPS_CONFLICTNO 0x7000000b
282 #define DT_MIPS_LIBLISTNO 0x70000010
283 #define DT_MIPS_SYMTABNO 0x70000011
284 #define DT_MIPS_UNREFEXTNO 0x70000012
285 #define DT_MIPS_GOTSYM 0x70000013
286 #define DT_MIPS_HIPAGENO 0x70000014
287 #define DT_MIPS_RLD_MAP 0x70000016
290 #define STB_LOCAL 0
294 #define STT_NOTYPE 0
301 #define ELF_ST_TYPE(x) (((unsigned int) x) & 0xf)
302 #define ELF_ST_INFO(bind, type) (((bind) << 4) | ((type) & 0xf))
310 #define AT_NULL 0 /* end of vector */
341 #define AT_L1D_CACHESHAPE 35 /* bits 0-3: cache associativity. */
363 #define ELF32_R_TYPE(x) ((x) & 0xff)
366 #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
367 #define ELF64_R_TYPE_DATA(i) (((ELF64_R_TYPE(i) >> 8) ^ 0x00800000) - 0x00800000)
369 #define R_386_NONE 0
384 #define R_MIPS_NONE 0
438 #define EF_SPARCV9_TSO 0
441 #define EF_SPARC_LEDATA 0x800000 /* little endian data */
442 #define EF_SPARC_EXT_MASK 0xFFFF00
443 #define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */
444 #define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */
445 #define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */
446 #define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */
451 #define R_SPARC_NONE 0
496 #define HWCAP_ARM_SWP (1 << 0)
521 #define PPC_FEATURE_32 0x80000000
522 #define PPC_FEATURE_64 0x40000000
523 #define PPC_FEATURE_601_INSTR 0x20000000
524 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
525 #define PPC_FEATURE_HAS_FPU 0x08000000
526 #define PPC_FEATURE_HAS_MMU 0x04000000
527 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
528 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
529 #define PPC_FEATURE_HAS_SPE 0x00800000
530 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
531 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
532 #define PPC_FEATURE_NO_TB 0x00100000
533 #define PPC_FEATURE_POWER4 0x00080000
534 #define PPC_FEATURE_POWER5 0x00040000
535 #define PPC_FEATURE_POWER5_PLUS 0x00020000
536 #define PPC_FEATURE_CELL 0x00010000
537 #define PPC_FEATURE_BOOKE 0x00008000
538 #define PPC_FEATURE_SMT 0x00004000
539 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
540 #define PPC_FEATURE_ARCH_2_05 0x00001000
541 #define PPC_FEATURE_PA6T 0x00000800
542 #define PPC_FEATURE_HAS_DFP 0x00000400
543 #define PPC_FEATURE_POWER6_EXT 0x00000200
544 #define PPC_FEATURE_ARCH_2_06 0x00000100
545 #define PPC_FEATURE_HAS_VSX 0x00000080
548 0x00000040
550 #define PPC_FEATURE_TRUE_LE 0x00000002
551 #define PPC_FEATURE_PPC_LE 0x00000001
555 #define PPC_FEATURE2_ARCH_2_07 0x80000000
556 #define PPC_FEATURE2_HAS_HTM 0x40000000
557 #define PPC_FEATURE2_HAS_DSCR 0x20000000
558 #define PPC_FEATURE2_HAS_EBB 0x10000000
559 #define PPC_FEATURE2_HAS_ISEL 0x08000000
560 #define PPC_FEATURE2_HAS_TAR 0x04000000
561 #define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000
562 #define PPC_FEATURE2_HTM_NOSC 0x01000000
563 #define PPC_FEATURE2_ARCH_3_00 0x00800000
564 #define PPC_FEATURE2_HAS_IEEE128 0x00400000
565 #define PPC_FEATURE2_ARCH_3_10 0x00040000
569 #define HWCAP_SPARC_FLUSH 0x00000001
570 #define HWCAP_SPARC_STBAR 0x00000002
571 #define HWCAP_SPARC_SWAP 0x00000004
572 #define HWCAP_SPARC_MULDIV 0x00000008
573 #define HWCAP_SPARC_V9 0x00000010
574 #define HWCAP_SPARC_ULTRA3 0x00000020
575 #define HWCAP_SPARC_BLKINIT 0x00000040
576 #define HWCAP_SPARC_N2 0x00000080
577 #define HWCAP_SPARC_MUL32 0x00000100
578 #define HWCAP_SPARC_DIV32 0x00000200
579 #define HWCAP_SPARC_FSMULD 0x00000400
580 #define HWCAP_SPARC_V8PLUS 0x00000800
581 #define HWCAP_SPARC_POPC 0x00001000
582 #define HWCAP_SPARC_VIS 0x00002000
583 #define HWCAP_SPARC_VIS2 0x00004000
584 #define HWCAP_SPARC_ASI_BLK_INIT 0x00008000
585 #define HWCAP_SPARC_FMAF 0x00010000
586 #define HWCAP_SPARC_VIS3 0x00020000
587 #define HWCAP_SPARC_HPC 0x00040000
588 #define HWCAP_SPARC_RANDOM 0x00080000
589 #define HWCAP_SPARC_TRANS 0x00100000
590 #define HWCAP_SPARC_FJFMAU 0x00200000
591 #define HWCAP_SPARC_IMA 0x00400000
592 #define HWCAP_SPARC_ASI_CACHE_SPARING 0x00800000
593 #define HWCAP_SPARC_PAUSE 0x01000000
594 #define HWCAP_SPARC_CBCOND 0x02000000
595 #define HWCAP_SPARC_CRYPTO 0x04000000
599 #define HWCAP_S390_NR_ESAN3 0
650 #define EF_M68K_CPU32 0x00810000
651 #define EF_M68K_M68000 0x01000000
652 #define EF_M68K_CFV4E 0x00008000
653 #define EF_M68K_FIDO 0x02000000
659 either 0 or EF_M68K_CFV4E. */
660 #define EF_M68K_CF_ISA_MASK 0x0F /* Which ISA */
661 #define EF_M68K_CF_ISA_A_NODIV 0x01 /* ISA A except for div */
662 #define EF_M68K_CF_ISA_A 0x02
663 #define EF_M68K_CF_ISA_A_PLUS 0x03
664 #define EF_M68K_CF_ISA_B_NOUSP 0x04 /* ISA_B except for USP */
665 #define EF_M68K_CF_ISA_B 0x05
666 #define EF_M68K_CF_ISA_C 0x06
667 #define EF_M68K_CF_ISA_C_NODIV 0x07 /* ISA C except for div */
668 #define EF_M68K_CF_MAC_MASK 0x30
669 #define EF_M68K_CF_MAC 0x10 /* MAC */
670 #define EF_M68K_CF_EMAC 0x20 /* EMAC */
671 #define EF_M68K_CF_EMAC_B 0x30 /* EMAC_B */
672 #define EF_M68K_CF_FLOAT 0x40 /* Has float insns */
673 #define EF_M68K_CF_MASK 0xFF
678 #define R_68K_NONE 0
705 #define R_ALPHA_NONE 0 /* No reloc */
739 #define SHF_ALPHA_GPREL 0x10000000
745 #define EF_PPC64_ABI 0x3
748 #define R_PPC_NONE 0
793 #define EF_ARM_RELEXEC 0x01
794 #define EF_ARM_HASENTRY 0x02
795 #define EF_ARM_INTERWORK 0x04
796 #define EF_ARM_APCS_26 0x08
797 #define EF_ARM_APCS_FLOAT 0x10
798 #define EF_ARM_PIC 0x20
799 #define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */
800 #define EF_NEW_ABI 0x80
801 #define EF_OLD_ABI 0x100
802 #define EF_ARM_SOFT_FLOAT 0x200
803 #define EF_ARM_VFP_FLOAT 0x400
804 #define EF_ARM_MAVERICK_FLOAT 0x800
807 #define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */
808 #define EF_ARM_DYNSYMSUSESEGIDX 0x08 /* NB conflicts with EF_APCS26 */
809 #define EF_ARM_MAPSYMSFIRST 0x10 /* NB conflicts with EF_APCS_FLOAT */
810 #define EF_ARM_EABIMASK 0xFF000000
813 #define EF_ARM_BE8 0x00800000
814 #define EF_ARM_LE8 0x00400000
817 #define EF_ARM_EABI_UNKNOWN 0x00000000
818 #define EF_ARM_EABI_VER1 0x01000000
819 #define EF_ARM_EABI_VER2 0x02000000
820 #define EF_ARM_EABI_VER3 0x03000000
821 #define EF_ARM_EABI_VER4 0x04000000
822 #define EF_ARM_EABI_VER5 0x05000000
825 #define STT_ARM_TFUNC 0xd
828 #define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
829 #define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined
833 #define PF_ARM_SB 0x10000000 /* Segment contains the location
837 #define R_ARM_NONE 0 /* No reloc */
879 #define R_AARCH64_NONE 256 /* also accepts R_ARM_NONE (0) */
1006 #define R_390_NONE 0 /* No reloc. */
1085 #define R_X86_64_NONE 0 /* No reloc */
1113 #define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */
1114 #define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */
1115 #define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
1116 #define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
1117 #define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch
1119 #define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
1120 #define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
1124 #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
1125 #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
1126 #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
1130 #define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declared
1132 #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
1136 #define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */
1137 #define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */
1138 #define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */
1142 #define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */
1143 #define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */
1144 #define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */
1150 #define STT_HP_OPAQUE (STT_LOOS + 0x1)
1151 #define STT_HP_STUB (STT_LOOS + 0x2)
1155 #define R_PARISC_NONE 0 /* No reloc. */
1246 #define PT_HP_TLS (PT_LOOS + 0x0)
1247 #define PT_HP_CORE_NONE (PT_LOOS + 0x1)
1248 #define PT_HP_CORE_VERSION (PT_LOOS + 0x2)
1249 #define PT_HP_CORE_KERNEL (PT_LOOS + 0x3)
1250 #define PT_HP_CORE_COMM (PT_LOOS + 0x4)
1251 #define PT_HP_CORE_PROC (PT_LOOS + 0x5)
1252 #define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6)
1253 #define PT_HP_CORE_STACK (PT_LOOS + 0x7)
1254 #define PT_HP_CORE_SHM (PT_LOOS + 0x8)
1255 #define PT_HP_CORE_MMF (PT_LOOS + 0x9)
1256 #define PT_HP_PARALLEL (PT_LOOS + 0x10)
1257 #define PT_HP_FASTBIND (PT_LOOS + 0x11)
1258 #define PT_HP_OPT_ANNOT (PT_LOOS + 0x12)
1259 #define PT_HP_HSL_ANNOT (PT_LOOS + 0x13)
1260 #define PT_HP_STACK (PT_LOOS + 0x14)
1262 #define PT_PARISC_ARCHEXT 0x70000000
1263 #define PT_PARISC_UNWIND 0x70000001
1267 #define PF_PARISC_SBP 0x08000000
1269 #define PF_HP_PAGE_SIZE 0x00100000
1270 #define PF_HP_FAR_SHARED 0x00200000
1271 #define PF_HP_NEAR_SHARED 0x00400000
1272 #define PF_HP_CODE 0x01000000
1273 #define PF_HP_MODIFY 0x02000000
1274 #define PF_HP_LAZYSWAP 0x04000000
1275 #define PF_HP_SBP 0x08000000
1280 #define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
1281 #define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */
1282 #define EF_IA_64_ARCH 0xff000000 /* arch. version mask */
1285 #define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */
1289 #define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */
1292 #define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */
1296 #define SHF_IA_64_SHORT 0x10000000 /* section near gp */
1297 #define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */
1300 #define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
1304 #define R_IA64_NONE 0x00 /* none */
1305 #define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */
1306 #define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */
1307 #define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */
1308 #define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */
1309 #define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */
1310 #define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */
1311 #define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */
1312 #define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */
1313 #define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */
1314 #define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */
1315 #define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */
1316 #define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */
1317 #define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */
1318 #define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */
1319 #define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */
1320 #define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */
1321 #define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */
1322 #define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */
1323 #define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */
1324 #define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */
1325 #define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */
1326 #define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */
1327 #define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */
1328 #define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */
1329 #define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */
1330 #define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */
1331 #define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */
1332 #define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */
1333 #define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */
1334 #define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */
1335 #define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */
1336 #define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */
1337 #define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */
1338 #define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */
1339 #define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */
1340 #define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */
1341 #define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */
1342 #define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */
1343 #define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */
1344 #define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */
1345 #define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */
1346 #define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */
1347 #define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */
1348 #define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */
1349 #define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */
1350 #define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */
1351 #define R_IA64_REL32MSB 0x6c /* data 4 + REL */
1352 #define R_IA64_REL32LSB 0x6d /* data 4 + REL */
1353 #define R_IA64_REL64MSB 0x6e /* data 8 + REL */
1354 #define R_IA64_REL64LSB 0x6f /* data 8 + REL */
1355 #define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */
1356 #define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */
1357 #define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */
1358 #define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */
1359 #define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */
1360 #define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */
1361 #define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */
1362 #define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */
1363 #define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */
1364 #define R_IA64_COPY 0x84 /* copy relocation */
1365 #define R_IA64_SUB 0x85 /* Addend and symbol difference */
1366 #define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
1367 #define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */
1368 #define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */
1369 #define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */
1370 #define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */
1371 #define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */
1372 #define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */
1373 #define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */
1374 #define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */
1375 #define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */
1376 #define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */
1377 #define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */
1378 #define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */
1379 #define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */
1380 #define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */
1381 #define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */
1382 #define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */
1383 #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
1384 #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
1387 #define R_RISCV_NONE 0
1442 #define EF_RISCV_RVC 0x0001
1443 #define EF_RISCV_FLOAT_ABI 0x0006
1444 #define EF_RISCV_FLOAT_ABI_SOFT 0x0000
1445 #define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
1446 #define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
1447 #define EF_RISCV_FLOAT_ABI_QUAD 0x0006
1448 #define EF_RISCV_RVE 0x0008
1449 #define EF_RISCV_TSO 0x0010
1485 unsigned char st_other; /* No defined meaning, 0 */
1496 value is in the field sh_info of section 0. */
1497 #define PN_XNUM 0xffff
1535 #define PF_R 0x4
1536 #define PF_W 0x2
1537 #define PF_X 0x1
1562 #define SHT_NULL 0
1575 #define SHT_LOPROC 0x70000000
1576 #define SHT_HIPROC 0x7fffffff
1577 #define SHT_LOUSER 0x80000000
1578 #define SHT_HIUSER 0xffffffff
1579 #define SHT_MIPS_LIST 0x70000000
1580 #define SHT_MIPS_CONFLICT 0x70000002
1581 #define SHT_MIPS_GPTAB 0x70000003
1582 #define SHT_MIPS_UCODE 0x70000004
1585 #define SHF_WRITE 0x1
1586 #define SHF_ALLOC 0x2
1587 #define SHF_EXECINSTR 0x4
1588 #define SHF_MASKPROC 0xf0000000
1589 #define SHF_MIPS_GPREL 0x10000000
1592 #define SHN_UNDEF 0
1593 #define SHN_LORESERVE 0xff00
1594 #define SHN_LOPROC 0xff00
1595 #define SHN_HIPROC 0xff1f
1596 #define SHN_ABS 0xfff1
1597 #define SHN_COMMON 0xfff2
1598 #define SHN_HIRESERVE 0xffff
1599 #define SHN_MIPS_ACCOMON 0xff00
1627 #define EI_MAG0 0 /* e_ident[] indexes */
1637 #define ELFOSABI_NONE 0 /* UNIX System V ABI */
1638 #define ELFOSABI_SYSV 0 /* Alias. */
1654 #define ELFMAG0 0x7f /* EI_MAG */
1661 #define ELFCLASSNONE 0 /* EI_CLASS */
1666 #define ELFDATANONE 0 /* e_ident[EI_DATA] */
1670 #define EV_NONE 0 /* e_version, EI_VERSION */
1681 #define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */
1682 #define NT_S390_PV_CPU_DATA 0x30e /* s390 protvirt cpu dump data */
1683 #define NT_S390_RI_CB 0x30d /* s390 runtime instrumentation */
1684 #define NT_S390_GS_CB 0x30b /* s390 guarded storage registers */
1685 #define NT_S390_VXRS_HIGH 0x30a /* s390 vector registers 16-31 */
1686 #define NT_S390_VXRS_LOW 0x309 /* s390 vector registers 0-15 (lower half) */
1687 #define NT_S390_PREFIX 0x305 /* s390 prefix register */
1688 #define NT_S390_CTRS 0x304 /* s390 control registers */
1689 #define NT_S390_TODPREG 0x303 /* s390 TOD programmable register */
1690 #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */
1691 #define NT_S390_TIMER 0x301 /* s390 timer register */
1692 #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
1693 #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
1694 #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
1695 #define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */
1696 #define NT_ARM_TLS 0x401 /* ARM TLS register */
1697 #define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */
1698 #define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */
1699 #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
1700 #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
1711 #define GNU_PROPERTY_LOPROC 0xc0000000
1712 #define GNU_PROPERTY_HIPROC 0xdfffffff
1713 #define GNU_PROPERTY_LOUSER 0xe0000000
1714 #define GNU_PROPERTY_HIUSER 0xffffffff
1716 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
1717 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
1729 #define XEN_ELFNOTE_PHYS32_ENTRY 18 /* 0x12 */