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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmpc8349_pci.h5 #define M8265_PCIBR0 0x101ac
6 #define M8265_PCIBR1 0x101b0
7 #define M8265_PCIMSK0 0x101c4
8 #define M8265_PCIMSK1 0x101c8
12 #define PCIBR_ENABLE 0x00000001
16 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
17 #define PCIMSK_64KB 0xFFFF0000
18 #define PCIMSK_128KB 0xFFFE0000
19 #define PCIMSK_256KB 0xFFFC0000
20 #define PCIMSK_512KB 0xFFF80000
[all …]
/openbmc/qemu/include/hw/i386/
H A Dapic-msidef.h12 #define MSI_DATA_VECTOR_SHIFT 0
13 #define MSI_DATA_VECTOR_MASK 0x000000ff
29 #define MSI_ADDR_DEST_ID_MASK 0x000ff000
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_mmu.S6 #define BASE 0x20000000
7 #define TLB_BASE 0x80000000
23 clean_tlb_way 0, 0x00001000, 4
24 clean_tlb_way 1, 0x00001000, 4
25 clean_tlb_way 2, 0x00001000, 4
26 clean_tlb_way 3, 0x00001000, 4
27 clean_tlb_way 4, 0x00100000, 4
28 movi a2, 0x00000007
30 movi a2, 0x00000008
32 movi a2, 0x00000009
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/
H A Dcpu.c28 /* enable watchdog, set timeout to 0 and wait */ in do_reset()
40 u16 id = 0; in print_cpuinfo()
44 switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) { in print_cpuinfo()
45 case 0x0C: in print_cpuinfo()
48 case 0x0D: in print_cpuinfo()
51 case 0x0E: in print_cpuinfo()
54 case 0x0F: in print_cpuinfo()
57 case 0x10: in print_cpuinfo()
60 case 0x11: in print_cpuinfo()
63 case 0x12: in print_cpuinfo()
[all …]
/openbmc/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_acc.c17 u32 hi = 0, lo = value; in pci_acc_write_reg()
23 lo |= (0x03 << 8); in pci_acc_write_reg()
25 lo &= ~(0x03 << 8); in pci_acc_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_acc_write_reg()
42 } else if (value & 0x01) { in pci_acc_write_reg()
43 value &= 0xfffffffc; in pci_acc_write_reg()
44 hi = 0xA0000000 | ((value & 0x000ff000) >> 12); in pci_acc_write_reg()
45 lo = 0x000fff80 | ((value & 0x00000fff) << 20); in pci_acc_write_reg()
52 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); in pci_acc_write_reg()
65 u32 conf_data = 0; in pci_acc_read_reg()
[all …]
H A Dcs5536_ide.c17 u32 hi = 0, lo = value; in pci_ide_write_reg()
23 lo |= (0x03 << 4); in pci_ide_write_reg()
25 lo &= ~(0x03 << 4); in pci_ide_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
40 hi &= 0xffffff00; in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
55 hi = 0x60000000 | ((value & 0x000ff000) >> 12); in pci_ide_write_reg()
[all …]
/openbmc/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/qemu/hw/pci-host/
H A Dastro.c94 case 0x0008: in elroy_chip_read_with_attrs()
95 val = 0x6000005; /* func_class */ in elroy_chip_read_with_attrs()
97 case 0x0058: in elroy_chip_read_with_attrs()
106 case 0x0080: in elroy_chip_read_with_attrs()
109 case 0x0108: in elroy_chip_read_with_attrs()
112 case 0x200 ... 0x250 - 1: /* LMMIO, GMMIO, WLMMIO, WGMMIO, ... */ in elroy_chip_read_with_attrs()
113 index = (addr - 0x200) / 8; in elroy_chip_read_with_attrs()
116 case 0x0680: in elroy_chip_read_with_attrs()
119 case 0x0688: in elroy_chip_read_with_attrs()
120 val = 0; /* ERROR_STATUS */ in elroy_chip_read_with_attrs()
[all …]
/openbmc/linux/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
[all …]
/openbmc/u-boot/include/
H A Dfsl_ifc.h17 #define FSL_IFC_V1_1_0 0x01010000
18 #define FSL_IFC_V2_0_0 0x02000000
38 #define CSPR_BA 0xFFFF0000
40 #define CSPR_PORT_SIZE 0x00000180
43 #define CSPR_PORT_SIZE_8 0x00000080
45 #define CSPR_PORT_SIZE_16 0x00000100
47 #define CSPR_PORT_SIZE_32 0x00000180
49 #define CSPR_WP 0x00000040
52 #define CSPR_MSEL 0x00000006
55 #define CSPR_MSEL_NOR 0x00000000
[all …]
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dda850-evm.dts32 pinctrl-0 = <&ecap2_pins>;
40 pwms = <&ecap2 0 50000 0>;
41 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
48 pinctrl-0 = <&lcd_pins>;
59 ac-bias-intrpt = <0>;
62 fdd = <0x80>;
63 sync-edge = <0>;
65 raster-order = <0>;
66 fifo-th = <0>;
81 hsync-active = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/openbmc/linux/drivers/parisc/
H A Diosapic.c161 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
164 #define IOSAPIC_REG_SELECT 0x00
165 #define IOSAPIC_REG_WINDOW 0x10
166 #define IOSAPIC_REG_EOI 0x40
168 #define IOSAPIC_REG_VERSION 0x1
170 #define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
171 #define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
185 #define IOSAPIC_VERSION_MASK 0x000000ff
188 #define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
189 #define IOSAPIC_MAX_ENTRY_SHIFT 0x10
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h11 #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
12 #define IRAM_SIZE 0x00080000 /* 512 KB */
14 #define AIPS0_BASE_ADDR 0x40000000
15 #define AIPS1_BASE_ADDR 0x40080000
17 /* AIPS 0 */
18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
[all …]
/openbmc/linux/drivers/nvmem/
H A Dimx-ocotp.c27 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
30 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
34 #define IMX_OCOTP_ADDR_CTRL 0x0000
35 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
36 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
37 #define IMX_OCOTP_ADDR_TIMING 0x0010
38 #define IMX_OCOTP_ADDR_DATA0 0x0020
39 #define IMX_OCOTP_ADDR_DATA1 0x0030
40 #define IMX_OCOTP_ADDR_DATA2 0x0040
41 #define IMX_OCOTP_ADDR_DATA3 0x0050
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dpxa168fb.h6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
[all …]

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