Lines Matching +full:0 +full:x000ff000

32 		pinctrl-0 = <&ecap2_pins>;
40 		pwms = <&ecap2 0 50000 0>;
41 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
48 		pinctrl-0 = <&lcd_pins>;
59 			ac-bias-intrpt	= <0>;
62 			fdd		= <0x80>;
63 			sync-edge	= <0>;
65 			raster-order	= <0>;
66 			fifo-th		= <0>;
81 				hsync-active = <0>;
82 				vsync-active = <0>;
173 			0x00 0x11111111 0xffffffff
175 			0x04 0x00011000 0x000ff000
180 			/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
181 			0x1c 0x10110110  0xf0ff0ff0
183 			 * EMA_D[0], EMA_D[1], EMA_D[2],
187 			0x24 0x11111111  0xffffffff
189 			0x30 0x01100000  0x0ff00000
222 	pinctrl-0 = <&i2c0_pins>;
225 		reg = <0x48>;
228 		#sound-dai-cells = <0>;
230 		reg = <0x18>;
241 		reg = <0x20>;
247 		reg = <0x21>;
262 	pinctrl-0 = <&mmc0_pins>;
270 	pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
271 	flash: m25p80@0 {
277 		reg = <0>;
278 		partition@0 {
280 			reg = <0x00000000 0x00010000>;
285 			reg = <0x00010000 0x00080000>;
290 			reg = <0x00090000 0x00010000>;
295 			reg = <0x000a0000 0x00280000>;
299 			reg = <0x00320000 0x00400000>;
303 			reg = <0x007f0000 0x00010000>;
312 	pinctrl-0 = <&mdio_pins>;
319 	pinctrl-0 = <&mii_pins>;
334 		vdcdc1_reg: regulator@0 {
379 	#sound-dai-cells = <0>;
382 	pinctrl-0 = <&mcasp0_pins>;
384 	op-mode = <0>;          /* MCASP_IIS_MODE */
387 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
388 		0 0 0 0
389 		0 0 0 0
390 		0 0 0 1
391 		2 0 0 0
407 	pinctrl-0 = <&nand_pins>;
417 		nand@2000000,0 {
421 			reg = <0 0x02000000 0x02000000
422 			       1 0x00000000 0x00008000>;
425 			ti,davinci-mask-ale = <0>;
426 			ti,davinci-mask-cle = <0>;
427 			ti,davinci-mask-chipsel = <0>;
449 	pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;