27 #define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
30 #define IMX_OCOTP_OFFSET_PER_WORD	0x10  /* Offset between the start addr
34 #define IMX_OCOTP_ADDR_CTRL		0x0000
35 #define IMX_OCOTP_ADDR_CTRL_SET		0x0004
36 #define IMX_OCOTP_ADDR_CTRL_CLR		0x0008
37 #define IMX_OCOTP_ADDR_TIMING		0x0010
38 #define IMX_OCOTP_ADDR_DATA0		0x0020
39 #define IMX_OCOTP_ADDR_DATA1		0x0030
40 #define IMX_OCOTP_ADDR_DATA2		0x0040
41 #define IMX_OCOTP_ADDR_DATA3		0x0050
43 #define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
44 #define IMX_OCOTP_BM_CTRL_BUSY		0x00000100
45 #define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
46 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400
48 #define IMX_OCOTP_BM_CTRL_ADDR_8MP		0x000001FF
49 #define IMX_OCOTP_BM_CTRL_BUSY_8MP		0x00000200
50 #define IMX_OCOTP_BM_CTRL_ERROR_8MP		0x00000400
51 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP	0x00000800
74 #define IMX_OCOTP_WR_UNLOCK		0x3E770000
75 #define IMX_OCOTP_READ_LOCKED_VAL	0xBADABADA
113 	for (count = 10000; count >= 0; count--) {  in imx_ocotp_wait_for_busy()
120 	if (count < 0) {  in imx_ocotp_wait_for_busy()
140 	return 0;  in imx_ocotp_wait_for_busy()
182 	if (ret < 0) {  in imx_ocotp_read()
189 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_read()
190 	if (ret < 0) {  in imx_ocotp_read()
200 		 * For "read locked" registers 0xBADABADA will be returned and  in imx_ocotp_read()
231 		for (i = 0; i < bytes / 2; i++)  in imx_ocotp_cell_pp()
234 	return 0;  in imx_ocotp_cell_pp()
281 	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;  in imx_ocotp_set_imx6_timing()
282 	timing |= strobe_prog & 0x00000FFF;  in imx_ocotp_set_imx6_timing()
283 	timing |= (relax       << 12) & 0x0000F000;  in imx_ocotp_set_imx6_timing()
284 	timing |= (strobe_read << 16) & 0x003F0000;  in imx_ocotp_set_imx6_timing()
304 	timing = strobe_prog & 0x00000FFF;  in imx_ocotp_set_imx7_timing()
305 	timing |= (fsource << 12) & 0x000FF000;  in imx_ocotp_set_imx7_timing()
319 	u8 word = 0;  in imx_ocotp_write()
329 	if (ret < 0) {  in imx_ocotp_write()
344 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_write()
345 	if (ret < 0) {  in imx_ocotp_write()
357 	if (priv->params->bank_address_words != 0) {  in imx_ocotp_write()
390 	 * fields with 0's will be ignored. At the same time that the write is  in imx_ocotp_write()
404 	if (priv->params->bank_address_words != 0) {  in imx_ocotp_write()
407 		case 0:  in imx_ocotp_write()
408 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
409 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
410 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
415 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
416 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
417 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
420 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
422 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);  in imx_ocotp_write()
423 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
426 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);  in imx_ocotp_write()
427 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);  in imx_ocotp_write()
429 			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);  in imx_ocotp_write()
444 	ret = imx_ocotp_wait_for_busy(priv, 0);  in imx_ocotp_write()
445 	if (ret < 0) {  in imx_ocotp_write()
468 	if (ret < 0)  in imx_ocotp_write()
474 	return ret < 0 ? ret : bytes;  in imx_ocotp_write()
488 	.bank_address_words = 0,
495 	.bank_address_words = 0,
502 	.bank_address_words = 0,
509 	.bank_address_words = 0,
516 	.bank_address_words = 0,
523 	.bank_address_words = 0,
537 	.bank_address_words = 0,
543 	.bank_address_words = 0,
550 	.bank_address_words = 0,
557 	.bank_address_words = 0,
564 	.bank_address_words = 0,
604 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in imx_ocotp_probe()