Lines Matching +full:0 +full:x000ff000

29 		pinctrl-0 = <&ecap2_pins>;
37 		pwms = <&ecap2 0 50000 0>;
38 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 		pinctrl-0 = <&lcd_pins>;
56 			ac-bias-intrpt = <0>;
59 			fdd = <0x80>;
60 			sync-edge = <0>;
62 			raster-order = <0>;
63 			fifo-th = <0>;
78 				hsync-active = <0>;
79 				vsync-active = <0>;
170 			0x00 0x11111111 0xffffffff
172 			0x04 0x00011000 0x000ff000
177 			/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
178 			0x1c 0x10110110  0xf0ff0ff0
180 			 * EMA_D[0], EMA_D[1], EMA_D[2],
184 			0x24 0x11111111  0xffffffff
186 			0x30 0x01100000  0x0ff00000
232 	pinctrl-0 = <&i2c0_pins>;
235 		reg = <0x48>;
238 		#sound-dai-cells = <0>;
240 		reg = <0x18>;
251 		reg = <0x20>;
257 		reg = <0x21>;
272 	pinctrl-0 = <&mmc0_pins>;
280 	pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
281 	flash: flash@0 {
287 		reg = <0>;
288 		partition@0 {
290 			reg = <0x00000000 0x00010000>;
295 			reg = <0x00010000 0x00080000>;
300 			reg = <0x00090000 0x00010000>;
305 			reg = <0x000a0000 0x00280000>;
309 			reg = <0x00320000 0x00400000>;
313 			reg = <0x007f0000 0x00010000>;
322 	pinctrl-0 = <&mdio_pins>;
329 	pinctrl-0 = <&mii_pins>;
344 		vdcdc1_reg: regulator@0 {
389 	#sound-dai-cells = <0>;
392 	pinctrl-0 = <&mcasp0_pins>;
394 	op-mode = <0>;          /* MCASP_IIS_MODE */
397 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
398 		0 0 0 0
399 		0 0 0 0
400 		0 0 0 1
401 		2 0 0 0
417 	pinctrl-0 = <&nand_pins>;
427 		nand@2000000,0 {
431 			reg = <0 0x02000000 0x02000000
432 			       1 0x00000000 0x00008000>;
435 			ti,davinci-mask-ale = <0>;
436 			ti,davinci-mask-cle = <0>;
437 			ti,davinci-mask-chipsel = <0>;
459 	pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;