183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 20b66513bSYork Sun /* 30b66513bSYork Sun * Copyright 2010-2011 Freescale Semiconductor, Inc. 40b66513bSYork Sun * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 50b66513bSYork Sun */ 60b66513bSYork Sun 70b66513bSYork Sun #ifndef __FSL_IFC_H 80b66513bSYork Sun #define __FSL_IFC_H 90b66513bSYork Sun 100b66513bSYork Sun #ifdef CONFIG_FSL_IFC 110b66513bSYork Sun #include <config.h> 120b66513bSYork Sun #include <common.h> 13457e51cfSSimon Glass #ifdef CONFIG_ARM 14457e51cfSSimon Glass #include <asm/arch/soc.h> 15457e51cfSSimon Glass #endif 160b66513bSYork Sun 17591dd192SPrabhakar Kushwaha #define FSL_IFC_V1_1_0 0x01010000 18591dd192SPrabhakar Kushwaha #define FSL_IFC_V2_0_0 0x02000000 191b4175d6SPrabhakar Kushwaha 201b4175d6SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_IFC_LE 211b4175d6SPrabhakar Kushwaha #define ifc_in32(a) in_le32(a) 221b4175d6SPrabhakar Kushwaha #define ifc_out32(a, v) out_le32(a, v) 231b4175d6SPrabhakar Kushwaha #define ifc_in16(a) in_le16(a) 24d3963721SScott Wood #define ifc_out16(a, v) out_le16(a, v) 251b4175d6SPrabhakar Kushwaha #elif defined(CONFIG_SYS_FSL_IFC_BE) 261b4175d6SPrabhakar Kushwaha #define ifc_in32(a) in_be32(a) 271b4175d6SPrabhakar Kushwaha #define ifc_out32(a, v) out_be32(a, v) 281b4175d6SPrabhakar Kushwaha #define ifc_in16(a) in_be16(a) 29d3963721SScott Wood #define ifc_out16(a, v) out_be16(a, v) 301b4175d6SPrabhakar Kushwaha #else 311b4175d6SPrabhakar Kushwaha #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined 321b4175d6SPrabhakar Kushwaha #endif 331b4175d6SPrabhakar Kushwaha 341b4175d6SPrabhakar Kushwaha 350b66513bSYork Sun /* 360b66513bSYork Sun * CSPR - Chip Select Property Register 370b66513bSYork Sun */ 380b66513bSYork Sun #define CSPR_BA 0xFFFF0000 390b66513bSYork Sun #define CSPR_BA_SHIFT 16 400b66513bSYork Sun #define CSPR_PORT_SIZE 0x00000180 410b66513bSYork Sun #define CSPR_PORT_SIZE_SHIFT 7 420b66513bSYork Sun /* Port Size 8 bit */ 430b66513bSYork Sun #define CSPR_PORT_SIZE_8 0x00000080 440b66513bSYork Sun /* Port Size 16 bit */ 450b66513bSYork Sun #define CSPR_PORT_SIZE_16 0x00000100 460b66513bSYork Sun /* Port Size 32 bit */ 470b66513bSYork Sun #define CSPR_PORT_SIZE_32 0x00000180 480b66513bSYork Sun /* Write Protect */ 490b66513bSYork Sun #define CSPR_WP 0x00000040 500b66513bSYork Sun #define CSPR_WP_SHIFT 6 510b66513bSYork Sun /* Machine Select */ 520b66513bSYork Sun #define CSPR_MSEL 0x00000006 530b66513bSYork Sun #define CSPR_MSEL_SHIFT 1 540b66513bSYork Sun /* NOR */ 550b66513bSYork Sun #define CSPR_MSEL_NOR 0x00000000 560b66513bSYork Sun /* NAND */ 570b66513bSYork Sun #define CSPR_MSEL_NAND 0x00000002 580b66513bSYork Sun /* GPCM */ 590b66513bSYork Sun #define CSPR_MSEL_GPCM 0x00000004 600b66513bSYork Sun /* Bank Valid */ 610b66513bSYork Sun #define CSPR_V 0x00000001 620b66513bSYork Sun #define CSPR_V_SHIFT 0 630b66513bSYork Sun 640b66513bSYork Sun /* Convert an address into the right format for the CSPR Registers */ 650b66513bSYork Sun #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 660b66513bSYork Sun 670b66513bSYork Sun /* 680b66513bSYork Sun * Address Mask Register 690b66513bSYork Sun */ 700b66513bSYork Sun #define IFC_AMASK_MASK 0xFFFF0000 710b66513bSYork Sun #define IFC_AMASK_SHIFT 16 720b66513bSYork Sun #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 73088d52cfSRajesh Bhagat (LOG2(n) - IFC_AMASK_SHIFT)) 740b66513bSYork Sun 750b66513bSYork Sun /* 760b66513bSYork Sun * Chip Select Option Register IFC_NAND Machine 770b66513bSYork Sun */ 780b66513bSYork Sun /* Enable ECC Encoder */ 790b66513bSYork Sun #define CSOR_NAND_ECC_ENC_EN 0x80000000 800b66513bSYork Sun #define CSOR_NAND_ECC_MODE_MASK 0x30000000 810b66513bSYork Sun /* 4 bit correction per 520 Byte sector */ 820b66513bSYork Sun #define CSOR_NAND_ECC_MODE_4 0x00000000 830b66513bSYork Sun /* 8 bit correction per 528 Byte sector */ 840b66513bSYork Sun #define CSOR_NAND_ECC_MODE_8 0x10000000 850b66513bSYork Sun /* Enable ECC Decoder */ 860b66513bSYork Sun #define CSOR_NAND_ECC_DEC_EN 0x04000000 870b66513bSYork Sun /* Row Address Length */ 880b66513bSYork Sun #define CSOR_NAND_RAL_MASK 0x01800000 890b66513bSYork Sun #define CSOR_NAND_RAL_SHIFT 20 900b66513bSYork Sun #define CSOR_NAND_RAL_1 0x00000000 910b66513bSYork Sun #define CSOR_NAND_RAL_2 0x00800000 920b66513bSYork Sun #define CSOR_NAND_RAL_3 0x01000000 930b66513bSYork Sun #define CSOR_NAND_RAL_4 0x01800000 940b66513bSYork Sun /* Page Size 512b, 2k, 4k */ 950b66513bSYork Sun #define CSOR_NAND_PGS_MASK 0x00180000 960b66513bSYork Sun #define CSOR_NAND_PGS_SHIFT 16 970b66513bSYork Sun #define CSOR_NAND_PGS_512 0x00000000 980b66513bSYork Sun #define CSOR_NAND_PGS_2K 0x00080000 990b66513bSYork Sun #define CSOR_NAND_PGS_4K 0x00100000 10077fdd6d1STom Rini #define CSOR_NAND_PGS_8K 0x00180000 1010b66513bSYork Sun /* Spare region Size */ 1020b66513bSYork Sun #define CSOR_NAND_SPRZ_MASK 0x0000E000 1030b66513bSYork Sun #define CSOR_NAND_SPRZ_SHIFT 13 1040b66513bSYork Sun #define CSOR_NAND_SPRZ_16 0x00000000 1050b66513bSYork Sun #define CSOR_NAND_SPRZ_64 0x00002000 1060b66513bSYork Sun #define CSOR_NAND_SPRZ_128 0x00004000 1070b66513bSYork Sun #define CSOR_NAND_SPRZ_210 0x00006000 1080b66513bSYork Sun #define CSOR_NAND_SPRZ_218 0x00008000 1090b66513bSYork Sun #define CSOR_NAND_SPRZ_224 0x0000A000 11077fdd6d1STom Rini #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 1110b66513bSYork Sun /* Pages Per Block */ 1120b66513bSYork Sun #define CSOR_NAND_PB_MASK 0x00000700 1130b66513bSYork Sun #define CSOR_NAND_PB_SHIFT 8 114088d52cfSRajesh Bhagat #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) 1150b66513bSYork Sun /* Time for Read Enable High to Output High Impedance */ 1160b66513bSYork Sun #define CSOR_NAND_TRHZ_MASK 0x0000001C 1170b66513bSYork Sun #define CSOR_NAND_TRHZ_SHIFT 2 1180b66513bSYork Sun #define CSOR_NAND_TRHZ_20 0x00000000 1190b66513bSYork Sun #define CSOR_NAND_TRHZ_40 0x00000004 1200b66513bSYork Sun #define CSOR_NAND_TRHZ_60 0x00000008 1210b66513bSYork Sun #define CSOR_NAND_TRHZ_80 0x0000000C 1220b66513bSYork Sun #define CSOR_NAND_TRHZ_100 0x00000010 1230b66513bSYork Sun /* Buffer control disable */ 1240b66513bSYork Sun #define CSOR_NAND_BCTLD 0x00000001 1250b66513bSYork Sun 1260b66513bSYork Sun /* 1270b66513bSYork Sun * Chip Select Option Register - NOR Flash Mode 1280b66513bSYork Sun */ 1290b66513bSYork Sun /* Enable Address shift Mode */ 1300b66513bSYork Sun #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 1310b66513bSYork Sun /* Page Read Enable from NOR device */ 1320b66513bSYork Sun #define CSOR_NOR_PGRD_EN 0x10000000 1330b66513bSYork Sun /* AVD Toggle Enable during Burst Program */ 1340b66513bSYork Sun #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 1350b66513bSYork Sun /* Address Data Multiplexing Shift */ 1360b66513bSYork Sun #define CSOR_NOR_ADM_MASK 0x0003E000 1370b66513bSYork Sun #define CSOR_NOR_ADM_SHIFT_SHIFT 13 1380b66513bSYork Sun #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 1390b66513bSYork Sun /* Type of the NOR device hooked */ 1400b66513bSYork Sun #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 1410b66513bSYork Sun #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 1420b66513bSYork Sun /* Time for Read Enable High to Output High Impedance */ 1430b66513bSYork Sun #define CSOR_NOR_TRHZ_MASK 0x0000001C 1440b66513bSYork Sun #define CSOR_NOR_TRHZ_SHIFT 2 1450b66513bSYork Sun #define CSOR_NOR_TRHZ_20 0x00000000 1460b66513bSYork Sun #define CSOR_NOR_TRHZ_40 0x00000004 1470b66513bSYork Sun #define CSOR_NOR_TRHZ_60 0x00000008 1480b66513bSYork Sun #define CSOR_NOR_TRHZ_80 0x0000000C 1490b66513bSYork Sun #define CSOR_NOR_TRHZ_100 0x00000010 1500b66513bSYork Sun /* Buffer control disable */ 1510b66513bSYork Sun #define CSOR_NOR_BCTLD 0x00000001 1520b66513bSYork Sun 1530b66513bSYork Sun /* 1540b66513bSYork Sun * Chip Select Option Register - GPCM Mode 1550b66513bSYork Sun */ 1560b66513bSYork Sun /* GPCM Mode - Normal */ 1570b66513bSYork Sun #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 1580b66513bSYork Sun /* GPCM Mode - GenericASIC */ 1590b66513bSYork Sun #define CSOR_GPCM_GPMODE_ASIC 0x80000000 1600b66513bSYork Sun /* Parity Mode odd/even */ 1610b66513bSYork Sun #define CSOR_GPCM_PARITY_EVEN 0x40000000 1620b66513bSYork Sun /* Parity Checking enable/disable */ 1630b66513bSYork Sun #define CSOR_GPCM_PAR_EN 0x20000000 1640b66513bSYork Sun /* GPCM Timeout Count */ 1650b66513bSYork Sun #define CSOR_GPCM_GPTO_MASK 0x0F000000 1660b66513bSYork Sun #define CSOR_GPCM_GPTO_SHIFT 24 167088d52cfSRajesh Bhagat #define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 1680b66513bSYork Sun /* GPCM External Access Termination mode for read access */ 1690b66513bSYork Sun #define CSOR_GPCM_RGETA_EXT 0x00080000 1700b66513bSYork Sun /* GPCM External Access Termination mode for write access */ 1710b66513bSYork Sun #define CSOR_GPCM_WGETA_EXT 0x00040000 1720b66513bSYork Sun /* Address Data Multiplexing Shift */ 1730b66513bSYork Sun #define CSOR_GPCM_ADM_MASK 0x0003E000 1740b66513bSYork Sun #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 1750b66513bSYork Sun #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 1760b66513bSYork Sun /* Generic ASIC Parity error indication delay */ 1770b66513bSYork Sun #define CSOR_GPCM_GAPERRD_MASK 0x00000180 1780b66513bSYork Sun #define CSOR_GPCM_GAPERRD_SHIFT 7 1790b66513bSYork Sun #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 1800b66513bSYork Sun /* Time for Read Enable High to Output High Impedance */ 1810b66513bSYork Sun #define CSOR_GPCM_TRHZ_MASK 0x0000001C 1820b66513bSYork Sun #define CSOR_GPCM_TRHZ_20 0x00000000 1830b66513bSYork Sun #define CSOR_GPCM_TRHZ_40 0x00000004 1840b66513bSYork Sun #define CSOR_GPCM_TRHZ_60 0x00000008 1850b66513bSYork Sun #define CSOR_GPCM_TRHZ_80 0x0000000C 1860b66513bSYork Sun #define CSOR_GPCM_TRHZ_100 0x00000010 1870b66513bSYork Sun /* Buffer control disable */ 1880b66513bSYork Sun #define CSOR_GPCM_BCTLD 0x00000001 1890b66513bSYork Sun 1900b66513bSYork Sun /* 1910b66513bSYork Sun * Flash Timing Registers (FTIM0 - FTIM2_CSn) 1920b66513bSYork Sun */ 1930b66513bSYork Sun /* 1940b66513bSYork Sun * FTIM0 - NAND Flash Mode 1950b66513bSYork Sun */ 1960b66513bSYork Sun #define FTIM0_NAND 0x7EFF3F3F 1970b66513bSYork Sun #define FTIM0_NAND_TCCST_SHIFT 25 1980b66513bSYork Sun #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 1990b66513bSYork Sun #define FTIM0_NAND_TWP_SHIFT 16 2000b66513bSYork Sun #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 2010b66513bSYork Sun #define FTIM0_NAND_TWCHT_SHIFT 8 2020b66513bSYork Sun #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 2030b66513bSYork Sun #define FTIM0_NAND_TWH_SHIFT 0 2040b66513bSYork Sun #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 2050b66513bSYork Sun /* 2060b66513bSYork Sun * FTIM1 - NAND Flash Mode 2070b66513bSYork Sun */ 2080b66513bSYork Sun #define FTIM1_NAND 0xFFFF3FFF 2090b66513bSYork Sun #define FTIM1_NAND_TADLE_SHIFT 24 2100b66513bSYork Sun #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 2110b66513bSYork Sun #define FTIM1_NAND_TWBE_SHIFT 16 2120b66513bSYork Sun #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 2130b66513bSYork Sun #define FTIM1_NAND_TRR_SHIFT 8 2140b66513bSYork Sun #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 2150b66513bSYork Sun #define FTIM1_NAND_TRP_SHIFT 0 2160b66513bSYork Sun #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 2170b66513bSYork Sun /* 2180b66513bSYork Sun * FTIM2 - NAND Flash Mode 2190b66513bSYork Sun */ 2200b66513bSYork Sun #define FTIM2_NAND 0x1FE1F8FF 2210b66513bSYork Sun #define FTIM2_NAND_TRAD_SHIFT 21 2220b66513bSYork Sun #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 2230b66513bSYork Sun #define FTIM2_NAND_TREH_SHIFT 11 2240b66513bSYork Sun #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 2250b66513bSYork Sun #define FTIM2_NAND_TWHRE_SHIFT 0 2260b66513bSYork Sun #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 2270b66513bSYork Sun /* 2280b66513bSYork Sun * FTIM3 - NAND Flash Mode 2290b66513bSYork Sun */ 2300b66513bSYork Sun #define FTIM3_NAND 0xFF000000 2310b66513bSYork Sun #define FTIM3_NAND_TWW_SHIFT 24 2320b66513bSYork Sun #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 2330b66513bSYork Sun 2340b66513bSYork Sun /* 2350b66513bSYork Sun * FTIM0 - NOR Flash Mode 2360b66513bSYork Sun */ 2370b66513bSYork Sun #define FTIM0_NOR 0xF03F3F3F 2380b66513bSYork Sun #define FTIM0_NOR_TACSE_SHIFT 28 2390b66513bSYork Sun #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 2400b66513bSYork Sun #define FTIM0_NOR_TEADC_SHIFT 16 2410b66513bSYork Sun #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 2420b66513bSYork Sun #define FTIM0_NOR_TAVDS_SHIFT 8 2430b66513bSYork Sun #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 2440b66513bSYork Sun #define FTIM0_NOR_TEAHC_SHIFT 0 2450b66513bSYork Sun #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 2460b66513bSYork Sun /* 2470b66513bSYork Sun * FTIM1 - NOR Flash Mode 2480b66513bSYork Sun */ 2490b66513bSYork Sun #define FTIM1_NOR 0xFF003F3F 2500b66513bSYork Sun #define FTIM1_NOR_TACO_SHIFT 24 2510b66513bSYork Sun #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 2520b66513bSYork Sun #define FTIM1_NOR_TRAD_NOR_SHIFT 8 2530b66513bSYork Sun #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 2540b66513bSYork Sun #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 2550b66513bSYork Sun #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 2560b66513bSYork Sun /* 2570b66513bSYork Sun * FTIM2 - NOR Flash Mode 2580b66513bSYork Sun */ 2590b66513bSYork Sun #define FTIM2_NOR 0x0F3CFCFF 2600b66513bSYork Sun #define FTIM2_NOR_TCS_SHIFT 24 2610b66513bSYork Sun #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 2620b66513bSYork Sun #define FTIM2_NOR_TCH_SHIFT 18 2630b66513bSYork Sun #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 2640b66513bSYork Sun #define FTIM2_NOR_TWPH_SHIFT 10 2650b66513bSYork Sun #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 2660b66513bSYork Sun #define FTIM2_NOR_TWP_SHIFT 0 2670b66513bSYork Sun #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 2680b66513bSYork Sun 2690b66513bSYork Sun /* 2700b66513bSYork Sun * FTIM0 - Normal GPCM Mode 2710b66513bSYork Sun */ 2720b66513bSYork Sun #define FTIM0_GPCM 0xF03F3F3F 2730b66513bSYork Sun #define FTIM0_GPCM_TACSE_SHIFT 28 2740b66513bSYork Sun #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 2750b66513bSYork Sun #define FTIM0_GPCM_TEADC_SHIFT 16 2760b66513bSYork Sun #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 2770b66513bSYork Sun #define FTIM0_GPCM_TAVDS_SHIFT 8 2780b66513bSYork Sun #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 2790b66513bSYork Sun #define FTIM0_GPCM_TEAHC_SHIFT 0 2800b66513bSYork Sun #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 2810b66513bSYork Sun /* 2820b66513bSYork Sun * FTIM1 - Normal GPCM Mode 2830b66513bSYork Sun */ 2840b66513bSYork Sun #define FTIM1_GPCM 0xFF003F00 2850b66513bSYork Sun #define FTIM1_GPCM_TACO_SHIFT 24 2860b66513bSYork Sun #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 2870b66513bSYork Sun #define FTIM1_GPCM_TRAD_SHIFT 8 2880b66513bSYork Sun #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 2890b66513bSYork Sun /* 2900b66513bSYork Sun * FTIM2 - Normal GPCM Mode 2910b66513bSYork Sun */ 2920b66513bSYork Sun #define FTIM2_GPCM 0x0F3C00FF 2930b66513bSYork Sun #define FTIM2_GPCM_TCS_SHIFT 24 2940b66513bSYork Sun #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 2950b66513bSYork Sun #define FTIM2_GPCM_TCH_SHIFT 18 2960b66513bSYork Sun #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 2970b66513bSYork Sun #define FTIM2_GPCM_TWP_SHIFT 0 2980b66513bSYork Sun #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 2990b66513bSYork Sun 3000b66513bSYork Sun /* 3010b66513bSYork Sun * Ready Busy Status Register (RB_STAT) 3020b66513bSYork Sun */ 3030b66513bSYork Sun /* CSn is READY */ 3040b66513bSYork Sun #define IFC_RB_STAT_READY_CS0 0x80000000 3050b66513bSYork Sun #define IFC_RB_STAT_READY_CS1 0x40000000 3060b66513bSYork Sun #define IFC_RB_STAT_READY_CS2 0x20000000 3070b66513bSYork Sun #define IFC_RB_STAT_READY_CS3 0x10000000 3080b66513bSYork Sun 3090b66513bSYork Sun /* 3100b66513bSYork Sun * General Control Register (GCR) 3110b66513bSYork Sun */ 3120b66513bSYork Sun #define IFC_GCR_MASK 0x8000F800 3130b66513bSYork Sun /* reset all IFC hardware */ 3140b66513bSYork Sun #define IFC_GCR_SOFT_RST_ALL 0x80000000 3150b66513bSYork Sun /* Turnaroud Time of external buffer */ 3160b66513bSYork Sun #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 3170b66513bSYork Sun #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 3180b66513bSYork Sun 3190b66513bSYork Sun /* 3200b66513bSYork Sun * Common Event and Error Status Register (CM_EVTER_STAT) 3210b66513bSYork Sun */ 3220b66513bSYork Sun /* Chip select error */ 3230b66513bSYork Sun #define IFC_CM_EVTER_STAT_CSER 0x80000000 3240b66513bSYork Sun 3250b66513bSYork Sun /* 3260b66513bSYork Sun * Common Event and Error Enable Register (CM_EVTER_EN) 3270b66513bSYork Sun */ 3280b66513bSYork Sun /* Chip select error checking enable */ 3290b66513bSYork Sun #define IFC_CM_EVTER_EN_CSEREN 0x80000000 3300b66513bSYork Sun 3310b66513bSYork Sun /* 3320b66513bSYork Sun * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 3330b66513bSYork Sun */ 3340b66513bSYork Sun /* Chip select error interrupt enable */ 3350b66513bSYork Sun #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 3360b66513bSYork Sun 3370b66513bSYork Sun /* 3380b66513bSYork Sun * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 3390b66513bSYork Sun */ 3400b66513bSYork Sun /* transaction type of error Read/Write */ 3410b66513bSYork Sun #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 3420b66513bSYork Sun #define IFC_CM_ERATTR0_ERAID 0x0FF00000 3430b66513bSYork Sun #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 3440b66513bSYork Sun 3450b66513bSYork Sun /* 3460b66513bSYork Sun * Clock Control Register (CCR) 3470b66513bSYork Sun */ 3480b66513bSYork Sun #define IFC_CCR_MASK 0x0F0F8800 3490b66513bSYork Sun /* Clock division ratio */ 3500b66513bSYork Sun #define IFC_CCR_CLK_DIV_MASK 0x0F000000 3510b66513bSYork Sun #define IFC_CCR_CLK_DIV_SHIFT 24 3520b66513bSYork Sun #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 3530b66513bSYork Sun /* IFC Clock Delay */ 3540b66513bSYork Sun #define IFC_CCR_CLK_DLY_MASK 0x000F0000 3550b66513bSYork Sun #define IFC_CCR_CLK_DLY_SHIFT 16 3560b66513bSYork Sun #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 3570b66513bSYork Sun /* Invert IFC clock before sending out */ 3580b66513bSYork Sun #define IFC_CCR_INV_CLK_EN 0x00008000 3590b66513bSYork Sun /* Fedback IFC Clock */ 3600b66513bSYork Sun #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 3610b66513bSYork Sun 3620b66513bSYork Sun /* 3630b66513bSYork Sun * Clock Status Register (CSR) 3640b66513bSYork Sun */ 3650b66513bSYork Sun /* Clk is stable */ 3660b66513bSYork Sun #define IFC_CSR_CLK_STAT_STABLE 0x80000000 3670b66513bSYork Sun 3680b66513bSYork Sun /* 3690b66513bSYork Sun * IFC_NAND Machine Specific Registers 3700b66513bSYork Sun */ 3710b66513bSYork Sun /* 3720b66513bSYork Sun * NAND Configuration Register (NCFGR) 3730b66513bSYork Sun */ 3740b66513bSYork Sun /* Auto Boot Mode */ 3750b66513bSYork Sun #define IFC_NAND_NCFGR_BOOT 0x80000000 37604818bbdSPrabhakar Kushwaha /* SRAM INIT EN */ 37704818bbdSPrabhakar Kushwaha #define IFC_NAND_SRAM_INIT_EN 0x20000000 3780b66513bSYork Sun /* Addressing Mode-ROW0+n/COL0 */ 3790b66513bSYork Sun #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 3800b66513bSYork Sun /* Addressing Mode-ROW0+n/COL0+n */ 3810b66513bSYork Sun #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 3820b66513bSYork Sun /* Number of loop iterations of FIR sequences for multi page operations */ 3830b66513bSYork Sun #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 3840b66513bSYork Sun #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 3850b66513bSYork Sun #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 3860b66513bSYork Sun /* Number of wait cycles */ 3870b66513bSYork Sun #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 3880b66513bSYork Sun #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 3890b66513bSYork Sun 3900b66513bSYork Sun /* 3910b66513bSYork Sun * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 3920b66513bSYork Sun */ 3930b66513bSYork Sun /* General purpose FCM flash command bytes CMD0-CMD7 */ 3940b66513bSYork Sun #define IFC_NAND_FCR0_CMD0 0xFF000000 3950b66513bSYork Sun #define IFC_NAND_FCR0_CMD0_SHIFT 24 3960b66513bSYork Sun #define IFC_NAND_FCR0_CMD1 0x00FF0000 3970b66513bSYork Sun #define IFC_NAND_FCR0_CMD1_SHIFT 16 3980b66513bSYork Sun #define IFC_NAND_FCR0_CMD2 0x0000FF00 3990b66513bSYork Sun #define IFC_NAND_FCR0_CMD2_SHIFT 8 4000b66513bSYork Sun #define IFC_NAND_FCR0_CMD3 0x000000FF 4010b66513bSYork Sun #define IFC_NAND_FCR0_CMD3_SHIFT 0 4020b66513bSYork Sun #define IFC_NAND_FCR1_CMD4 0xFF000000 4030b66513bSYork Sun #define IFC_NAND_FCR1_CMD4_SHIFT 24 4040b66513bSYork Sun #define IFC_NAND_FCR1_CMD5 0x00FF0000 4050b66513bSYork Sun #define IFC_NAND_FCR1_CMD5_SHIFT 16 4060b66513bSYork Sun #define IFC_NAND_FCR1_CMD6 0x0000FF00 4070b66513bSYork Sun #define IFC_NAND_FCR1_CMD6_SHIFT 8 4080b66513bSYork Sun #define IFC_NAND_FCR1_CMD7 0x000000FF 4090b66513bSYork Sun #define IFC_NAND_FCR1_CMD7_SHIFT 0 4100b66513bSYork Sun 4110b66513bSYork Sun /* 4120b66513bSYork Sun * Flash ROW and COL Address Register (ROWn, COLn) 4130b66513bSYork Sun */ 4140b66513bSYork Sun /* Main/spare region locator */ 4150b66513bSYork Sun #define IFC_NAND_COL_MS 0x80000000 4160b66513bSYork Sun /* Column Address */ 4170b66513bSYork Sun #define IFC_NAND_COL_CA_MASK 0x00000FFF 4180b66513bSYork Sun 4190b66513bSYork Sun /* 4200b66513bSYork Sun * NAND Flash Byte Count Register (NAND_BC) 4210b66513bSYork Sun */ 4220b66513bSYork Sun /* Byte Count for read/Write */ 4230b66513bSYork Sun #define IFC_NAND_BC 0x000001FF 4240b66513bSYork Sun 4250b66513bSYork Sun /* 4260b66513bSYork Sun * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 4270b66513bSYork Sun */ 4280b66513bSYork Sun /* NAND Machine specific opcodes OP0-OP14*/ 4290b66513bSYork Sun #define IFC_NAND_FIR0_OP0 0xFC000000 4300b66513bSYork Sun #define IFC_NAND_FIR0_OP0_SHIFT 26 4310b66513bSYork Sun #define IFC_NAND_FIR0_OP1 0x03F00000 4320b66513bSYork Sun #define IFC_NAND_FIR0_OP1_SHIFT 20 4330b66513bSYork Sun #define IFC_NAND_FIR0_OP2 0x000FC000 4340b66513bSYork Sun #define IFC_NAND_FIR0_OP2_SHIFT 14 4350b66513bSYork Sun #define IFC_NAND_FIR0_OP3 0x00003F00 4360b66513bSYork Sun #define IFC_NAND_FIR0_OP3_SHIFT 8 4370b66513bSYork Sun #define IFC_NAND_FIR0_OP4 0x000000FC 4380b66513bSYork Sun #define IFC_NAND_FIR0_OP4_SHIFT 2 4390b66513bSYork Sun #define IFC_NAND_FIR1_OP5 0xFC000000 4400b66513bSYork Sun #define IFC_NAND_FIR1_OP5_SHIFT 26 4410b66513bSYork Sun #define IFC_NAND_FIR1_OP6 0x03F00000 4420b66513bSYork Sun #define IFC_NAND_FIR1_OP6_SHIFT 20 4430b66513bSYork Sun #define IFC_NAND_FIR1_OP7 0x000FC000 4440b66513bSYork Sun #define IFC_NAND_FIR1_OP7_SHIFT 14 4450b66513bSYork Sun #define IFC_NAND_FIR1_OP8 0x00003F00 4460b66513bSYork Sun #define IFC_NAND_FIR1_OP8_SHIFT 8 4470b66513bSYork Sun #define IFC_NAND_FIR1_OP9 0x000000FC 4480b66513bSYork Sun #define IFC_NAND_FIR1_OP9_SHIFT 2 4490b66513bSYork Sun #define IFC_NAND_FIR2_OP10 0xFC000000 4500b66513bSYork Sun #define IFC_NAND_FIR2_OP10_SHIFT 26 4510b66513bSYork Sun #define IFC_NAND_FIR2_OP11 0x03F00000 4520b66513bSYork Sun #define IFC_NAND_FIR2_OP11_SHIFT 20 4530b66513bSYork Sun #define IFC_NAND_FIR2_OP12 0x000FC000 4540b66513bSYork Sun #define IFC_NAND_FIR2_OP12_SHIFT 14 4550b66513bSYork Sun #define IFC_NAND_FIR2_OP13 0x00003F00 4560b66513bSYork Sun #define IFC_NAND_FIR2_OP13_SHIFT 8 4570b66513bSYork Sun #define IFC_NAND_FIR2_OP14 0x000000FC 4580b66513bSYork Sun #define IFC_NAND_FIR2_OP14_SHIFT 2 4590b66513bSYork Sun 4600b66513bSYork Sun /* 4610b66513bSYork Sun * Instruction opcodes to be programmed 4620b66513bSYork Sun * in FIR registers- 6bits 4630b66513bSYork Sun */ 4640b66513bSYork Sun enum ifc_nand_fir_opcodes { 4650b66513bSYork Sun IFC_FIR_OP_NOP, 4660b66513bSYork Sun IFC_FIR_OP_CA0, 4670b66513bSYork Sun IFC_FIR_OP_CA1, 4680b66513bSYork Sun IFC_FIR_OP_CA2, 4690b66513bSYork Sun IFC_FIR_OP_CA3, 4700b66513bSYork Sun IFC_FIR_OP_RA0, 4710b66513bSYork Sun IFC_FIR_OP_RA1, 4720b66513bSYork Sun IFC_FIR_OP_RA2, 4730b66513bSYork Sun IFC_FIR_OP_RA3, 4740b66513bSYork Sun IFC_FIR_OP_CMD0, 4750b66513bSYork Sun IFC_FIR_OP_CMD1, 4760b66513bSYork Sun IFC_FIR_OP_CMD2, 4770b66513bSYork Sun IFC_FIR_OP_CMD3, 4780b66513bSYork Sun IFC_FIR_OP_CMD4, 4790b66513bSYork Sun IFC_FIR_OP_CMD5, 4800b66513bSYork Sun IFC_FIR_OP_CMD6, 4810b66513bSYork Sun IFC_FIR_OP_CMD7, 4820b66513bSYork Sun IFC_FIR_OP_CW0, 4830b66513bSYork Sun IFC_FIR_OP_CW1, 4840b66513bSYork Sun IFC_FIR_OP_CW2, 4850b66513bSYork Sun IFC_FIR_OP_CW3, 4860b66513bSYork Sun IFC_FIR_OP_CW4, 4870b66513bSYork Sun IFC_FIR_OP_CW5, 4880b66513bSYork Sun IFC_FIR_OP_CW6, 4890b66513bSYork Sun IFC_FIR_OP_CW7, 4900b66513bSYork Sun IFC_FIR_OP_WBCD, 4910b66513bSYork Sun IFC_FIR_OP_RBCD, 4920b66513bSYork Sun IFC_FIR_OP_BTRD, 4930b66513bSYork Sun IFC_FIR_OP_RDSTAT, 4940b66513bSYork Sun IFC_FIR_OP_NWAIT, 4950b66513bSYork Sun IFC_FIR_OP_WFR, 4960b66513bSYork Sun IFC_FIR_OP_SBRD, 4970b66513bSYork Sun IFC_FIR_OP_UA, 4980b66513bSYork Sun IFC_FIR_OP_RB, 4990b66513bSYork Sun }; 5000b66513bSYork Sun 5010b66513bSYork Sun /* 5020b66513bSYork Sun * NAND Chip Select Register (NAND_CSEL) 5030b66513bSYork Sun */ 5040b66513bSYork Sun #define IFC_NAND_CSEL 0x0C000000 5050b66513bSYork Sun #define IFC_NAND_CSEL_SHIFT 26 5060b66513bSYork Sun #define IFC_NAND_CSEL_CS0 0x00000000 5070b66513bSYork Sun #define IFC_NAND_CSEL_CS1 0x04000000 5080b66513bSYork Sun #define IFC_NAND_CSEL_CS2 0x08000000 5090b66513bSYork Sun #define IFC_NAND_CSEL_CS3 0x0C000000 5100b66513bSYork Sun 5110b66513bSYork Sun /* 5120b66513bSYork Sun * NAND Operation Sequence Start (NANDSEQ_STRT) 5130b66513bSYork Sun */ 5140b66513bSYork Sun /* NAND Flash Operation Start */ 5150b66513bSYork Sun #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 5160b66513bSYork Sun /* Automatic Erase */ 5170b66513bSYork Sun #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 5180b66513bSYork Sun /* Automatic Program */ 5190b66513bSYork Sun #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 5200b66513bSYork Sun /* Automatic Copyback */ 5210b66513bSYork Sun #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 5220b66513bSYork Sun /* Automatic Read Operation */ 5230b66513bSYork Sun #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 5240b66513bSYork Sun /* Automatic Status Read */ 5250b66513bSYork Sun #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 5260b66513bSYork Sun 5270b66513bSYork Sun /* 5280b66513bSYork Sun * NAND Event and Error Status Register (NAND_EVTER_STAT) 5290b66513bSYork Sun */ 5300b66513bSYork Sun /* Operation Complete */ 5310b66513bSYork Sun #define IFC_NAND_EVTER_STAT_OPC 0x80000000 5320b66513bSYork Sun /* Flash Timeout Error */ 5330b66513bSYork Sun #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 5340b66513bSYork Sun /* Write Protect Error */ 5350b66513bSYork Sun #define IFC_NAND_EVTER_STAT_WPER 0x04000000 5360b66513bSYork Sun /* ECC Error */ 5370b66513bSYork Sun #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 5380b66513bSYork Sun /* RCW Load Done */ 5390b66513bSYork Sun #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 5400b66513bSYork Sun /* Boot Loadr Done */ 5410b66513bSYork Sun #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 5420b66513bSYork Sun /* Bad Block Indicator search select */ 5430b66513bSYork Sun #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 5440b66513bSYork Sun 5450b66513bSYork Sun /* 5460b66513bSYork Sun * NAND Flash Page Read Completion Event Status Register 5470b66513bSYork Sun * (PGRDCMPL_EVT_STAT) 5480b66513bSYork Sun */ 5490b66513bSYork Sun #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 5500b66513bSYork Sun /* Small Page 0-15 Done */ 5510b66513bSYork Sun #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 5520b66513bSYork Sun /* Large Page(2K) 0-3 Done */ 5530b66513bSYork Sun #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 5540b66513bSYork Sun /* Large Page(4K) 0-1 Done */ 5550b66513bSYork Sun #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 5560b66513bSYork Sun 5570b66513bSYork Sun /* 5580b66513bSYork Sun * NAND Event and Error Enable Register (NAND_EVTER_EN) 5590b66513bSYork Sun */ 5600b66513bSYork Sun /* Operation complete event enable */ 5610b66513bSYork Sun #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 5620b66513bSYork Sun /* Page read complete event enable */ 5630b66513bSYork Sun #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 5640b66513bSYork Sun /* Flash Timeout error enable */ 5650b66513bSYork Sun #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 5660b66513bSYork Sun /* Write Protect error enable */ 5670b66513bSYork Sun #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 5680b66513bSYork Sun /* ECC error logging enable */ 5690b66513bSYork Sun #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 5700b66513bSYork Sun 5710b66513bSYork Sun /* 5720b66513bSYork Sun * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 5730b66513bSYork Sun */ 5740b66513bSYork Sun /* Enable interrupt for operation complete */ 5750b66513bSYork Sun #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 5760b66513bSYork Sun /* Enable interrupt for Page read complete */ 5770b66513bSYork Sun #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 5780b66513bSYork Sun /* Enable interrupt for Flash timeout error */ 5790b66513bSYork Sun #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 5800b66513bSYork Sun /* Enable interrupt for Write protect error */ 5810b66513bSYork Sun #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 5820b66513bSYork Sun /* Enable interrupt for ECC error*/ 5830b66513bSYork Sun #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 5840b66513bSYork Sun 5850b66513bSYork Sun /* 5860b66513bSYork Sun * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 5870b66513bSYork Sun */ 5880b66513bSYork Sun #define IFC_NAND_ERATTR0_MASK 0x0C080000 5890b66513bSYork Sun /* Error on CS0-3 for NAND */ 5900b66513bSYork Sun #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 5910b66513bSYork Sun #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 5920b66513bSYork Sun #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 5930b66513bSYork Sun #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 5940b66513bSYork Sun /* Transaction type of error Read/Write */ 5950b66513bSYork Sun #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 5960b66513bSYork Sun 5970b66513bSYork Sun /* 5980b66513bSYork Sun * NAND Flash Status Register (NAND_FSR) 5990b66513bSYork Sun */ 6000b66513bSYork Sun /* First byte of data read from read status op */ 6010b66513bSYork Sun #define IFC_NAND_NFSR_RS0 0xFF000000 6020b66513bSYork Sun /* Second byte of data read from read status op */ 6030b66513bSYork Sun #define IFC_NAND_NFSR_RS1 0x00FF0000 6040b66513bSYork Sun 6050b66513bSYork Sun /* 6060b66513bSYork Sun * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 6070b66513bSYork Sun */ 6080b66513bSYork Sun /* Number of ECC errors on sector n (n = 0-15) */ 6090b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 6100b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 6110b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 6120b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 6130b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 6140b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 6150b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 6160b66513bSYork Sun #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 6170b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 6180b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 6190b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 6200b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 6210b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 6220b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 6230b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 6240b66513bSYork Sun #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 6250b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 6260b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 6270b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 6280b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 6290b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 6300b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 6310b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 6320b66513bSYork Sun #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 6330b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 6340b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 6350b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 6360b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 6370b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 6380b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 6390b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 6400b66513bSYork Sun #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 6410b66513bSYork Sun 6420b66513bSYork Sun /* 6430b66513bSYork Sun * NAND Control Register (NANDCR) 6440b66513bSYork Sun */ 6450b66513bSYork Sun #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 6460b66513bSYork Sun #define IFC_NAND_NCR_FTOCNT_SHIFT 25 647088d52cfSRajesh Bhagat #define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 6480b66513bSYork Sun 6490b66513bSYork Sun /* 6500b66513bSYork Sun * NAND_AUTOBOOT_TRGR 6510b66513bSYork Sun */ 6520b66513bSYork Sun /* Trigger RCW load */ 6530b66513bSYork Sun #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 6540b66513bSYork Sun /* Trigget Auto Boot */ 6550b66513bSYork Sun #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 6560b66513bSYork Sun 6570b66513bSYork Sun /* 6580b66513bSYork Sun * NAND_MDR 6590b66513bSYork Sun */ 6600b66513bSYork Sun /* 1st read data byte when opcode SBRD */ 6610b66513bSYork Sun #define IFC_NAND_MDR_RDATA0 0xFF000000 6620b66513bSYork Sun /* 2nd read data byte when opcode SBRD */ 6630b66513bSYork Sun #define IFC_NAND_MDR_RDATA1 0x00FF0000 6640b66513bSYork Sun 6650b66513bSYork Sun /* 6660b66513bSYork Sun * NOR Machine Specific Registers 6670b66513bSYork Sun */ 6680b66513bSYork Sun /* 6690b66513bSYork Sun * NOR Event and Error Status Register (NOR_EVTER_STAT) 6700b66513bSYork Sun */ 6710b66513bSYork Sun /* NOR Command Sequence Operation Complete */ 6720b66513bSYork Sun #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 6730b66513bSYork Sun /* Write Protect Error */ 6740b66513bSYork Sun #define IFC_NOR_EVTER_STAT_WPER 0x04000000 6750b66513bSYork Sun /* Command Sequence Timeout Error */ 6760b66513bSYork Sun #define IFC_NOR_EVTER_STAT_STOER 0x01000000 6770b66513bSYork Sun 6780b66513bSYork Sun /* 6790b66513bSYork Sun * NOR Event and Error Enable Register (NOR_EVTER_EN) 6800b66513bSYork Sun */ 6810b66513bSYork Sun /* NOR Command Seq complete event enable */ 6820b66513bSYork Sun #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 6830b66513bSYork Sun /* Write Protect Error Checking Enable */ 6840b66513bSYork Sun #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 6850b66513bSYork Sun /* Timeout Error Enable */ 6860b66513bSYork Sun #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 6870b66513bSYork Sun 6880b66513bSYork Sun /* 6890b66513bSYork Sun * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 6900b66513bSYork Sun */ 6910b66513bSYork Sun /* Enable interrupt for OPC complete */ 6920b66513bSYork Sun #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 6930b66513bSYork Sun /* Enable interrupt for write protect error */ 6940b66513bSYork Sun #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 6950b66513bSYork Sun /* Enable interrupt for timeout error */ 6960b66513bSYork Sun #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 6970b66513bSYork Sun 6980b66513bSYork Sun /* 6990b66513bSYork Sun * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 7000b66513bSYork Sun */ 7010b66513bSYork Sun /* Source ID for error transaction */ 7020b66513bSYork Sun #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 7030b66513bSYork Sun /* AXI ID for error transation */ 7040b66513bSYork Sun #define IFC_NOR_ERATTR0_ERAID 0x000FF000 7050b66513bSYork Sun /* Chip select corresponds to NOR error */ 7060b66513bSYork Sun #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 7070b66513bSYork Sun #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 7080b66513bSYork Sun #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 7090b66513bSYork Sun #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 7100b66513bSYork Sun /* Type of transaction read/write */ 7110b66513bSYork Sun #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 7120b66513bSYork Sun 7130b66513bSYork Sun /* 7140b66513bSYork Sun * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 7150b66513bSYork Sun */ 7160b66513bSYork Sun #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 7170b66513bSYork Sun #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 7180b66513bSYork Sun 7190b66513bSYork Sun /* 7200b66513bSYork Sun * NOR Control Register (NORCR) 7210b66513bSYork Sun */ 7220b66513bSYork Sun #define IFC_NORCR_MASK 0x0F0F0000 7230b66513bSYork Sun /* No. of Address/Data Phase */ 7240b66513bSYork Sun #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 7250b66513bSYork Sun #define IFC_NORCR_NUM_PHASE_SHIFT 24 7260b66513bSYork Sun #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 7270b66513bSYork Sun /* Sequence Timeout Count */ 7280b66513bSYork Sun #define IFC_NORCR_STOCNT_MASK 0x000F0000 7290b66513bSYork Sun #define IFC_NORCR_STOCNT_SHIFT 16 730088d52cfSRajesh Bhagat #define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 7310b66513bSYork Sun 7320b66513bSYork Sun /* 7330b66513bSYork Sun * GPCM Machine specific registers 7340b66513bSYork Sun */ 7350b66513bSYork Sun /* 7360b66513bSYork Sun * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 7370b66513bSYork Sun */ 7380b66513bSYork Sun /* Timeout error */ 7390b66513bSYork Sun #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 7400b66513bSYork Sun /* Parity error */ 7410b66513bSYork Sun #define IFC_GPCM_EVTER_STAT_PER 0x01000000 7420b66513bSYork Sun 7430b66513bSYork Sun /* 7440b66513bSYork Sun * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 7450b66513bSYork Sun */ 7460b66513bSYork Sun /* Timeout error enable */ 7470b66513bSYork Sun #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 7480b66513bSYork Sun /* Parity error enable */ 7490b66513bSYork Sun #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 7500b66513bSYork Sun 7510b66513bSYork Sun /* 7520b66513bSYork Sun * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 7530b66513bSYork Sun */ 7540b66513bSYork Sun /* Enable Interrupt for timeout error */ 7550b66513bSYork Sun #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 7560b66513bSYork Sun /* Enable Interrupt for Parity error */ 7570b66513bSYork Sun #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 7580b66513bSYork Sun 7590b66513bSYork Sun /* 7600b66513bSYork Sun * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 7610b66513bSYork Sun */ 7620b66513bSYork Sun /* Source ID for error transaction */ 7630b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 7640b66513bSYork Sun /* AXI ID for error transaction */ 7650b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 7660b66513bSYork Sun /* Chip select corresponds to GPCM error */ 7670b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 7680b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 7690b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 7700b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 7710b66513bSYork Sun /* Type of transaction read/Write */ 7720b66513bSYork Sun #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 7730b66513bSYork Sun 7740b66513bSYork Sun /* 7750b66513bSYork Sun * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 7760b66513bSYork Sun */ 7770b66513bSYork Sun /* On which beat of address/data parity error is observed */ 7780b66513bSYork Sun #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 7790b66513bSYork Sun /* Parity Error on byte */ 7800b66513bSYork Sun #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 7810b66513bSYork Sun /* Parity Error reported in addr or data phase */ 7820b66513bSYork Sun #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 7830b66513bSYork Sun 7840b66513bSYork Sun /* 7850b66513bSYork Sun * GPCM Status Register (GPCM_STAT) 7860b66513bSYork Sun */ 7870b66513bSYork Sun #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 7880b66513bSYork Sun 7890b66513bSYork Sun 7900b66513bSYork Sun #ifndef __ASSEMBLY__ 7910b66513bSYork Sun #include <asm/io.h> 7920b66513bSYork Sun 7930b66513bSYork Sun extern void print_ifc_regs(void); 7940b66513bSYork Sun extern void init_early_memctl_regs(void); 795e77224e2SYork Sun void init_final_memctl_regs(void); 7960b66513bSYork Sun 79739b0bbbbSJaiprakash Singh #define IFC_RREGS_4KOFFSET (4*1024) 79839b0bbbbSJaiprakash Singh #define IFC_RREGS_64KOFFSET (64*1024) 7990b66513bSYork Sun 80039b0bbbbSJaiprakash Singh #define IFC_FCM_BASE_ADDR \ 80139b0bbbbSJaiprakash Singh ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) 8020b66513bSYork Sun 80339b0bbbbSJaiprakash Singh #define get_ifc_cspr_ext(i) \ 80439b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) 80539b0bbbbSJaiprakash Singh #define get_ifc_cspr(i) \ 80639b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) 80739b0bbbbSJaiprakash Singh #define get_ifc_csor_ext(i) \ 80839b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) 80939b0bbbbSJaiprakash Singh #define get_ifc_csor(i) \ 81039b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) 81139b0bbbbSJaiprakash Singh #define get_ifc_amask(i) \ 81239b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) 81339b0bbbbSJaiprakash Singh #define get_ifc_ftim(i, j) \ 81439b0bbbbSJaiprakash Singh (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) 8151b4175d6SPrabhakar Kushwaha #define set_ifc_cspr_ext(i, v) \ 81639b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) 81739b0bbbbSJaiprakash Singh #define set_ifc_cspr(i, v) \ 81839b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) 8191b4175d6SPrabhakar Kushwaha #define set_ifc_csor_ext(i, v) \ 82039b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) 82139b0bbbbSJaiprakash Singh #define set_ifc_csor(i, v) \ 82239b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) 82339b0bbbbSJaiprakash Singh #define set_ifc_amask(i, v) \ 82439b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) 8250b66513bSYork Sun #define set_ifc_ftim(i, j, v) \ 82639b0bbbbSJaiprakash Singh (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) 8270b66513bSYork Sun 8280b66513bSYork Sun enum ifc_chip_sel { 8290b66513bSYork Sun IFC_CS0, 8300b66513bSYork Sun IFC_CS1, 8310b66513bSYork Sun IFC_CS2, 8320b66513bSYork Sun IFC_CS3, 8330b66513bSYork Sun IFC_CS4, 8340b66513bSYork Sun IFC_CS5, 8350b66513bSYork Sun IFC_CS6, 8360b66513bSYork Sun IFC_CS7, 8370b66513bSYork Sun }; 8380b66513bSYork Sun 8390b66513bSYork Sun enum ifc_ftims { 8400b66513bSYork Sun IFC_FTIM0, 8410b66513bSYork Sun IFC_FTIM1, 8420b66513bSYork Sun IFC_FTIM2, 8430b66513bSYork Sun IFC_FTIM3, 8440b66513bSYork Sun }; 8450b66513bSYork Sun 8460b66513bSYork Sun /* 8470b66513bSYork Sun * IFC Controller NAND Machine registers 8480b66513bSYork Sun */ 8490b66513bSYork Sun struct fsl_ifc_nand { 8500b66513bSYork Sun u32 ncfgr; 8510b66513bSYork Sun u32 res1[0x4]; 8520b66513bSYork Sun u32 nand_fcr0; 8530b66513bSYork Sun u32 nand_fcr1; 8540b66513bSYork Sun u32 res2[0x8]; 8550b66513bSYork Sun u32 row0; 8560b66513bSYork Sun u32 res3; 8570b66513bSYork Sun u32 col0; 8580b66513bSYork Sun u32 res4; 8590b66513bSYork Sun u32 row1; 8600b66513bSYork Sun u32 res5; 8610b66513bSYork Sun u32 col1; 8620b66513bSYork Sun u32 res6; 8630b66513bSYork Sun u32 row2; 8640b66513bSYork Sun u32 res7; 8650b66513bSYork Sun u32 col2; 8660b66513bSYork Sun u32 res8; 8670b66513bSYork Sun u32 row3; 8680b66513bSYork Sun u32 res9; 8690b66513bSYork Sun u32 col3; 8700b66513bSYork Sun u32 res10[0x24]; 8710b66513bSYork Sun u32 nand_fbcr; 8720b66513bSYork Sun u32 res11; 8730b66513bSYork Sun u32 nand_fir0; 8740b66513bSYork Sun u32 nand_fir1; 8750b66513bSYork Sun u32 nand_fir2; 8760b66513bSYork Sun u32 res12[0x10]; 8770b66513bSYork Sun u32 nand_csel; 8780b66513bSYork Sun u32 res13; 8790b66513bSYork Sun u32 nandseq_strt; 8800b66513bSYork Sun u32 res14; 8810b66513bSYork Sun u32 nand_evter_stat; 8820b66513bSYork Sun u32 res15; 8830b66513bSYork Sun u32 pgrdcmpl_evt_stat; 8840b66513bSYork Sun u32 res16[0x2]; 8850b66513bSYork Sun u32 nand_evter_en; 8860b66513bSYork Sun u32 res17[0x2]; 8870b66513bSYork Sun u32 nand_evter_intr_en; 88839b0bbbbSJaiprakash Singh u32 nand_vol_addr_stat; 88939b0bbbbSJaiprakash Singh u32 res18; 8900b66513bSYork Sun u32 nand_erattr0; 8910b66513bSYork Sun u32 nand_erattr1; 8920b66513bSYork Sun u32 res19[0x10]; 8930b66513bSYork Sun u32 nand_fsr; 894f195fad1SJagdish Gediya u32 res20[0x1]; 895f195fad1SJagdish Gediya u32 nand_eccstat[8]; 89639b0bbbbSJaiprakash Singh u32 res21[0x1c]; 8970b66513bSYork Sun u32 nanndcr; 8980b66513bSYork Sun u32 res22[0x2]; 8990b66513bSYork Sun u32 nand_autoboot_trgr; 9000b66513bSYork Sun u32 res23; 9010b66513bSYork Sun u32 nand_mdr; 90239b0bbbbSJaiprakash Singh u32 res24[0x1c]; 90339b0bbbbSJaiprakash Singh u32 nand_dll_lowcfg0; 90439b0bbbbSJaiprakash Singh u32 nand_dll_lowcfg1; 90539b0bbbbSJaiprakash Singh u32 res25; 90639b0bbbbSJaiprakash Singh u32 nand_dll_lowstat; 90739b0bbbbSJaiprakash Singh u32 res26[0x3C]; 9080b66513bSYork Sun }; 9090b66513bSYork Sun 9100b66513bSYork Sun /* 9110b66513bSYork Sun * IFC controller NOR Machine registers 9120b66513bSYork Sun */ 9130b66513bSYork Sun struct fsl_ifc_nor { 9140b66513bSYork Sun u32 nor_evter_stat; 9150b66513bSYork Sun u32 res1[0x2]; 9160b66513bSYork Sun u32 nor_evter_en; 9170b66513bSYork Sun u32 res2[0x2]; 9180b66513bSYork Sun u32 nor_evter_intr_en; 9190b66513bSYork Sun u32 res3[0x2]; 9200b66513bSYork Sun u32 nor_erattr0; 9210b66513bSYork Sun u32 nor_erattr1; 9220b66513bSYork Sun u32 nor_erattr2; 9230b66513bSYork Sun u32 res4[0x4]; 9240b66513bSYork Sun u32 norcr; 9250b66513bSYork Sun u32 res5[0xEF]; 9260b66513bSYork Sun }; 9270b66513bSYork Sun 9280b66513bSYork Sun /* 9290b66513bSYork Sun * IFC controller GPCM Machine registers 9300b66513bSYork Sun */ 9310b66513bSYork Sun struct fsl_ifc_gpcm { 9320b66513bSYork Sun u32 gpcm_evter_stat; 9330b66513bSYork Sun u32 res1[0x2]; 9340b66513bSYork Sun u32 gpcm_evter_en; 9350b66513bSYork Sun u32 res2[0x2]; 9360b66513bSYork Sun u32 gpcm_evter_intr_en; 9370b66513bSYork Sun u32 res3[0x2]; 9380b66513bSYork Sun u32 gpcm_erattr0; 9390b66513bSYork Sun u32 gpcm_erattr1; 9400b66513bSYork Sun u32 gpcm_erattr2; 9410b66513bSYork Sun u32 gpcm_stat; 9420b66513bSYork Sun }; 9430b66513bSYork Sun 9440b66513bSYork Sun #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 9450b66513bSYork Sun #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 9460b66513bSYork Sun #define IFC_CSPR_REG_LEN 148 9470b66513bSYork Sun #define IFC_AMASK_REG_LEN 144 9480b66513bSYork Sun #define IFC_CSOR_REG_LEN 144 9490b66513bSYork Sun #define IFC_FTIM_REG_LEN 576 9500b66513bSYork Sun 9510b66513bSYork Sun #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 9520b66513bSYork Sun CONFIG_SYS_FSL_IFC_BANK_COUNT 9530b66513bSYork Sun #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 9540b66513bSYork Sun CONFIG_SYS_FSL_IFC_BANK_COUNT 9550b66513bSYork Sun #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 9560b66513bSYork Sun CONFIG_SYS_FSL_IFC_BANK_COUNT 9570b66513bSYork Sun #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 9580b66513bSYork Sun CONFIG_SYS_FSL_IFC_BANK_COUNT 9590b66513bSYork Sun #else 9600b66513bSYork Sun #error IFC BANK count not vaild 9610b66513bSYork Sun #endif 9620b66513bSYork Sun #else 9630b66513bSYork Sun #error IFC BANK count not defined 9640b66513bSYork Sun #endif 9650b66513bSYork Sun 9660b66513bSYork Sun struct fsl_ifc_cspr { 9670b66513bSYork Sun u32 cspr_ext; 9680b66513bSYork Sun u32 cspr; 9690b66513bSYork Sun u32 res; 9700b66513bSYork Sun }; 9710b66513bSYork Sun 9720b66513bSYork Sun struct fsl_ifc_amask { 9730b66513bSYork Sun u32 amask; 9740b66513bSYork Sun u32 res[0x2]; 9750b66513bSYork Sun }; 9760b66513bSYork Sun 9770b66513bSYork Sun struct fsl_ifc_csor { 9780b66513bSYork Sun u32 csor; 9790b66513bSYork Sun u32 csor_ext; 9800b66513bSYork Sun u32 res; 9810b66513bSYork Sun }; 9820b66513bSYork Sun 9830b66513bSYork Sun struct fsl_ifc_ftim { 9840b66513bSYork Sun u32 ftim[4]; 9850b66513bSYork Sun u32 res[0x8]; 9860b66513bSYork Sun }; 9870b66513bSYork Sun 9880b66513bSYork Sun /* 98939b0bbbbSJaiprakash Singh * IFC Controller Global Registers 99039b0bbbbSJaiprakash Singh * FCM - Flash control machine 9910b66513bSYork Sun */ 99239b0bbbbSJaiprakash Singh 99339b0bbbbSJaiprakash Singh struct fsl_ifc_fcm { 9940b66513bSYork Sun u32 ifc_rev; 9950b66513bSYork Sun u32 res1[0x2]; 9960b66513bSYork Sun struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 9970b66513bSYork Sun u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 9980b66513bSYork Sun struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 9990b66513bSYork Sun u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 10000b66513bSYork Sun struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 10010b66513bSYork Sun u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 10020b66513bSYork Sun struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 10030b66513bSYork Sun u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 10040b66513bSYork Sun u32 rb_stat; 100539b0bbbbSJaiprakash Singh u32 rb_map; 100639b0bbbbSJaiprakash Singh u32 wp_map; 10070b66513bSYork Sun u32 ifc_gcr; 10080b66513bSYork Sun u32 res7[0x2]; 10090b66513bSYork Sun u32 cm_evter_stat; 10100b66513bSYork Sun u32 res8[0x2]; 10110b66513bSYork Sun u32 cm_evter_en; 10120b66513bSYork Sun u32 res9[0x2]; 10130b66513bSYork Sun u32 cm_evter_intr_en; 10140b66513bSYork Sun u32 res10[0x2]; 10150b66513bSYork Sun u32 cm_erattr0; 10160b66513bSYork Sun u32 cm_erattr1; 10170b66513bSYork Sun u32 res11[0x2]; 10180b66513bSYork Sun u32 ifc_ccr; 10190b66513bSYork Sun u32 ifc_csr; 102039b0bbbbSJaiprakash Singh u32 ddr_ccr_low; 102139b0bbbbSJaiprakash Singh }; 102239b0bbbbSJaiprakash Singh 102339b0bbbbSJaiprakash Singh struct fsl_ifc_runtime { 10240b66513bSYork Sun struct fsl_ifc_nand ifc_nand; 10250b66513bSYork Sun struct fsl_ifc_nor ifc_nor; 10260b66513bSYork Sun struct fsl_ifc_gpcm ifc_gpcm; 10270b66513bSYork Sun }; 10280b66513bSYork Sun 102939b0bbbbSJaiprakash Singh struct fsl_ifc { 103039b0bbbbSJaiprakash Singh struct fsl_ifc_fcm *gregs; 103139b0bbbbSJaiprakash Singh struct fsl_ifc_runtime *rregs; 103239b0bbbbSJaiprakash Singh }; 103339b0bbbbSJaiprakash Singh 1034*9bd5fe70SPankit Garg struct ifc_regs { 1035*9bd5fe70SPankit Garg const char *name; 1036*9bd5fe70SPankit Garg u32 pr; 1037*9bd5fe70SPankit Garg u32 pr_ext; 1038*9bd5fe70SPankit Garg u32 amask; 1039*9bd5fe70SPankit Garg u32 or; 1040*9bd5fe70SPankit Garg u32 ftim[4]; 1041*9bd5fe70SPankit Garg u32 or_ext; 1042*9bd5fe70SPankit Garg u32 pr_final; 1043*9bd5fe70SPankit Garg u32 amask_final; 1044*9bd5fe70SPankit Garg }; 1045*9bd5fe70SPankit Garg 1046*9bd5fe70SPankit Garg struct ifc_regs_info { 1047*9bd5fe70SPankit Garg struct ifc_regs *regs; 1048*9bd5fe70SPankit Garg u32 cs_size; 1049*9bd5fe70SPankit Garg }; 1050*9bd5fe70SPankit Garg 10510b66513bSYork Sun #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 10520b66513bSYork Sun #undef CSPR_MSEL_NOR 10530b66513bSYork Sun #define CSPR_MSEL_NOR CSPR_MSEL_GPCM 10540b66513bSYork Sun #endif 10550b66513bSYork Sun #endif /* CONFIG_FSL_IFC */ 10560b66513bSYork Sun 10570b66513bSYork Sun #endif /* __ASSEMBLY__ */ 10580b66513bSYork Sun #endif /* __FSL_IFC_H */ 1059