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/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5253.h16 #define PLL_PLLCR (0x000180)
18 #define SIM_RSR (0x000000)
19 #define SIM_SYPCR (0x000001)
20 #define SIM_SWIVR (0x000002)
21 #define SIM_SWSR (0x000003)
22 #define SIM_MPARK (0x00000C)
25 #define SIM_RSR_SWTR (0x20)
26 #define SIM_RSR_HRST (0x80)
29 #define CIM_MISCCR (0x000500)
30 #define CIM_ATA_DADDR (0x000504)
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/openbmc/linux/drivers/scsi/aic94xx/
H A Daic94xx_sds.h17 #define FLASH_MANUF_ID_AMD 0x01
18 #define FLASH_MANUF_ID_ST 0x20
19 #define FLASH_MANUF_ID_FUJITSU 0x04
20 #define FLASH_MANUF_ID_MACRONIX 0xC2
21 #define FLASH_MANUF_ID_INTEL 0x89
22 #define FLASH_MANUF_ID_UNKNOWN 0xFF
24 #define FLASH_DEV_ID_AM29LV008BT 0x3E
25 #define FLASH_DEV_ID_AM29LV800DT 0xDA
26 #define FLASH_DEV_ID_STM29W800DT 0xD7
27 #define FLASH_DEV_ID_STM29LV640 0xDE
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/openbmc/linux/arch/powerpc/include/asm/nohash/
H A Dpte-e500.h13 #define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
14 #define _PAGE_SW1 0x000002
15 #define _PAGE_BAP_SR 0x000004
16 #define _PAGE_BAP_UR 0x000008
17 #define _PAGE_BAP_SW 0x000010
18 #define _PAGE_BAP_UW 0x000020
19 #define _PAGE_BAP_SX 0x000040
20 #define _PAGE_BAP_UX 0x000080
21 #define _PAGE_PSIZE_MSK 0x000f00
22 #define _PAGE_PSIZE_4K 0x000200
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/openbmc/u-boot/tools/
H A Dzynqmpimage.h9 * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16)
17 #define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
18 #define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
19 #define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
20 #define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
21 #define HEADER_CPU_SELECT_MASK (0x3 << 10)
22 #define HEADER_CPU_SELECT_R5_SINGLE (0x0 << 10)
23 #define HEADER_CPU_SELECT_A53_32BIT (0x1 << 10)
24 #define HEADER_CPU_SELECT_A53_64BIT (0x2 << 10)
25 #define HEADER_CPU_SELECT_R5_DUAL (0x3 << 10)
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml32 - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
33 - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
34 - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
41 node bindings, describing it as PF 5 of device 0, bus 0.
45 EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
51 - phy-mode = "sgmii": on ports 0, 1, 2, 3
52 - phy-mode = "qsgmii": on ports 0, 1, 2, 3
53 - phy-mode = "usxgmii": on ports 0, 1, 2, 3
54 - phy-mode = "1000base-x": on ports 0, 1, 2, 3
55 - phy-mode = "2500base-x": on ports 0, 1, 2, 3
[all …]
/openbmc/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c14 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
42 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
45 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
50 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
53 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
60 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4),
64 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4),
67 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4),
72 REG(ANA_ADVLEARN, 0x009000),
73 REG(ANA_VLANMASK, 0x009004),
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
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