Home
last modified time | relevance | path

Searched +full:0 +full:x0000ff00 (Results 1 – 25 of 510) sorted by relevance

12345678910>>...21

/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
[all …]
H A Drt2500pci.h20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
[all …]
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
H A Drt61pci.h20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
[all …]
H A Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dpreg_alias.c32 "%0 = C4\n" in preg_alias()
46 "%0 = C5:4\n" in preg_alias_pair()
66 "%0 = p0\n\t" in creg_alias()
78 uint64_t cval_pair = (0xdeadbeefULL << 32) | cval; in creg_alias_pair()
82 "%0 = p0\n\t" in creg_alias_pair()
92 check32(c5, 0xdeadbeef); in creg_alias_pair()
103 uint32_t old_val = 0x0000001c; in test_packet()
111 " if (!p2) %0 = %3\n\t" in test_packet()
114 : "r"(0xffffffff), "r"(0xff00ffff), "r"(0x837ed653) in test_packet()
119 result = 0xffffffff; in test_packet()
[all …]
H A Dload_unpack.c22 * r0 = memubh(r1+#0)
45 for (int i = 0; i < 16; i++) { in init_buf()
46 int sign = i % 2 == 0 ? 0x80 : 0; in init_buf()
57 "%0 = mem" #SZ "(%1+#" #OFF ")\n\t" \
70 BxW_LOAD_io_##SIGN(result, buf, 0 * (SIZE)); \
81 TEST_io(loadbzw2_io, int32_t, Z, 2, 0x00000000,
82 0x00020081, 0x00040083, 0x00060085, 0x00080087)
83 TEST_io(loadbsw2_io, int32_t, S, 2, 0x0000ff00,
84 0x00020081, 0x00040083, 0x00060085, 0x00080087)
85 TEST_io(loadbzw4_io, int64_t, Z, 4, 0x0000000000000000LL,
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dtable.c6 0x800, 0x80040000,
7 0x804, 0x00000003,
8 0x808, 0x0000FC00,
9 0x80C, 0x0000000A,
10 0x810, 0x10001331,
11 0x814, 0x020C3D10,
12 0x818, 0x02200385,
13 0x81C, 0x00000000,
14 0x820, 0x01000100,
15 0x824, 0x00390204,
[all …]
/openbmc/linux/arch/mips/include/asm/mach-rc32434/
H A Deth.h33 #define ETH0_BASE_ADDR 0x18060000
84 #define ETH_INT_FC_EN (1 << 0)
90 #define ETH_INT_FC_IOC 0x000000c0
93 #define ETH_FIFI_TT_TTH_BIT 0
94 #define ETH_FIFO_TT_TTH 0x0000007f
97 #define ETH_ARC_PRO (1 << 0)
103 #define ETH_SAL_BYTE_5 0x000000ff
104 #define ETH_SAL_BYTE_4 0x0000ff00
105 #define ETH_SAL_BYTE_3 0x00ff0000
106 #define ETH_SAL_BYTE_2 0xff000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/iproc-common/
H A Dtimer.h15 #define TIMER_PVT_LOAD_OFFSET 0x00000000
16 #define TIMER_PVT_COUNTER_OFFSET 0x00000004
17 #define TIMER_PVT_CTRL_OFFSET 0x00000008
18 #define TIMER_PVT_STATUS_OFFSET 0x0000000C
19 #define TIMER_PVT_TIM_CTRL_TIM_EN 0x00000001
20 #define TIMER_PVT_TIM_CTRL_AUTO_RELD 0x00000002
21 #define TIMER_PVT_TIM_CTRL_INT_EN 0x00000004
22 #define TIMER_PVT_TIM_CTRL_PRESC_MASK 0x0000FF00
23 #define TIMER_PVT_TIM_INT_STATUS_SET 0x00000001
26 #define TIMER_GLB_LOW_OFFSET 0x00000000
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dpxa168fb.h6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Ddt2817.c24 * [0] - I/O port base base address
30 #define DT2817_CR 0
39 unsigned int oe = 0; in dt2817_dio_insn_config()
44 mask = 0x000000ff; in dt2817_dio_insn_config()
46 mask = 0x0000ff00; in dt2817_dio_insn_config()
48 mask = 0x00ff0000; in dt2817_dio_insn_config()
50 mask = 0xff000000; in dt2817_dio_insn_config()
56 if (s->io_bits & 0x000000ff) in dt2817_dio_insn_config()
57 oe |= 0x1; in dt2817_dio_insn_config()
58 if (s->io_bits & 0x0000ff00) in dt2817_dio_insn_config()
[all …]
/openbmc/u-boot/board/is1/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c13 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
14 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
15 #define SERDES_COMLANE_REGS 0x0a00
16 #define SERDES_WIZ_REGS 0x1fc0
18 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
19 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
20 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
21 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
22 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
23 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dsleep.S72 mov r4, #TCMIF_ASM_BASE & 0xff000000
73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
[all …]
H A Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
43 mov r4, #0x0700 @ let the clocks settle
44 orr r4, r4, #0x00ff
46 cmp r4, #0
49 lock: ldrh r4, [r2], #0 @ read back dpll value
[all …]
/openbmc/linux/drivers/net/ethernet/engleder/
H A Dtsnep_hw.h12 #define ECM_TYPE 0x0000
13 #define ECM_REVISION_MASK 0x000000FF
14 #define ECM_REVISION_SHIFT 0
15 #define ECM_VERSION_MASK 0x0000FF00
17 #define ECM_QUEUE_COUNT_MASK 0x00070000
19 #define ECM_GATE_CONTROL 0x02000000
22 #define ECM_SYSTEM_TIME_LOW 0x0008
23 #define ECM_SYSTEM_TIME_HIGH 0x000C
26 #define ECM_CLOCK_RATE 0x0010
27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dmac.h30 AR_RTSCTSQual##_index : 0))
34 AR_2040_##_index : 0) \
36 AR_GI##_index : 0) \
38 AR_STBC##_index : 0))
71 #define ATH9K_TXERR_XRETRY 0x01
72 #define ATH9K_TXERR_FILT 0x02
73 #define ATH9K_TXERR_FIFO 0x04
74 #define ATH9K_TXERR_XTXOP 0x08
75 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
76 #define ATH9K_TX_ACKED 0x20
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/lvgl/files/
H A D0002-fix-sdl-handle-both-LV_IMAGE_SRC_FILE-and-LV_IMAGE_S.patch42 + 0x00FF0000,
43 + 0x0000FF00,
44 + 0x000000FF,
45 + 0xFF000000
47 + 0x0000FF00,
48 + 0x00FF0000,
49 + 0xFF000000,
50 + 0x000000FF
62 2.43.0
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0_internal.h26 #define HW_ATL_B0_MAC 0U
36 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
38 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
39 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
40 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
42 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
43 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
44 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
45 #define HW_ATL_B0_TXD_CTL_DD (0x00100000)
46 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
[all …]
/openbmc/linux/drivers/media/rc/img-ir/
H A Dimg-ir.h20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]

12345678910>>...21