175a6faf6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2bab6de8fSDavid VomLehn /* 3bab6de8fSDavid VomLehn * aQuantia Corporation Network Driver 494ad9455SEgor Pomozov * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5bab6de8fSDavid VomLehn */ 6bab6de8fSDavid VomLehn 7bab6de8fSDavid VomLehn /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific 8bab6de8fSDavid VomLehn * constants. 9bab6de8fSDavid VomLehn */ 10bab6de8fSDavid VomLehn 11bab6de8fSDavid VomLehn #ifndef HW_ATL_B0_INTERNAL_H 12bab6de8fSDavid VomLehn #define HW_ATL_B0_INTERNAL_H 13bab6de8fSDavid VomLehn 14bab6de8fSDavid VomLehn #include "../aq_common.h" 15bab6de8fSDavid VomLehn 16d85fc17bSIgor Russkikh #define HW_ATL_B0_MTU_JUMBO 16352U 17bab6de8fSDavid VomLehn #define HW_ATL_B0_MTU 1514U 18bab6de8fSDavid VomLehn 19bab6de8fSDavid VomLehn #define HW_ATL_B0_TX_RINGS 4U 20bab6de8fSDavid VomLehn #define HW_ATL_B0_RX_RINGS 4U 21bab6de8fSDavid VomLehn 22bab6de8fSDavid VomLehn #define HW_ATL_B0_RINGS_MAX 32U 23bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_SIZE (16U) 24bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_SIZE (16U) 25bab6de8fSDavid VomLehn 26bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC 0U 27bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC_MIN 1U 28bab6de8fSDavid VomLehn #define HW_ATL_B0_MAC_MAX 33U 29bab6de8fSDavid VomLehn 30bab6de8fSDavid VomLehn /* UCAST/MCAST filters */ 31bab6de8fSDavid VomLehn #define HW_ATL_B0_UCAST_FILTERS_MAX 38 32bab6de8fSDavid VomLehn #define HW_ATL_B0_MCAST_FILTERS_MAX 8 33bab6de8fSDavid VomLehn 34bab6de8fSDavid VomLehn /* interrupts */ 35bab6de8fSDavid VomLehn #define HW_ATL_B0_ERR_INT 8U 36bab6de8fSDavid VomLehn #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU) 37bab6de8fSDavid VomLehn 38bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000) 39bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000) 40bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000) 41bab6de8fSDavid VomLehn 42bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001) 43bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002) 44bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) 45bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_DD (0x00100000) 46bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_EOP (0x00200000) 47bab6de8fSDavid VomLehn 48bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) 49bab6de8fSDavid VomLehn 50bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) 51bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) 52bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) 53bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) 54bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) 55bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) 56bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) 57bab6de8fSDavid VomLehn 58bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) 59bab6de8fSDavid VomLehn #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) 60bab6de8fSDavid VomLehn 61bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U 62bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_STATE_ADR 0x036CU 63bab6de8fSDavid VomLehn 64bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU 65bab6de8fSDavid VomLehn #define HW_ATL_B0_MPI_SPEED_SHIFT 16U 66bab6de8fSDavid VomLehn 67bab6de8fSDavid VomLehn #define HW_ATL_B0_TXBUF_MAX 160U 6894ad9455SEgor Pomozov #define HW_ATL_B0_PTP_TXBUF_SIZE 8U 6994ad9455SEgor Pomozov 70bab6de8fSDavid VomLehn #define HW_ATL_B0_RXBUF_MAX 320U 7194ad9455SEgor Pomozov #define HW_ATL_B0_PTP_RXBUF_SIZE 16U 72bab6de8fSDavid VomLehn 73bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U 74bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U 75bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_HASHKEY_BITS 320U 76bab6de8fSDavid VomLehn 77bab6de8fSDavid VomLehn #define HW_ATL_B0_TCRSS_4_8 1 788ce84271SDmitry Bezrukov #define HW_ATL_B0_TC_MAX 8U 79bab6de8fSDavid VomLehn #define HW_ATL_B0_RSS_MAX 8U 80bab6de8fSDavid VomLehn 811eef4757SNikita Danilov #define HW_ATL_B0_LRO_RXD_MAX 16U 82bab6de8fSDavid VomLehn #define HW_ATL_B0_RS_SLIP_ENABLED 0U 83bab6de8fSDavid VomLehn 84bab6de8fSDavid VomLehn /* (256k -1(max pay_len) - 54(header)) */ 85bab6de8fSDavid VomLehn #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U 86bab6de8fSDavid VomLehn 87bab6de8fSDavid VomLehn /* (256k -1(max pay_len) - 74(header)) */ 88bab6de8fSDavid VomLehn #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U 89bab6de8fSDavid VomLehn 90bab6de8fSDavid VomLehn #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U 91bab6de8fSDavid VomLehn #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU 92bab6de8fSDavid VomLehn 93bab6de8fSDavid VomLehn #define HW_ATL_B0_FW_SEMA_RAM 0x2U 94bab6de8fSDavid VomLehn 95bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) 96bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) 97bab6de8fSDavid VomLehn 98bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) 99bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) 100bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) 101bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) 102bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) 103bab6de8fSDavid VomLehn 104bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ 105bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ 106bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) 107bab6de8fSDavid VomLehn #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) 108bab6de8fSDavid VomLehn 109bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_DD (0x1) 110bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_NCEA0 (0x1) 111bab6de8fSDavid VomLehn 112bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) 113161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT (0x0) 114bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) 115161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT (0x4) 116bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) 117161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT (0x13) 118bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) 119bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) 120161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT (0x16) 121161dea83SIgor Russkikh 122161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN BIT(5) 123161dea83SIgor Russkikh #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE BIT(6) 124bab6de8fSDavid VomLehn 125bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) 126bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) 127bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) 128bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) 129bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) 130bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) 131bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) 132bab6de8fSDavid VomLehn #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) 133bab6de8fSDavid VomLehn 134bab6de8fSDavid VomLehn #define L2_FILTER_ACTION_DISCARD (0x0) 135bab6de8fSDavid VomLehn #define L2_FILTER_ACTION_HOST (0x1) 136bab6de8fSDavid VomLehn 137bab6de8fSDavid VomLehn #define HW_ATL_B0_UCP_0X370_REG (0x370) 138bab6de8fSDavid VomLehn 139bab6de8fSDavid VomLehn #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) 140bab6de8fSDavid VomLehn 141bab6de8fSDavid VomLehn #define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U 142bab6de8fSDavid VomLehn 143b82ee71aSIgor Russkikh #define HW_ATL_INTR_MODER_MAX 0x1FF 144b82ee71aSIgor Russkikh #define HW_ATL_INTR_MODER_MIN 0xFF 145b82ee71aSIgor Russkikh 146c1af5427SAnton Mikaev #define HW_ATL_B0_MIN_RXD \ 147c1af5427SAnton Mikaev (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) 148c1af5427SAnton Mikaev #define HW_ATL_B0_MIN_TXD \ 149c1af5427SAnton Mikaev (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) 150c1af5427SAnton Mikaev 151c1af5427SAnton Mikaev #define HW_ATL_B0_MAX_RXD 8184U 152c1af5427SAnton Mikaev #define HW_ATL_B0_MAX_TXD 8184U 153c1af5427SAnton Mikaev 15440f05e5bSMark Starovoytov #define HW_ATL_RSS_DISABLED 0x00000000U 15540f05e5bSMark Starovoytov #define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS 0xA2222222U 15640f05e5bSMark Starovoytov #define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS 0x80003333U 15740f05e5bSMark Starovoytov 158bab6de8fSDavid VomLehn /* HW layer capabilities */ 159bab6de8fSDavid VomLehn 160bab6de8fSDavid VomLehn #endif /* HW_ATL_B0_INTERNAL_H */ 161