1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 299f143b3STony Lindgren/* 399f143b3STony Lindgren * linux/arch/arm/plat-omap/sram-fn.S 499f143b3STony Lindgren * 599f143b3STony Lindgren * Functions that need to be run in internal SRAM 699f143b3STony Lindgren */ 799f143b3STony Lindgren 899f143b3STony Lindgren#include <linux/linkage.h> 9*7e0a9e62SArnd Bergmann#include <linux/soc/ti/omap1-io.h> 102e3ee9f4STony Lindgren 1199f143b3STony Lindgren#include <asm/assembler.h> 122e3ee9f4STony Lindgren 13*7e0a9e62SArnd Bergmann#include "hardware.h" 142e3ee9f4STony Lindgren#include "iomap.h" 152e3ee9f4STony Lindgren 1699f143b3STony Lindgren .text 1799f143b3STony Lindgren 1899f143b3STony Lindgren/* 1999f143b3STony Lindgren * Reprograms ULPD and CKCTL. 2099f143b3STony Lindgren */ 21b6338bdcSJean Pihet .align 3 22c2d43e39STony LindgrenENTRY(omap1_sram_reprogram_clock) 2399f143b3STony Lindgren stmfd sp!, {r0 - r12, lr} @ save registers on stack 2499f143b3STony Lindgren 2594113260STony Lindgren mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 2694113260STony Lindgren orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 2794113260STony Lindgren orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 2899f143b3STony Lindgren 2994113260STony Lindgren mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 3094113260STony Lindgren orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 3194113260STony Lindgren orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 3299f143b3STony Lindgren 3399f143b3STony Lindgren tst r0, #1 << 4 @ want lock mode? 3499f143b3STony Lindgren beq newck @ nope 3599f143b3STony Lindgren bic r0, r0, #1 << 4 @ else clear lock bit 3699f143b3STony Lindgren strh r0, [r2] @ set dpll into bypass mode 3799f143b3STony Lindgren orr r0, r0, #1 << 4 @ set lock bit again 3899f143b3STony Lindgren 3999f143b3STony Lindgrennewck: 4099f143b3STony Lindgren strh r1, [r3] @ write new ckctl value 4199f143b3STony Lindgren strh r0, [r2] @ write new dpll value 4299f143b3STony Lindgren 4399f143b3STony Lindgren mov r4, #0x0700 @ let the clocks settle 4499f143b3STony Lindgren orr r4, r4, #0x00ff 4599f143b3STony Lindgrendelay: sub r4, r4, #1 4699f143b3STony Lindgren cmp r4, #0 4799f143b3STony Lindgren bne delay 4899f143b3STony Lindgren 4999f143b3STony Lindgrenlock: ldrh r4, [r2], #0 @ read back dpll value 5099f143b3STony Lindgren tst r0, #1 << 4 @ want lock mode? 5199f143b3STony Lindgren beq out @ nope 5299f143b3STony Lindgren tst r4, #1 << 0 @ dpll rate locked? 5399f143b3STony Lindgren beq lock @ try again 5499f143b3STony Lindgren 5599f143b3STony Lindgrenout: 5699f143b3STony Lindgren ldmfd sp!, {r0 - r12, pc} @ restore regs and return 57c2d43e39STony LindgrenENTRY(omap1_sram_reprogram_clock_sz) 58c2d43e39STony Lindgren .word . - omap1_sram_reprogram_clock 59