1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 	<http://rt2x00.serialmonkey.com>
5 
6  */
7 
8 /*
9 	Module: rt2400pci
10 	Abstract: Data structures and registers for the rt2400pci module.
11 	Supported chipsets: RT2460.
12  */
13 
14 #ifndef RT2400PCI_H
15 #define RT2400PCI_H
16 
17 /*
18  * RF chip defines.
19  */
20 #define RF2420				0x0000
21 #define RF2421				0x0001
22 
23 /*
24  * Signal information.
25  * Default offset is required for RSSI <-> dBm conversion.
26  */
27 #define DEFAULT_RSSI_OFFSET		100
28 
29 /*
30  * Register layout information.
31  */
32 #define CSR_REG_BASE			0x0000
33 #define CSR_REG_SIZE			0x014c
34 #define EEPROM_BASE			0x0000
35 #define EEPROM_SIZE			0x0100
36 #define BBP_BASE			0x0000
37 #define BBP_SIZE			0x0020
38 #define RF_BASE				0x0004
39 #define RF_SIZE				0x000c
40 
41 /*
42  * Number of TX queues.
43  */
44 #define NUM_TX_QUEUES			2
45 
46 /*
47  * Control/Status Registers(CSR).
48  * Some values are set in TU, whereas 1 TU == 1024 us.
49  */
50 
51 /*
52  * CSR0: ASIC revision number.
53  */
54 #define CSR0				0x0000
55 #define CSR0_REVISION			FIELD32(0x0000ffff)
56 
57 /*
58  * CSR1: System control register.
59  * SOFT_RESET: Software reset, 1: reset, 0: normal.
60  * BBP_RESET: Hardware reset, 1: reset, 0, release.
61  * HOST_READY: Host ready after initialization.
62  */
63 #define CSR1				0x0004
64 #define CSR1_SOFT_RESET			FIELD32(0x00000001)
65 #define CSR1_BBP_RESET			FIELD32(0x00000002)
66 #define CSR1_HOST_READY			FIELD32(0x00000004)
67 
68 /*
69  * CSR2: System admin status register (invalid).
70  */
71 #define CSR2				0x0008
72 
73 /*
74  * CSR3: STA MAC address register 0.
75  */
76 #define CSR3				0x000c
77 #define CSR3_BYTE0			FIELD32(0x000000ff)
78 #define CSR3_BYTE1			FIELD32(0x0000ff00)
79 #define CSR3_BYTE2			FIELD32(0x00ff0000)
80 #define CSR3_BYTE3			FIELD32(0xff000000)
81 
82 /*
83  * CSR4: STA MAC address register 1.
84  */
85 #define CSR4				0x0010
86 #define CSR4_BYTE4			FIELD32(0x000000ff)
87 #define CSR4_BYTE5			FIELD32(0x0000ff00)
88 
89 /*
90  * CSR5: BSSID register 0.
91  */
92 #define CSR5				0x0014
93 #define CSR5_BYTE0			FIELD32(0x000000ff)
94 #define CSR5_BYTE1			FIELD32(0x0000ff00)
95 #define CSR5_BYTE2			FIELD32(0x00ff0000)
96 #define CSR5_BYTE3			FIELD32(0xff000000)
97 
98 /*
99  * CSR6: BSSID register 1.
100  */
101 #define CSR6				0x0018
102 #define CSR6_BYTE4			FIELD32(0x000000ff)
103 #define CSR6_BYTE5			FIELD32(0x0000ff00)
104 
105 /*
106  * CSR7: Interrupt source register.
107  * Write 1 to clear interrupt.
108  * TBCN_EXPIRE: Beacon timer expired interrupt.
109  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
110  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
111  * TXDONE_TXRING: Tx ring transmit done interrupt.
112  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
113  * TXDONE_PRIORING: Priority ring transmit done interrupt.
114  * RXDONE: Receive done interrupt.
115  */
116 #define CSR7				0x001c
117 #define CSR7_TBCN_EXPIRE		FIELD32(0x00000001)
118 #define CSR7_TWAKE_EXPIRE		FIELD32(0x00000002)
119 #define CSR7_TATIMW_EXPIRE		FIELD32(0x00000004)
120 #define CSR7_TXDONE_TXRING		FIELD32(0x00000008)
121 #define CSR7_TXDONE_ATIMRING		FIELD32(0x00000010)
122 #define CSR7_TXDONE_PRIORING		FIELD32(0x00000020)
123 #define CSR7_RXDONE			FIELD32(0x00000040)
124 
125 /*
126  * CSR8: Interrupt mask register.
127  * Write 1 to mask interrupt.
128  * TBCN_EXPIRE: Beacon timer expired interrupt.
129  * TWAKE_EXPIRE: Wakeup timer expired interrupt.
130  * TATIMW_EXPIRE: Timer of atim window expired interrupt.
131  * TXDONE_TXRING: Tx ring transmit done interrupt.
132  * TXDONE_ATIMRING: Atim ring transmit done interrupt.
133  * TXDONE_PRIORING: Priority ring transmit done interrupt.
134  * RXDONE: Receive done interrupt.
135  */
136 #define CSR8				0x0020
137 #define CSR8_TBCN_EXPIRE		FIELD32(0x00000001)
138 #define CSR8_TWAKE_EXPIRE		FIELD32(0x00000002)
139 #define CSR8_TATIMW_EXPIRE		FIELD32(0x00000004)
140 #define CSR8_TXDONE_TXRING		FIELD32(0x00000008)
141 #define CSR8_TXDONE_ATIMRING		FIELD32(0x00000010)
142 #define CSR8_TXDONE_PRIORING		FIELD32(0x00000020)
143 #define CSR8_RXDONE			FIELD32(0x00000040)
144 
145 /*
146  * CSR9: Maximum frame length register.
147  * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
148  */
149 #define CSR9				0x0024
150 #define CSR9_MAX_FRAME_UNIT		FIELD32(0x00000f80)
151 
152 /*
153  * CSR11: Back-off control register.
154  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
155  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
156  * SLOT_TIME: Slot time, default is 20us for 802.11b.
157  * LONG_RETRY: Long retry count.
158  * SHORT_RETRY: Short retry count.
159  */
160 #define CSR11				0x002c
161 #define CSR11_CWMIN			FIELD32(0x0000000f)
162 #define CSR11_CWMAX			FIELD32(0x000000f0)
163 #define CSR11_SLOT_TIME			FIELD32(0x00001f00)
164 #define CSR11_LONG_RETRY		FIELD32(0x00ff0000)
165 #define CSR11_SHORT_RETRY		FIELD32(0xff000000)
166 
167 /*
168  * CSR12: Synchronization configuration register 0.
169  * All units in 1/16 TU.
170  * BEACON_INTERVAL: Beacon interval, default is 100 TU.
171  * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
172  */
173 #define CSR12				0x0030
174 #define CSR12_BEACON_INTERVAL		FIELD32(0x0000ffff)
175 #define CSR12_CFP_MAX_DURATION		FIELD32(0xffff0000)
176 
177 /*
178  * CSR13: Synchronization configuration register 1.
179  * All units in 1/16 TU.
180  * ATIMW_DURATION: Atim window duration.
181  * CFP_PERIOD: Cfp period, default is 0 TU.
182  */
183 #define CSR13				0x0034
184 #define CSR13_ATIMW_DURATION		FIELD32(0x0000ffff)
185 #define CSR13_CFP_PERIOD		FIELD32(0x00ff0000)
186 
187 /*
188  * CSR14: Synchronization control register.
189  * TSF_COUNT: Enable tsf auto counting.
190  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
191  * TBCN: Enable tbcn with reload value.
192  * TCFP: Enable tcfp & cfp / cp switching.
193  * TATIMW: Enable tatimw & atim window switching.
194  * BEACON_GEN: Enable beacon generator.
195  * CFP_COUNT_PRELOAD: Cfp count preload value.
196  * TBCM_PRELOAD: Tbcn preload value in units of 64us.
197  */
198 #define CSR14				0x0038
199 #define CSR14_TSF_COUNT			FIELD32(0x00000001)
200 #define CSR14_TSF_SYNC			FIELD32(0x00000006)
201 #define CSR14_TBCN			FIELD32(0x00000008)
202 #define CSR14_TCFP			FIELD32(0x00000010)
203 #define CSR14_TATIMW			FIELD32(0x00000020)
204 #define CSR14_BEACON_GEN		FIELD32(0x00000040)
205 #define CSR14_CFP_COUNT_PRELOAD		FIELD32(0x0000ff00)
206 #define CSR14_TBCM_PRELOAD		FIELD32(0xffff0000)
207 
208 /*
209  * CSR15: Synchronization status register.
210  * CFP: ASIC is in contention-free period.
211  * ATIMW: ASIC is in ATIM window.
212  * BEACON_SENT: Beacon is send.
213  */
214 #define CSR15				0x003c
215 #define CSR15_CFP			FIELD32(0x00000001)
216 #define CSR15_ATIMW			FIELD32(0x00000002)
217 #define CSR15_BEACON_SENT		FIELD32(0x00000004)
218 
219 /*
220  * CSR16: TSF timer register 0.
221  */
222 #define CSR16				0x0040
223 #define CSR16_LOW_TSFTIMER		FIELD32(0xffffffff)
224 
225 /*
226  * CSR17: TSF timer register 1.
227  */
228 #define CSR17				0x0044
229 #define CSR17_HIGH_TSFTIMER		FIELD32(0xffffffff)
230 
231 /*
232  * CSR18: IFS timer register 0.
233  * SIFS: Sifs, default is 10 us.
234  * PIFS: Pifs, default is 30 us.
235  */
236 #define CSR18				0x0048
237 #define CSR18_SIFS			FIELD32(0x0000ffff)
238 #define CSR18_PIFS			FIELD32(0xffff0000)
239 
240 /*
241  * CSR19: IFS timer register 1.
242  * DIFS: Difs, default is 50 us.
243  * EIFS: Eifs, default is 364 us.
244  */
245 #define CSR19				0x004c
246 #define CSR19_DIFS			FIELD32(0x0000ffff)
247 #define CSR19_EIFS			FIELD32(0xffff0000)
248 
249 /*
250  * CSR20: Wakeup timer register.
251  * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
252  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
253  * AUTOWAKE: Enable auto wakeup / sleep mechanism.
254  */
255 #define CSR20				0x0050
256 #define CSR20_DELAY_AFTER_TBCN		FIELD32(0x0000ffff)
257 #define CSR20_TBCN_BEFORE_WAKEUP	FIELD32(0x00ff0000)
258 #define CSR20_AUTOWAKE			FIELD32(0x01000000)
259 
260 /*
261  * CSR21: EEPROM control register.
262  * RELOAD: Write 1 to reload eeprom content.
263  * TYPE_93C46: 1: 93c46, 0:93c66.
264  */
265 #define CSR21				0x0054
266 #define CSR21_RELOAD			FIELD32(0x00000001)
267 #define CSR21_EEPROM_DATA_CLOCK		FIELD32(0x00000002)
268 #define CSR21_EEPROM_CHIP_SELECT	FIELD32(0x00000004)
269 #define CSR21_EEPROM_DATA_IN		FIELD32(0x00000008)
270 #define CSR21_EEPROM_DATA_OUT		FIELD32(0x00000010)
271 #define CSR21_TYPE_93C46		FIELD32(0x00000020)
272 
273 /*
274  * CSR22: CFP control register.
275  * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
276  * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
277  */
278 #define CSR22				0x0058
279 #define CSR22_CFP_DURATION_REMAIN	FIELD32(0x0000ffff)
280 #define CSR22_RELOAD_CFP_DURATION	FIELD32(0x00010000)
281 
282 /*
283  * Transmit related CSRs.
284  * Some values are set in TU, whereas 1 TU == 1024 us.
285  */
286 
287 /*
288  * TXCSR0: TX Control Register.
289  * KICK_TX: Kick tx ring.
290  * KICK_ATIM: Kick atim ring.
291  * KICK_PRIO: Kick priority ring.
292  * ABORT: Abort all transmit related ring operation.
293  */
294 #define TXCSR0				0x0060
295 #define TXCSR0_KICK_TX			FIELD32(0x00000001)
296 #define TXCSR0_KICK_ATIM		FIELD32(0x00000002)
297 #define TXCSR0_KICK_PRIO		FIELD32(0x00000004)
298 #define TXCSR0_ABORT			FIELD32(0x00000008)
299 
300 /*
301  * TXCSR1: TX Configuration Register.
302  * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
303  * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
304  * TSF_OFFSET: Insert tsf offset.
305  * AUTORESPONDER: Enable auto responder which include ack & cts.
306  */
307 #define TXCSR1				0x0064
308 #define TXCSR1_ACK_TIMEOUT		FIELD32(0x000001ff)
309 #define TXCSR1_ACK_CONSUME_TIME		FIELD32(0x0003fe00)
310 #define TXCSR1_TSF_OFFSET		FIELD32(0x00fc0000)
311 #define TXCSR1_AUTORESPONDER		FIELD32(0x01000000)
312 
313 /*
314  * TXCSR2: Tx descriptor configuration register.
315  * TXD_SIZE: Tx descriptor size, default is 48.
316  * NUM_TXD: Number of tx entries in ring.
317  * NUM_ATIM: Number of atim entries in ring.
318  * NUM_PRIO: Number of priority entries in ring.
319  */
320 #define TXCSR2				0x0068
321 #define TXCSR2_TXD_SIZE			FIELD32(0x000000ff)
322 #define TXCSR2_NUM_TXD			FIELD32(0x0000ff00)
323 #define TXCSR2_NUM_ATIM			FIELD32(0x00ff0000)
324 #define TXCSR2_NUM_PRIO			FIELD32(0xff000000)
325 
326 /*
327  * TXCSR3: TX Ring Base address register.
328  */
329 #define TXCSR3				0x006c
330 #define TXCSR3_TX_RING_REGISTER		FIELD32(0xffffffff)
331 
332 /*
333  * TXCSR4: TX Atim Ring Base address register.
334  */
335 #define TXCSR4				0x0070
336 #define TXCSR4_ATIM_RING_REGISTER	FIELD32(0xffffffff)
337 
338 /*
339  * TXCSR5: TX Prio Ring Base address register.
340  */
341 #define TXCSR5				0x0074
342 #define TXCSR5_PRIO_RING_REGISTER	FIELD32(0xffffffff)
343 
344 /*
345  * TXCSR6: Beacon Base address register.
346  */
347 #define TXCSR6				0x0078
348 #define TXCSR6_BEACON_RING_REGISTER	FIELD32(0xffffffff)
349 
350 /*
351  * TXCSR7: Auto responder control register.
352  * AR_POWERMANAGEMENT: Auto responder power management bit.
353  */
354 #define TXCSR7				0x007c
355 #define TXCSR7_AR_POWERMANAGEMENT	FIELD32(0x00000001)
356 
357 /*
358  * Receive related CSRs.
359  * Some values are set in TU, whereas 1 TU == 1024 us.
360  */
361 
362 /*
363  * RXCSR0: RX Control Register.
364  * DISABLE_RX: Disable rx engine.
365  * DROP_CRC: Drop crc error.
366  * DROP_PHYSICAL: Drop physical error.
367  * DROP_CONTROL: Drop control frame.
368  * DROP_NOT_TO_ME: Drop not to me unicast frame.
369  * DROP_TODS: Drop frame tods bit is true.
370  * DROP_VERSION_ERROR: Drop version error frame.
371  * PASS_CRC: Pass all packets with crc attached.
372  */
373 #define RXCSR0				0x0080
374 #define RXCSR0_DISABLE_RX		FIELD32(0x00000001)
375 #define RXCSR0_DROP_CRC			FIELD32(0x00000002)
376 #define RXCSR0_DROP_PHYSICAL		FIELD32(0x00000004)
377 #define RXCSR0_DROP_CONTROL		FIELD32(0x00000008)
378 #define RXCSR0_DROP_NOT_TO_ME		FIELD32(0x00000010)
379 #define RXCSR0_DROP_TODS		FIELD32(0x00000020)
380 #define RXCSR0_DROP_VERSION_ERROR	FIELD32(0x00000040)
381 #define RXCSR0_PASS_CRC			FIELD32(0x00000080)
382 
383 /*
384  * RXCSR1: RX descriptor configuration register.
385  * RXD_SIZE: Rx descriptor size, default is 32b.
386  * NUM_RXD: Number of rx entries in ring.
387  */
388 #define RXCSR1				0x0084
389 #define RXCSR1_RXD_SIZE			FIELD32(0x000000ff)
390 #define RXCSR1_NUM_RXD			FIELD32(0x0000ff00)
391 
392 /*
393  * RXCSR2: RX Ring base address register.
394  */
395 #define RXCSR2				0x0088
396 #define RXCSR2_RX_RING_REGISTER		FIELD32(0xffffffff)
397 
398 /*
399  * RXCSR3: BBP ID register for Rx operation.
400  * BBP_ID#: BBP register # id.
401  * BBP_ID#_VALID: BBP register # id is valid or not.
402  */
403 #define RXCSR3				0x0090
404 #define RXCSR3_BBP_ID0			FIELD32(0x0000007f)
405 #define RXCSR3_BBP_ID0_VALID		FIELD32(0x00000080)
406 #define RXCSR3_BBP_ID1			FIELD32(0x00007f00)
407 #define RXCSR3_BBP_ID1_VALID		FIELD32(0x00008000)
408 #define RXCSR3_BBP_ID2			FIELD32(0x007f0000)
409 #define RXCSR3_BBP_ID2_VALID		FIELD32(0x00800000)
410 #define RXCSR3_BBP_ID3			FIELD32(0x7f000000)
411 #define RXCSR3_BBP_ID3_VALID		FIELD32(0x80000000)
412 
413 /*
414  * RXCSR4: BBP ID register for Rx operation.
415  * BBP_ID#: BBP register # id.
416  * BBP_ID#_VALID: BBP register # id is valid or not.
417  */
418 #define RXCSR4				0x0094
419 #define RXCSR4_BBP_ID4			FIELD32(0x0000007f)
420 #define RXCSR4_BBP_ID4_VALID		FIELD32(0x00000080)
421 #define RXCSR4_BBP_ID5			FIELD32(0x00007f00)
422 #define RXCSR4_BBP_ID5_VALID		FIELD32(0x00008000)
423 
424 /*
425  * ARCSR0: Auto Responder PLCP config register 0.
426  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
427  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
428  */
429 #define ARCSR0				0x0098
430 #define ARCSR0_AR_BBP_DATA0		FIELD32(0x000000ff)
431 #define ARCSR0_AR_BBP_ID0		FIELD32(0x0000ff00)
432 #define ARCSR0_AR_BBP_DATA1		FIELD32(0x00ff0000)
433 #define ARCSR0_AR_BBP_ID1		FIELD32(0xff000000)
434 
435 /*
436  * ARCSR1: Auto Responder PLCP config register 1.
437  * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
438  * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
439  */
440 #define ARCSR1				0x009c
441 #define ARCSR1_AR_BBP_DATA2		FIELD32(0x000000ff)
442 #define ARCSR1_AR_BBP_ID2		FIELD32(0x0000ff00)
443 #define ARCSR1_AR_BBP_DATA3		FIELD32(0x00ff0000)
444 #define ARCSR1_AR_BBP_ID3		FIELD32(0xff000000)
445 
446 /*
447  * Miscellaneous Registers.
448  * Some values are set in TU, whereas 1 TU == 1024 us.
449  */
450 
451 /*
452  * PCICSR: PCI control register.
453  * BIG_ENDIAN: 1: big endian, 0: little endian.
454  * RX_TRESHOLD: Rx threshold in dw to start pci access
455  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
456  * TX_TRESHOLD: Tx threshold in dw to start pci access
457  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
458  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
459  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
460  */
461 #define PCICSR				0x008c
462 #define PCICSR_BIG_ENDIAN		FIELD32(0x00000001)
463 #define PCICSR_RX_TRESHOLD		FIELD32(0x00000006)
464 #define PCICSR_TX_TRESHOLD		FIELD32(0x00000018)
465 #define PCICSR_BURST_LENTH		FIELD32(0x00000060)
466 #define PCICSR_ENABLE_CLK		FIELD32(0x00000080)
467 
468 /*
469  * CNT0: FCS error count.
470  * FCS_ERROR: FCS error count, cleared when read.
471  */
472 #define CNT0				0x00a0
473 #define CNT0_FCS_ERROR			FIELD32(0x0000ffff)
474 
475 /*
476  * Statistic Register.
477  * CNT1: PLCP error count.
478  * CNT2: Long error count.
479  * CNT3: CCA false alarm count.
480  * CNT4: Rx FIFO overflow count.
481  * CNT5: Tx FIFO underrun count.
482  */
483 #define TIMECSR2			0x00a8
484 #define CNT1				0x00ac
485 #define CNT2				0x00b0
486 #define TIMECSR3			0x00b4
487 #define CNT3				0x00b8
488 #define CNT4				0x00bc
489 #define CNT5				0x00c0
490 
491 /*
492  * Baseband Control Register.
493  */
494 
495 /*
496  * PWRCSR0: Power mode configuration register.
497  */
498 #define PWRCSR0				0x00c4
499 
500 /*
501  * Power state transition time registers.
502  */
503 #define PSCSR0				0x00c8
504 #define PSCSR1				0x00cc
505 #define PSCSR2				0x00d0
506 #define PSCSR3				0x00d4
507 
508 /*
509  * PWRCSR1: Manual power control / status register.
510  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
511  * SET_STATE: Set state. Write 1 to trigger, self cleared.
512  * BBP_DESIRE_STATE: BBP desired state.
513  * RF_DESIRE_STATE: RF desired state.
514  * BBP_CURR_STATE: BBP current state.
515  * RF_CURR_STATE: RF current state.
516  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
517  */
518 #define PWRCSR1				0x00d8
519 #define PWRCSR1_SET_STATE		FIELD32(0x00000001)
520 #define PWRCSR1_BBP_DESIRE_STATE	FIELD32(0x00000006)
521 #define PWRCSR1_RF_DESIRE_STATE		FIELD32(0x00000018)
522 #define PWRCSR1_BBP_CURR_STATE		FIELD32(0x00000060)
523 #define PWRCSR1_RF_CURR_STATE		FIELD32(0x00000180)
524 #define PWRCSR1_PUT_TO_SLEEP		FIELD32(0x00000200)
525 
526 /*
527  * TIMECSR: Timer control register.
528  * US_COUNT: 1 us timer count in units of clock cycles.
529  * US_64_COUNT: 64 us timer count in units of 1 us timer.
530  * BEACON_EXPECT: Beacon expect window.
531  */
532 #define TIMECSR				0x00dc
533 #define TIMECSR_US_COUNT		FIELD32(0x000000ff)
534 #define TIMECSR_US_64_COUNT		FIELD32(0x0000ff00)
535 #define TIMECSR_BEACON_EXPECT		FIELD32(0x00070000)
536 
537 /*
538  * MACCSR0: MAC configuration register 0.
539  */
540 #define MACCSR0				0x00e0
541 
542 /*
543  * MACCSR1: MAC configuration register 1.
544  * KICK_RX: Kick one-shot rx in one-shot rx mode.
545  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
546  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
547  * AUTO_TXBBP: Auto tx logic access bbp control register.
548  * AUTO_RXBBP: Auto rx logic access bbp control register.
549  * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
550  * INTERSIL_IF: Intersil if calibration pin.
551  */
552 #define MACCSR1				0x00e4
553 #define MACCSR1_KICK_RX			FIELD32(0x00000001)
554 #define MACCSR1_ONESHOT_RXMODE		FIELD32(0x00000002)
555 #define MACCSR1_BBPRX_RESET_MODE	FIELD32(0x00000004)
556 #define MACCSR1_AUTO_TXBBP		FIELD32(0x00000008)
557 #define MACCSR1_AUTO_RXBBP		FIELD32(0x00000010)
558 #define MACCSR1_LOOPBACK		FIELD32(0x00000060)
559 #define MACCSR1_INTERSIL_IF		FIELD32(0x00000080)
560 
561 /*
562  * RALINKCSR: Ralink Rx auto-reset BBCR.
563  * AR_BBP_DATA#: Auto reset BBP register # data.
564  * AR_BBP_ID#: Auto reset BBP register # id.
565  */
566 #define RALINKCSR			0x00e8
567 #define RALINKCSR_AR_BBP_DATA0		FIELD32(0x000000ff)
568 #define RALINKCSR_AR_BBP_ID0		FIELD32(0x0000ff00)
569 #define RALINKCSR_AR_BBP_DATA1		FIELD32(0x00ff0000)
570 #define RALINKCSR_AR_BBP_ID1		FIELD32(0xff000000)
571 
572 /*
573  * BCNCSR: Beacon interval control register.
574  * CHANGE: Write one to change beacon interval.
575  * DELTATIME: The delta time value.
576  * NUM_BEACON: Number of beacon according to mode.
577  * MODE: Please refer to asic specs.
578  * PLUS: Plus or minus delta time value.
579  */
580 #define BCNCSR				0x00ec
581 #define BCNCSR_CHANGE			FIELD32(0x00000001)
582 #define BCNCSR_DELTATIME		FIELD32(0x0000001e)
583 #define BCNCSR_NUM_BEACON		FIELD32(0x00001fe0)
584 #define BCNCSR_MODE			FIELD32(0x00006000)
585 #define BCNCSR_PLUS			FIELD32(0x00008000)
586 
587 /*
588  * BBP / RF / IF Control Register.
589  */
590 
591 /*
592  * BBPCSR: BBP serial control register.
593  * VALUE: Register value to program into BBP.
594  * REGNUM: Selected BBP register.
595  * BUSY: 1: asic is busy execute BBP programming.
596  * WRITE_CONTROL: 1: write BBP, 0: read BBP.
597  */
598 #define BBPCSR				0x00f0
599 #define BBPCSR_VALUE			FIELD32(0x000000ff)
600 #define BBPCSR_REGNUM			FIELD32(0x00007f00)
601 #define BBPCSR_BUSY			FIELD32(0x00008000)
602 #define BBPCSR_WRITE_CONTROL		FIELD32(0x00010000)
603 
604 /*
605  * RFCSR: RF serial control register.
606  * VALUE: Register value + id to program into rf/if.
607  * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
608  * IF_SELECT: Chip to program: 0: rf, 1: if.
609  * PLL_LD: Rf pll_ld status.
610  * BUSY: 1: asic is busy execute rf programming.
611  */
612 #define RFCSR				0x00f4
613 #define RFCSR_VALUE			FIELD32(0x00ffffff)
614 #define RFCSR_NUMBER_OF_BITS		FIELD32(0x1f000000)
615 #define RFCSR_IF_SELECT			FIELD32(0x20000000)
616 #define RFCSR_PLL_LD			FIELD32(0x40000000)
617 #define RFCSR_BUSY			FIELD32(0x80000000)
618 
619 /*
620  * LEDCSR: LED control register.
621  * ON_PERIOD: On period, default 70ms.
622  * OFF_PERIOD: Off period, default 30ms.
623  * LINK: 0: linkoff, 1: linkup.
624  * ACTIVITY: 0: idle, 1: active.
625  */
626 #define LEDCSR				0x00f8
627 #define LEDCSR_ON_PERIOD		FIELD32(0x000000ff)
628 #define LEDCSR_OFF_PERIOD		FIELD32(0x0000ff00)
629 #define LEDCSR_LINK			FIELD32(0x00010000)
630 #define LEDCSR_ACTIVITY			FIELD32(0x00020000)
631 
632 /*
633  * ASIC pointer information.
634  * RXPTR: Current RX ring address.
635  * TXPTR: Current Tx ring address.
636  * PRIPTR: Current Priority ring address.
637  * ATIMPTR: Current ATIM ring address.
638  */
639 #define RXPTR				0x0100
640 #define TXPTR				0x0104
641 #define PRIPTR				0x0108
642 #define ATIMPTR				0x010c
643 
644 /*
645  * GPIO and others.
646  */
647 
648 /*
649  * GPIOCSR: GPIO control register.
650  *	GPIOCSR_VALx: Actual GPIO pin x value
651  *	GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
652  */
653 #define GPIOCSR				0x0120
654 #define GPIOCSR_VAL0			FIELD32(0x00000001)
655 #define GPIOCSR_VAL1			FIELD32(0x00000002)
656 #define GPIOCSR_VAL2			FIELD32(0x00000004)
657 #define GPIOCSR_VAL3			FIELD32(0x00000008)
658 #define GPIOCSR_VAL4			FIELD32(0x00000010)
659 #define GPIOCSR_VAL5			FIELD32(0x00000020)
660 #define GPIOCSR_VAL6			FIELD32(0x00000040)
661 #define GPIOCSR_VAL7			FIELD32(0x00000080)
662 #define GPIOCSR_DIR0			FIELD32(0x00000100)
663 #define GPIOCSR_DIR1			FIELD32(0x00000200)
664 #define GPIOCSR_DIR2			FIELD32(0x00000400)
665 #define GPIOCSR_DIR3			FIELD32(0x00000800)
666 #define GPIOCSR_DIR4			FIELD32(0x00001000)
667 #define GPIOCSR_DIR5			FIELD32(0x00002000)
668 #define GPIOCSR_DIR6			FIELD32(0x00004000)
669 #define GPIOCSR_DIR7			FIELD32(0x00008000)
670 
671 /*
672  * BBPPCSR: BBP Pin control register.
673  */
674 #define BBPPCSR				0x0124
675 
676 /*
677  * BCNCSR1: Tx BEACON offset time control register.
678  * PRELOAD: Beacon timer offset in units of usec.
679  */
680 #define BCNCSR1				0x0130
681 #define BCNCSR1_PRELOAD			FIELD32(0x0000ffff)
682 
683 /*
684  * MACCSR2: TX_PE to RX_PE turn-around time control register
685  * DELAY: RX_PE low width, in units of pci clock cycle.
686  */
687 #define MACCSR2				0x0134
688 #define MACCSR2_DELAY			FIELD32(0x000000ff)
689 
690 /*
691  * ARCSR2: 1 Mbps ACK/CTS PLCP.
692  */
693 #define ARCSR2				0x013c
694 #define ARCSR2_SIGNAL			FIELD32(0x000000ff)
695 #define ARCSR2_SERVICE			FIELD32(0x0000ff00)
696 #define ARCSR2_LENGTH_LOW		FIELD32(0x00ff0000)
697 #define ARCSR2_LENGTH			FIELD32(0xffff0000)
698 
699 /*
700  * ARCSR3: 2 Mbps ACK/CTS PLCP.
701  */
702 #define ARCSR3				0x0140
703 #define ARCSR3_SIGNAL			FIELD32(0x000000ff)
704 #define ARCSR3_SERVICE			FIELD32(0x0000ff00)
705 #define ARCSR3_LENGTH			FIELD32(0xffff0000)
706 
707 /*
708  * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
709  */
710 #define ARCSR4				0x0144
711 #define ARCSR4_SIGNAL			FIELD32(0x000000ff)
712 #define ARCSR4_SERVICE			FIELD32(0x0000ff00)
713 #define ARCSR4_LENGTH			FIELD32(0xffff0000)
714 
715 /*
716  * ARCSR5: 11 Mbps ACK/CTS PLCP.
717  */
718 #define ARCSR5				0x0148
719 #define ARCSR5_SIGNAL			FIELD32(0x000000ff)
720 #define ARCSR5_SERVICE			FIELD32(0x0000ff00)
721 #define ARCSR5_LENGTH			FIELD32(0xffff0000)
722 
723 /*
724  * BBP registers.
725  * The wordsize of the BBP is 8 bits.
726  */
727 
728 /*
729  * R1: TX antenna control
730  */
731 #define BBP_R1_TX_ANTENNA		FIELD8(0x03)
732 
733 /*
734  * R4: RX antenna control
735  */
736 #define BBP_R4_RX_ANTENNA		FIELD8(0x06)
737 
738 /*
739  * RF registers
740  */
741 
742 /*
743  * RF 1
744  */
745 #define RF1_TUNER			FIELD32(0x00020000)
746 
747 /*
748  * RF 3
749  */
750 #define RF3_TUNER			FIELD32(0x00000100)
751 #define RF3_TXPOWER			FIELD32(0x00003e00)
752 
753 /*
754  * EEPROM content.
755  * The wordsize of the EEPROM is 16 bits.
756  */
757 
758 /*
759  * HW MAC address.
760  */
761 #define EEPROM_MAC_ADDR_0		0x0002
762 #define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
763 #define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
764 #define EEPROM_MAC_ADDR1		0x0003
765 #define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
766 #define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
767 #define EEPROM_MAC_ADDR_2		0x0004
768 #define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
769 #define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)
770 
771 /*
772  * EEPROM antenna.
773  * ANTENNA_NUM: Number of antenna's.
774  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
775  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
776  * RF_TYPE: Rf_type of this adapter.
777  * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
778  * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
779  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
780  */
781 #define EEPROM_ANTENNA			0x0b
782 #define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
783 #define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
784 #define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
785 #define EEPROM_ANTENNA_RF_TYPE		FIELD16(0x0040)
786 #define EEPROM_ANTENNA_LED_MODE		FIELD16(0x0180)
787 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING	FIELD16(0x0200)
788 #define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)
789 
790 /*
791  * EEPROM BBP.
792  */
793 #define EEPROM_BBP_START		0x0c
794 #define EEPROM_BBP_SIZE			7
795 #define EEPROM_BBP_VALUE		FIELD16(0x00ff)
796 #define EEPROM_BBP_REG_ID		FIELD16(0xff00)
797 
798 /*
799  * EEPROM TXPOWER
800  */
801 #define EEPROM_TXPOWER_START		0x13
802 #define EEPROM_TXPOWER_SIZE		7
803 #define EEPROM_TXPOWER_1		FIELD16(0x00ff)
804 #define EEPROM_TXPOWER_2		FIELD16(0xff00)
805 
806 /*
807  * DMA descriptor defines.
808  */
809 #define TXD_DESC_SIZE			(8 * sizeof(__le32))
810 #define RXD_DESC_SIZE			(8 * sizeof(__le32))
811 
812 /*
813  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
814  */
815 
816 /*
817  * Word0
818  */
819 #define TXD_W0_OWNER_NIC		FIELD32(0x00000001)
820 #define TXD_W0_VALID			FIELD32(0x00000002)
821 #define TXD_W0_RESULT			FIELD32(0x0000001c)
822 #define TXD_W0_RETRY_COUNT		FIELD32(0x000000e0)
823 #define TXD_W0_MORE_FRAG		FIELD32(0x00000100)
824 #define TXD_W0_ACK			FIELD32(0x00000200)
825 #define TXD_W0_TIMESTAMP		FIELD32(0x00000400)
826 #define TXD_W0_RTS			FIELD32(0x00000800)
827 #define TXD_W0_IFS			FIELD32(0x00006000)
828 #define TXD_W0_RETRY_MODE		FIELD32(0x00008000)
829 #define TXD_W0_AGC			FIELD32(0x00ff0000)
830 #define TXD_W0_R2			FIELD32(0xff000000)
831 
832 /*
833  * Word1
834  */
835 #define TXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)
836 
837 /*
838  * Word2
839  */
840 #define TXD_W2_BUFFER_LENGTH		FIELD32(0x0000ffff)
841 #define TXD_W2_DATABYTE_COUNT		FIELD32(0xffff0000)
842 
843 /*
844  * Word3 & 4: PLCP information
845  * The PLCP values should be treated as if they were BBP values.
846  */
847 #define TXD_W3_PLCP_SIGNAL		FIELD32(0x000000ff)
848 #define TXD_W3_PLCP_SIGNAL_REGNUM	FIELD32(0x00007f00)
849 #define TXD_W3_PLCP_SIGNAL_BUSY		FIELD32(0x00008000)
850 #define TXD_W3_PLCP_SERVICE		FIELD32(0x00ff0000)
851 #define TXD_W3_PLCP_SERVICE_REGNUM	FIELD32(0x7f000000)
852 #define TXD_W3_PLCP_SERVICE_BUSY	FIELD32(0x80000000)
853 
854 #define TXD_W4_PLCP_LENGTH_LOW		FIELD32(0x000000ff)
855 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM	FIELD32(0x00007f00)
856 #define TXD_W3_PLCP_LENGTH_LOW_BUSY	FIELD32(0x00008000)
857 #define TXD_W4_PLCP_LENGTH_HIGH		FIELD32(0x00ff0000)
858 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM	FIELD32(0x7f000000)
859 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY	FIELD32(0x80000000)
860 
861 /*
862  * Word5
863  */
864 #define TXD_W5_BBCR4			FIELD32(0x0000ffff)
865 #define TXD_W5_AGC_REG			FIELD32(0x007f0000)
866 #define TXD_W5_AGC_REG_VALID		FIELD32(0x00800000)
867 #define TXD_W5_XXX_REG			FIELD32(0x7f000000)
868 #define TXD_W5_XXX_REG_VALID		FIELD32(0x80000000)
869 
870 /*
871  * Word6
872  */
873 #define TXD_W6_SK_BUFF			FIELD32(0xffffffff)
874 
875 /*
876  * Word7
877  */
878 #define TXD_W7_RESERVED			FIELD32(0xffffffff)
879 
880 /*
881  * RX descriptor format for RX Ring.
882  */
883 
884 /*
885  * Word0
886  */
887 #define RXD_W0_OWNER_NIC		FIELD32(0x00000001)
888 #define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000002)
889 #define RXD_W0_MULTICAST		FIELD32(0x00000004)
890 #define RXD_W0_BROADCAST		FIELD32(0x00000008)
891 #define RXD_W0_MY_BSS			FIELD32(0x00000010)
892 #define RXD_W0_CRC_ERROR		FIELD32(0x00000020)
893 #define RXD_W0_PHYSICAL_ERROR		FIELD32(0x00000080)
894 #define RXD_W0_DATABYTE_COUNT		FIELD32(0xffff0000)
895 
896 /*
897  * Word1
898  */
899 #define RXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)
900 
901 /*
902  * Word2
903  */
904 #define RXD_W2_BUFFER_LENGTH		FIELD32(0x0000ffff)
905 #define RXD_W2_BBR0			FIELD32(0x00ff0000)
906 #define RXD_W2_SIGNAL			FIELD32(0xff000000)
907 
908 /*
909  * Word3
910  */
911 #define RXD_W3_RSSI			FIELD32(0x000000ff)
912 #define RXD_W3_BBR3			FIELD32(0x0000ff00)
913 #define RXD_W3_BBR4			FIELD32(0x00ff0000)
914 #define RXD_W3_BBR5			FIELD32(0xff000000)
915 
916 /*
917  * Word4
918  */
919 #define RXD_W4_RX_END_TIME		FIELD32(0xffffffff)
920 
921 /*
922  * Word5 & 6 & 7: Reserved
923  */
924 #define RXD_W5_RESERVED			FIELD32(0xffffffff)
925 #define RXD_W6_RESERVED			FIELD32(0xffffffff)
926 #define RXD_W7_RESERVED			FIELD32(0xffffffff)
927 
928 /*
929  * Macros for converting txpower from EEPROM to mac80211 value
930  * and from mac80211 value to register value.
931  * NOTE: Logics in rt2400pci for txpower are reversed
932  * compared to the other rt2x00 drivers. A higher txpower
933  * value means that the txpower must be lowered. This is
934  * important when converting the value coming from the
935  * mac80211 stack to the rt2400 acceptable value.
936  */
937 #define MIN_TXPOWER	31
938 #define MAX_TXPOWER	62
939 #define DEFAULT_TXPOWER	39
940 
941 #define __CLAMP_TX(__txpower) \
942 	clamp_t(u8, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
943 
944 #define TXPOWER_FROM_DEV(__txpower) \
945 	((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
946 
947 #define TXPOWER_TO_DEV(__txpower) \
948 	(MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER))
949 
950 #endif /* RT2400PCI_H */
951