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/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_14nm.xml.h56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
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H A Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
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H A Ddsi_phy_7nm.xml.h56 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
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/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-usbphy.h10 #define USBPHY_CTRL 0x00000030
11 #define USBPHY_CTRL_SET 0x00000034
12 #define USBPHY_CTRL_CLR 0x00000038
13 #define USBPHY_CTRL_TOG 0x0000003C
14 #define USBPHY_PWD 0x00000000
15 #define USBPHY_TX 0x00000010
16 #define USBPHY_RX 0x00000020
17 #define USBPHY_DEBUG 0x00000050
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi35 #clock-cells = <0>;
44 #clock-cells = <0>;
53 #clock-cells = <0>;
64 i_clk_mgr: clock_manager@0xffd04000 {
67 reg = <0xffd04000 0x00000200>;
73 vco0-psrc = <0>; /* Field: vco0.psrc */
76 mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
77 mpuclk-src = <0>; /* Field: mpuclk.src */
78 nocclk-cnt = <0>; /* Field: nocclk.cnt */
79 nocclk-src = <0>; /* Field: nocclk.src */
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/openbmc/u-boot/board/micronas/vct/vcth/
H A Dreg_scc.h11 #define SCC0_BASE 0x00110000
12 #define SCC1_BASE 0x00110080
13 #define SCC2_BASE 0x00110100
14 #define SCC3_BASE 0x00110180
15 #define SCC4_BASE 0x00110200
16 #define SCC5_BASE 0x00110280
17 #define SCC6_BASE 0x00110300
18 #define SCC7_BASE 0x00110380
19 #define SCC8_BASE 0x00110400
20 #define SCC9_BASE 0x00110480
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/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-regs.h13 #define UMC_CPURST 0x00000700
14 #define UMC_IDSRST 0x0000070C
15 #define UMC_IXMRST 0x00000714
16 #define UMC_HDMRST 0x00000718
17 #define UMC_MDMRST 0x0000071C
18 #define UMC_HDDRST 0x00000720
19 #define UMC_MDDRST 0x00000724
20 #define UMC_SIORST 0x00000728
21 #define UMC_GIORST 0x0000072C
22 #define UMC_HD2RST 0x00000734
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dramcfg.c32 return (nvkm_rd32(subdev->device, 0x101000) & 0x0000003c) >> 2; in nvbios_ramcfg_strap()
44 return nvbios_rd08(bios, bit_M.offset + 0); in nvbios_ramcfg_count()
47 return 0x00; in nvbios_ramcfg_count()
55 u32 xlat = 0x00000000; in nvbios_ramcfg_index()
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
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/openbmc/linux/tools/include/uapi/linux/
H A Dethtool.h21 #define ETHTOOL_GCHANNELS 0x0000003c /* Get no of channels */
102 #define ETHTOOL_GDRVINFO 0x00000003
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_int_process_v11.c40 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
49 * - context_id0[24:0]
51 * Auto - only context_id0[8:0] is used, which reports various interrupts
52 * generated by SQG. The rest is 0.
53 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
54 * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
57 * S_SENDMSG and Errors. These are 0 for Auto.
61 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
67 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv05.c38 { 0x24, 0x00 }, in nv05_devinit_meminit()
39 { 0x28, 0x00 }, in nv05_devinit_meminit()
40 { 0x24, 0x01 }, in nv05_devinit_meminit()
41 { 0x1f, 0x00 }, in nv05_devinit_meminit()
42 { 0x0f, 0x00 }, in nv05_devinit_meminit()
43 { 0x17, 0x00 }, in nv05_devinit_meminit()
44 { 0x06, 0x00 }, in nv05_devinit_meminit()
45 { 0x00, 0x00 } in nv05_devinit_meminit()
51 u32 patt = 0xdeadbeef; in nv05_devinit_meminit()
63 strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; in nv05_devinit_meminit()
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/openbmc/qemu/fsdev/
H A Dfile-op-9p.h48 #define V9FS_IMMEDIATE_WRITEOUT 0x00000001
49 #define V9FS_PATHNAME_FSCONTEXT 0x00000002
53 #define V9FS_SM_PASSTHROUGH 0x00000004
57 #define V9FS_SM_MAPPED 0x00000008
62 #define V9FS_SM_NONE 0x00000010
66 #define V9FS_SM_MAPPED_FILE 0x00000020
67 #define V9FS_RDONLY 0x00000040
68 #define V9FS_PROXY_SOCK_FD 0x00000080
69 #define V9FS_PROXY_SOCK_NAME 0x00000100
73 #define V9FS_REMAP_INODES 0x00000200
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/openbmc/u-boot/board/armltd/integrator/
H A Dpci_v3.h23 #define V3_PCI_VENDOR 0x00000000
24 #define V3_PCI_DEVICE 0x00000002
25 #define V3_PCI_CMD 0x00000004
26 #define V3_PCI_STAT 0x00000006
27 #define V3_PCI_CC_REV 0x00000008
28 #define V3_PCI_HDR_CFG 0x0000000C
29 #define V3_PCI_IO_BASE 0x00000010
30 #define V3_PCI_BASE0 0x00000014
31 #define V3_PCI_BASE1 0x00000018
32 #define V3_PCI_SUB_VENDOR 0x0000002C
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/openbmc/linux/include/linux/
H A Datmel-ssc.h33 #define SSC_CR 0x00000000
37 #define SSC_CR_RXEN_OFFSET 0
46 #define SSC_CMR 0x00000004
48 #define SSC_CMR_DIV_OFFSET 0
51 #define SSC_RCMR 0x00000010
59 #define SSC_RCMR_CKS_OFFSET 0
70 #define SSC_RFMR 0x00000014
72 #define SSC_RFMR_DATLEN_OFFSET 0
93 #define SSC_TCMR 0x00000018
101 #define SSC_TCMR_CKS_OFFSET 0
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
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/openbmc/linux/net/core/
H A Dptp_classifier.c16 * jneq #0x800, test_ipv6 ; ETH_P_IP ?
20 * jset #0x1fff, drop_ipv4 ; don't allow fragments
21 * ldxb 4*([14]&0xf) ; load IP header len
25 * and #0xf ; mask PTP_CLASS_VMASK
26 * or #0x10 ; PTP_CLASS_IPV4
28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE
32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ?
38 * and #0xf ; mask PTP_CLASS_VMASK
39 * or #0x20 ; PTP_CLASS_IPV6
41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE
[all …]
/openbmc/linux/drivers/net/ethernet/toshiba/
H A Dspider_net.h56 #define SPIDER_NET_GHIINT0STS 0x00000000
57 #define SPIDER_NET_GHIINT1STS 0x00000004
58 #define SPIDER_NET_GHIINT2STS 0x00000008
59 #define SPIDER_NET_GHIINT0MSK 0x00000010
60 #define SPIDER_NET_GHIINT1MSK 0x00000014
61 #define SPIDER_NET_GHIINT2MSK 0x00000018
63 #define SPIDER_NET_GRESUMINTNUM 0x00000020
64 #define SPIDER_NET_GREINTNUM 0x00000024
66 #define SPIDER_NET_GFFRMNUM 0x00000028
67 #define SPIDER_NET_GFAFRMNUM 0x0000002c
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/openbmc/linux/drivers/dma/
H A Dfsl_raid.h47 #define FSL_RE_GFM_POLY 0x1d000000
50 #define FSL_RE_CFG1_CBSI 0x08000000
51 #define FSL_RE_CFG1_CBS0 0x00080000
56 #define FSL_RE_PQ_OPCODE 0x1B
57 #define FSL_RE_XOR_OPCODE 0x1A
58 #define FSL_RE_MOVE_OPCODE 0x8
60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
61 #define FSL_RE_CACHEABLE_IO 0x0
62 #define FSL_RE_BUFFER_OUTPUT 0x0
63 #define FSL_RE_INTR_ON_ERROR 0x1
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dbase.c74 const u8 ramcfg = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2; in nvkm_fb_bios_memtype()
109 u32 tags = 0; in nvkm_fb_oneinit()
134 return nvkm_mm_init(&fb->tags.mm, 0, 0, tags, 1); in nvkm_fb_oneinit()
144 return 0; in nvkm_fb_mem_unlock()
152 return 0; in nvkm_fb_mem_unlock()
159 return 0; in nvkm_fb_mem_unlock()
174 return 0; in nvkm_fb_mem_unlock()
186 return 0; in nvkm_fb_vidmem_size()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
221 return 0; in nvkm_fb_init()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c36 for (i = 0; i < submit->nr_cmds; i++) { in a3xx_submit()
67 OUT_RING(ring, 0x00000000); in a3xx_submit()
75 #if 0 in a3xx_submit()
79 OUT_RING(ring, 0x00000000); in a3xx_submit()
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
90 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
91 OUT_RING(ring, 0x00000000); in a3xx_me_init()
92 OUT_RING(ring, 0x00000000); in a3xx_me_init()
93 OUT_RING(ring, 0x00000000); in a3xx_me_init()
94 OUT_RING(ring, 0x00000080); in a3xx_me_init()
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/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
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