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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/openbmc/linux/arch/x86/kernel/cpu/
H A Dscattered.c27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
29 { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
30 { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
31 { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 },
32 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
33 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
34 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
35 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
36 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/openbmc/linux/net/core/
H A Dptp_classifier.c16 * jneq #0x800, test_ipv6 ; ETH_P_IP ?
20 * jset #0x1fff, drop_ipv4 ; don't allow fragments
21 * ldxb 4*([14]&0xf) ; load IP header len
25 * and #0xf ; mask PTP_CLASS_VMASK
26 * or #0x10 ; PTP_CLASS_IPV4
28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE
32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ?
38 * and #0xf ; mask PTP_CLASS_VMASK
39 * or #0x20 ; PTP_CLASS_IPV6
41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/openbmc/linux/drivers/staging/gdm724x/
H A Dhci_packet.h15 #define NIC_TYPE_NIC0 0x00000010
16 #define NIC_TYPE_NIC1 0x00000011
17 #define NIC_TYPE_NIC2 0x00000012
18 #define NIC_TYPE_NIC3 0x00000013
19 #define NIC_TYPE_ARP 0x00000100
20 #define NIC_TYPE_ICMPV6 0x00000200
21 #define NIC_TYPE_MASK 0x0000FFFF
22 #define NIC_TYPE_F_IPV4 0x00010000
23 #define NIC_TYPE_F_IPV6 0x00020000
24 #define NIC_TYPE_F_DHCP 0x00040000
[all …]
/openbmc/linux/sound/soc/qcom/qdsp6/
H A Dq6dsp-errno.h8 #define ADSP_EOK 0x00000000
10 #define ADSP_EFAILED 0x00000001
12 #define ADSP_EBADPARAM 0x00000002
14 #define ADSP_EUNSUPPORTED 0x00000003
16 #define ADSP_EVERSION 0x00000004
18 #define ADSP_EUNEXPECTED 0x00000005
20 #define ADSP_EPANIC 0x00000006
22 #define ADSP_ENORESOURCE 0x00000007
24 #define ADSP_EHANDLE 0x00000008
26 #define ADSP_EALREADY 0x00000009
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn315.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
H A Ddmub_dcn316.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
H A Ddmub_dcn314.c33 #define DCN_BASE__INST0_SEG0 0x00000012
34 #define DCN_BASE__INST0_SEG1 0x000000C0
35 #define DCN_BASE__INST0_SEG2 0x000034C0
36 #define DCN_BASE__INST0_SEG3 0x00009000
37 #define DCN_BASE__INST0_SEG4 0x02403C00
38 #define DCN_BASE__INST0_SEG5 0
66 return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16); in dmub_dcn314_is_psrsu_supported()
/openbmc/u-boot/include/
H A Dmb862xx.h14 #define PCI_VENDOR_ID_FUJITSU 0x10CF
15 #define PCI_DEVICE_ID_CORAL_P 0x2019
16 #define PCI_DEVICE_ID_CORAL_PA 0x201E
18 #define MB862XX_TYPE_LIME 0x1
20 #define GC_HOST_BASE 0x01fc0000
21 #define GC_DISP_BASE 0x01fd0000
22 #define GC_DRAW_BASE 0x01ff0000
25 #define GC_SRST 0x0000002c
26 #define GC_CCF 0x00000038
27 #define GC_CID 0x000000f0
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Drenoir_ip_offset.h39 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0 } },
[all …]
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Ddimgrey_cavefish_ip_offset.h39 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_sh_mask.h26 #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
27 #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000
28 #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
29 #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
30 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
31 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
32 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL
33 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002
34 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
35 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000
[all …]
/openbmc/linux/drivers/soc/atmel/
H A Dsoc.h36 #define AT91RM9200_CIDR_MATCH 0x09290780
38 #define AT91SAM9260_CIDR_MATCH 0x019803a0
39 #define AT91SAM9261_CIDR_MATCH 0x019703a0
40 #define AT91SAM9263_CIDR_MATCH 0x019607a0
41 #define AT91SAM9G20_CIDR_MATCH 0x019905a0
42 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
43 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0
44 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0
45 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0
46 #define SAM9X60_CIDR_MATCH 0x019b35a0
[all …]
/openbmc/u-boot/board/mpr2/
H A Dlowlevel_init.S56 mov #0, r0
71 FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
72 WTCNT_D: .word 0x5A00 /* start counting at zero */
73 WTCSR_D: .word 0xA507 /* divide by 4096 */
79 CS0BCR_D: .long 0x12490400
81 CS0WCR_D: .long 0x00000340
87 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
88 CS3BCR_D: .long 0x10004400
90 CS3WCR_D: .long 0x00000091
92 SDCR_D1: .long 0x00000012
[all …]
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c32 #define CPG_PLL1CR 0xE6150028
33 #define CPG_PLL3CR 0xE61500DC
50 if (cpu_type == 0x4A) { in blanche_init_sys()
51 writel(0x4D000000, CPG_PLL1CR); in blanche_init_sys()
52 writel(0x4F000000, CPG_PLL3CR); in blanche_init_sys()
56 writel(0xA5A5A500, &rwdt->rwtcsra); in blanche_init_sys()
57 writel(0xA5A5A500, &swdt->swtcsra); in blanche_init_sys()
63 { 0x0004, 0x0bffffff }, in blanche_init_pfc()
64 { 0x0008, 0x002fffff }, in blanche_init_pfc()
65 { 0x0014, 0x00000fff }, in blanche_init_pfc()
[all …]
/openbmc/linux/drivers/s390/scsi/
H A Dzfcp_fsf.h17 #define FSF_QTCB_CURRENT_VERSION 0x00000001
20 #define FSF_QTCB_FCP_CMND 0x00000001
21 #define FSF_QTCB_ABORT_FCP_CMND 0x00000002
22 #define FSF_QTCB_OPEN_PORT_WITH_DID 0x00000005
23 #define FSF_QTCB_OPEN_LUN 0x00000006
24 #define FSF_QTCB_CLOSE_LUN 0x00000007
25 #define FSF_QTCB_CLOSE_PORT 0x00000008
26 #define FSF_QTCB_CLOSE_PHYSICAL_PORT 0x00000009
27 #define FSF_QTCB_SEND_ELS 0x0000000B
28 #define FSF_QTCB_SEND_GENERIC 0x0000000C
[all …]

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