12decb194SH. Peter Anvin /*
23f79410cSMaxime Jayat * Routines to identify additional cpu features that are scattered in
32decb194SH. Peter Anvin * cpuid space.
42decb194SH. Peter Anvin */
52decb194SH. Peter Anvin #include <linux/cpu.h>
62decb194SH. Peter Anvin
7eb243d1dSIngo Molnar #include <asm/memtype.h>
8ad3bc25aSBorislav Petkov #include <asm/apic.h>
92decb194SH. Peter Anvin #include <asm/processor.h>
102decb194SH. Peter Anvin
11ad3bc25aSBorislav Petkov #include "cpu.h"
122decb194SH. Peter Anvin
132decb194SH. Peter Anvin struct cpuid_bit {
142decb194SH. Peter Anvin u16 feature;
152decb194SH. Peter Anvin u8 reg;
162decb194SH. Peter Anvin u8 bit;
172decb194SH. Peter Anvin u32 level;
182decb194SH. Peter Anvin u32 sub_leaf;
192decb194SH. Peter Anvin };
202decb194SH. Peter Anvin
219f72f855SSherry Hurwitz /*
229f72f855SSherry Hurwitz * Please keep the leaf sorted by cpuid_bit.level for faster search.
239f72f855SSherry Hurwitz * X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
249f72f855SSherry Hurwitz * levels are different and there is a separate entry for each.
259f72f855SSherry Hurwitz */
26148f9bb8SPaul Gortmaker static const struct cpuid_bit cpuid_bits[] = {
2747bdf337SHe Chen { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
2847bdf337SHe Chen { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
2900a2f23eSTony Luck { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
304ad3278dSPawan Gupta { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
31*c6e3d590SDaniel Sneddon { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 },
32acec0ce0SFenghua Yu { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
33acec0ce0SFenghua Yu { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
34acec0ce0SFenghua Yu { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
35acec0ce0SFenghua Yu { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
367ce7f35bSThomas Gleixner { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
377ce7f35bSThomas Gleixner { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
387ce7f35bSThomas Gleixner { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
39a511e793SFenghua Yu { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
40ab66a33bSVikas Shivappa { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
41e48cb1a3SFenghua Yu { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
42b8921dccSSean Christopherson { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
43b8921dccSSean Christopherson { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
4416a7fe37SKai Huang { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 },
4547f10a36SHe Chen { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
4647f10a36SHe Chen { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
4747f10a36SHe Chen { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
489f72f855SSherry Hurwitz { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
49f334f723SBabu Moger { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
5078335aacSBabu Moger { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
51d6d0c7f6SSandipan Das { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
52257449c6SSandipan Das { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
5355ed6c47SSandipan Das { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 },
542decb194SH. Peter Anvin { 0, 0, 0, 0, 0 }
552decb194SH. Peter Anvin };
562decb194SH. Peter Anvin
init_scattered_cpuid_features(struct cpuinfo_x86 * c)572decb194SH. Peter Anvin void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
582decb194SH. Peter Anvin {
592decb194SH. Peter Anvin u32 max_level;
602decb194SH. Peter Anvin u32 regs[4];
612decb194SH. Peter Anvin const struct cpuid_bit *cb;
622decb194SH. Peter Anvin
632decb194SH. Peter Anvin for (cb = cpuid_bits; cb->feature; cb++) {
642decb194SH. Peter Anvin
652decb194SH. Peter Anvin /* Verify that the level is valid */
662decb194SH. Peter Anvin max_level = cpuid_eax(cb->level & 0xffff0000);
672decb194SH. Peter Anvin if (max_level < cb->level ||
682decb194SH. Peter Anvin max_level > (cb->level | 0xffff))
692decb194SH. Peter Anvin continue;
702decb194SH. Peter Anvin
7147f10a36SHe Chen cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
7247f10a36SHe Chen ®s[CPUID_EBX], ®s[CPUID_ECX],
7347f10a36SHe Chen ®s[CPUID_EDX]);
742decb194SH. Peter Anvin
752decb194SH. Peter Anvin if (regs[cb->reg] & (1 << cb->bit))
762decb194SH. Peter Anvin set_cpu_cap(c, cb->feature);
772decb194SH. Peter Anvin }
782decb194SH. Peter Anvin }
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