1de2bdb3dSTom St Denis /* 2de2bdb3dSTom St Denis * 3de2bdb3dSTom St Denis * Copyright (C) 2016 Advanced Micro Devices, Inc. 4de2bdb3dSTom St Denis * 5de2bdb3dSTom St Denis * Permission is hereby granted, free of charge, to any person obtaining a 6de2bdb3dSTom St Denis * copy of this software and associated documentation files (the "Software"), 7de2bdb3dSTom St Denis * to deal in the Software without restriction, including without limitation 8de2bdb3dSTom St Denis * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9de2bdb3dSTom St Denis * and/or sell copies of the Software, and to permit persons to whom the 10de2bdb3dSTom St Denis * Software is furnished to do so, subject to the following conditions: 11de2bdb3dSTom St Denis * 12de2bdb3dSTom St Denis * The above copyright notice and this permission notice shall be included 13de2bdb3dSTom St Denis * in all copies or substantial portions of the Software. 14de2bdb3dSTom St Denis * 15de2bdb3dSTom St Denis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16de2bdb3dSTom St Denis * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17de2bdb3dSTom St Denis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18de2bdb3dSTom St Denis * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19de2bdb3dSTom St Denis * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20de2bdb3dSTom St Denis * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21de2bdb3dSTom St Denis */ 22de2bdb3dSTom St Denis 23de2bdb3dSTom St Denis #ifndef VCE_1_0_SH_MASK_H 24de2bdb3dSTom St Denis #define VCE_1_0_SH_MASK_H 25de2bdb3dSTom St Denis 26de2bdb3dSTom St Denis #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L 27de2bdb3dSTom St Denis #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000 28de2bdb3dSTom St Denis #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 29de2bdb3dSTom St Denis #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 30de2bdb3dSTom St Denis #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 31de2bdb3dSTom St Denis #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 32de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL 33de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002 34de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L 35de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000 36de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L 37de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000000 38de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003ffcL 39de2bdb3dSTom St Denis #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x00000002 40de2bdb3dSTom St Denis #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffffL 41de2bdb3dSTom St Denis #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x00000000 42de2bdb3dSTom St Denis #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffffL 43de2bdb3dSTom St Denis #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x00000000 44de2bdb3dSTom St Denis #define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffffL 45de2bdb3dSTom St Denis #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 46de2bdb3dSTom St Denis #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0L 47de2bdb3dSTom St Denis #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x00000006 48de2bdb3dSTom St Denis #define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0L 49de2bdb3dSTom St Denis #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x00000006 50de2bdb3dSTom St Denis #define VCE_RB_RPTR2__RB_RPTR_MASK 0x007ffff0L 51de2bdb3dSTom St Denis #define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x00000004 52de2bdb3dSTom St Denis #define VCE_RB_RPTR__RB_RPTR_MASK 0x007ffff0L 53de2bdb3dSTom St Denis #define VCE_RB_RPTR__RB_RPTR__SHIFT 0x00000004 54de2bdb3dSTom St Denis #define VCE_RB_SIZE2__RB_SIZE_MASK 0x007ffff0L 55de2bdb3dSTom St Denis #define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x00000004 56de2bdb3dSTom St Denis #define VCE_RB_SIZE__RB_SIZE_MASK 0x007ffff0L 57de2bdb3dSTom St Denis #define VCE_RB_SIZE__RB_SIZE__SHIFT 0x00000004 58de2bdb3dSTom St Denis #define VCE_RB_WPTR2__RB_WPTR_MASK 0x007ffff0L 59de2bdb3dSTom St Denis #define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x00000004 60de2bdb3dSTom St Denis #define VCE_RB_WPTR__RB_WPTR_MASK 0x007ffff0L 61de2bdb3dSTom St Denis #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004 62de2bdb3dSTom St Denis #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L 63de2bdb3dSTom St Denis #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000 64de2bdb3dSTom St Denis #define VCE_STATUS__JOB_BUSY_MASK 0x00000001L 65de2bdb3dSTom St Denis #define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000 66de2bdb3dSTom St Denis #define VCE_STATUS__UENC_BUSY_MASK 0x00000100L 67de2bdb3dSTom St Denis #define VCE_STATUS__UENC_BUSY__SHIFT 0x00000008 68de2bdb3dSTom St Denis #define VCE_STATUS__VCPU_REPORT_MASK 0x000000feL 69de2bdb3dSTom St Denis #define VCE_STATUS__VCPU_REPORT__SHIFT 0x00000001 70de2bdb3dSTom St Denis #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L 71de2bdb3dSTom St Denis #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x00000003 72de2bdb3dSTom St Denis #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L 73de2bdb3dSTom St Denis #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x00000003 74de2bdb3dSTom St Denis #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L 75de2bdb3dSTom St Denis #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x00000003 76de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x00000002L 77de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x00000001 78de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x00000004L 79de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x00000002 80de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x00000001L 81de2bdb3dSTom St Denis #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x00000000 82de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0fffffffL 83de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x00000000 84de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0fffffffL 85de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x00000000 86de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0fffffffL 87de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x00000000 88de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00ffffffL 89de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x00000000 90de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00ffffffL 91de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x00000000 92de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00ffffffL 93de2bdb3dSTom St Denis #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x00000000 94de2bdb3dSTom St Denis #define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L 95de2bdb3dSTom St Denis #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000 96de2bdb3dSTom St Denis #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L 97de2bdb3dSTom St Denis #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012 98de2bdb3dSTom St Denis 99de2bdb3dSTom St Denis #endif 100