Lines Matching +full:0 +full:x00000012
56 mov #0, r0
71 FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
72 WTCNT_D: .word 0x5A00 /* start counting at zero */
73 WTCSR_D: .word 0xA507 /* divide by 4096 */
79 CS0BCR_D: .long 0x12490400
81 CS0WCR_D: .long 0x00000340
87 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
88 CS3BCR_D: .long 0x10004400
90 CS3WCR_D: .long 0x00000091
92 SDCR_D1: .long 0x00000012
93 SDCR_D2: .long 0x00000812 /* refresh */
94 RTCSR_D: .long 0xA55A0008 /* 1/4, once */
95 RTCNT_D: .long 0xA55A005D /* count 93 */
96 RTCOR_D: .long 0xa55a005d /* count 93 */
98 SDMR3_D: .long 0x440
104 FRQCR_A: .long 0xA415FF80
105 WTCNT_A: .long 0xA415FF84
106 WTCSR_A: .long 0xA415FF86
108 #define BSC_BASE 0xA4FD0000
109 CS0BCR_A: .long BSC_BASE + 0x04
110 CS3BCR_A: .long BSC_BASE + 0x0C
111 CS0WCR_A: .long BSC_BASE + 0x24
112 CS3WCR_A: .long BSC_BASE + 0x2C
113 SDCR_A: .long BSC_BASE + 0x44
114 RTCSR_A: .long BSC_BASE + 0x48
115 RTCNT_A: .long BSC_BASE + 0x4C
116 RTCOR_A: .long BSC_BASE + 0x50
117 SDMR3_A: .long BSC_BASE + 0x5000