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/openbmc/linux/drivers/clk/mediatek/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
[all …]
/openbmc/linux/drivers/clk/imx/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
H A Dclk-imx27.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
13 #include "clk.h"
48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
[all …]
H A Dclk-vf610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
10 #include <dt-bindings/clock/vf610-clock.h>
12 #include "clk.h"
113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
[all …]
H A Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
80 * @clk: clk type of this resource
[all …]
H A Dclk-imx5.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/imx5-clock.h>
19 #include "clk.h"
65 /* Low-power Audio Playback Mode clock */
128 static struct clk *clk[IMX5_CLK_END]; variable
133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
[all …]
/openbmc/linux/drivers/sh/clk/
H A Dcpg.c5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
[all …]
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstih410-clock.dtsi8 #include <dt-bindings/clock/stih410-clks.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
30 arm_periph_clk: clk-m-a9-periphs {
[all …]
H A Dstih407-clock.dtsi8 #include <dt-bindings/clock/stih407-clks.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
18 clk_sysin: clk-sysin {
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
27 arm_periph_clk: clk-m-a9-periphs {
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
[all …]
/openbmc/linux/arch/mips/lantiq/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
23 #include "clk.h"
27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
[all …]
/openbmc/qemu/hw/core/
H A Dclock.c4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
21 #define CLOCK_PATH(_clk) (_clk->canonical_path)
23 void clock_setup_canonical_path(Clock *clk) in clock_setup_canonical_path() argument
25 g_free(clk->canonical_path); in clock_setup_canonical_path()
26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
39 clock_setup_canonical_path(clk); in clock_new()
41 return clk; in clock_new()
[all …]
/openbmc/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
[all …]
/openbmc/linux/drivers/clk/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk_test.o
6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
8 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
10 obj-$(CONFIG_CLK_GATE_KUNIT_TEST) += clk-gate_test.o
11 obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
[all …]
/openbmc/linux/kernel/time/
H A Dposix-clock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/posix-clock.h>
15 #include "posix-timers.h"
22 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
24 down_read(&clk->rwsem); in get_posix_clock()
26 if (!clk->zombie) in get_posix_clock()
27 return clk; in get_posix_clock()
29 up_read(&clk->rwsem); in get_posix_clock()
34 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
36 up_read(&clk->rwsem); in put_posix_clock()
[all …]
/openbmc/linux/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
5 * clk.c -- general ColdFire CPU kernel clk handling
16 #include <linux/clk.h>
31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clk.h>
491 *mem_type = params->mem_type; in clock_get_mem_selection()
492 *frequency_mhz = params->frequency_mhz; in clock_get_mem_selection()
493 *arm_freq = params->arm_freq_mhz; in clock_get_mem_selection()
494 *mem_manuf = params->mem_manuf; in clock_get_mem_selection()
511 if (arm_ratio->arm_freq_mhz == arm_freq) in get_arm_ratios()
534 if (mem->mem_type == mem_type && in clock_get_mem_timings()
535 mem->frequency_mhz == frequency_mhz && in clock_get_mem_timings()
536 mem->mem_manuf == mem_manuf) in clock_get_mem_timings()
[all …]
/openbmc/u-boot/drivers/clk/tegra/
H A Dtegra-car-clk.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
10 #include <asm/arch-tegra/clk_rst.h>
12 static int tegra_car_clk_request(struct clk *clk) in tegra_car_clk_request() argument
14 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_request()
15 clk->id); in tegra_car_clk_request()
25 if (clk->id >= PERIPH_ID_COUNT) in tegra_car_clk_request()
26 return -EINVAL; in tegra_car_clk_request()
31 static int tegra_car_clk_free(struct clk *clk) in tegra_car_clk_free() argument
33 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_free()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <clk.h>
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
19 return (const struct clk_ops *)dev->driver->ops; in clk_dev_ops()
25 struct phandle_1_arg *cells, struct clk *clk) in clk_get_by_index_platdata() argument
30 return -ENOSYS; in clk_get_by_index_platdata()
31 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); in clk_get_by_index_platdata()
34 clk->id = cells[0].arg[0]; in clk_get_by_index_platdata()
39 static int clk_of_xlate_default(struct clk *clk, in clk_of_xlate_default() argument
[all …]
H A Dclk-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
8 * Loosely based on Linux kernel sci-clk.c...
14 #include <clk-uclass.h>
18 * struct ti_sci_clk_data - clock controller information structure
32 return -ENOMEM; in ti_sci_clk_probe()
35 data->sci = ti_sci_get_handle(dev); in ti_sci_clk_probe()
36 if (IS_ERR(data->sci)) in ti_sci_clk_probe()
37 return PTR_ERR(data->sci); in ti_sci_clk_probe()
42 static int ti_sci_clk_of_xlate(struct clk *clk, in ti_sci_clk_of_xlate() argument
[all …]
/openbmc/qemu/hw/misc/
H A Domap_clk.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
27 struct clk { struct
30 struct clk *parent; argument
31 struct clk *child1; argument
32 struct clk *sibling; argument
42 int enabled; /* Is enabled, regardless of its input clk */ argument
50 static struct clk xtal_osc12m = { argument
56 static struct clk xtal_osc32k = {
62 static struct clk ck_ref = {
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dbase.c41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
76 * C-States
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
86 while (domain && domain->name != nv_clk_src_max) { in nvkm_cstate_valid()
87 if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) { in nvkm_cstate_valid()
88 u32 freq = cstate->domain[domain->name]; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
[all …]
/openbmc/linux/drivers/clk/ux500/
H A Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-half-divider.o
12 clk-rockchip-y += clk-inverter.o
13 clk-rockchip-y += clk-mmc-phase.o
14 clk-rockchip-y += clk-muxgrf.o
15 clk-rockchip-y += clk-ddr.o
[all …]

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