Lines Matching +full:- +full:clk
8 #include <dt-bindings/clock/stih410-clks.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
34 clock-div = <2>;
35 clock-mult = <1>;
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-clkgen-plla9";
51 clock-output-names = "clockgen-a9-pll-odf";
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
78 clock-output-names = "clk-m-a9-ext2f-div2";
80 clock-div = <2>;
81 clock-mult = <1>;
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,clkgen-pll0";
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
109 clk_s_a0_flexgen: clk-s-a0-flexgen {
112 #clock-cells = <1>;
117 clock-output-names = "clk-ic-lmi0",
118 "clk-ic-lmi1";
119 clock-critical = <CLK_IC_LMI0>;
123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
124 #clock-cells = <1>;
125 compatible = "st,quadfs-pll";
130 clock-output-names = "clk-s-c0-fs0-ch0",
131 "clk-s-c0-fs0-ch1",
132 "clk-s-c0-fs0-ch2",
133 "clk-s-c0-fs0-ch3";
134 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
137 clk_s_c0: clockgen-c@09103000 {
138 compatible = "st,clkgen-c32";
141 clk_s_c0_pll0: clk-s-c0-pll0 {
142 #clock-cells = <1>;
143 compatible = "st,clkgen-pll0";
147 clock-output-names = "clk-s-c0-pll0-odf-0";
148 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
151 clk_s_c0_pll1: clk-s-c0-pll1 {
152 #clock-cells = <1>;
153 compatible = "st,clkgen-pll1";
157 clock-output-names = "clk-s-c0-pll1-odf-0";
160 clk_s_c0_flexgen: clk-s-c0-flexgen {
161 #clock-cells = <1>;
172 clock-output-names = "clk-icn-gpu",
173 "clk-fdma",
174 "clk-nand",
175 "clk-hva",
176 "clk-proc-stfe",
177 "clk-proc-tp",
178 "clk-rx-icn-dmu",
179 "clk-rx-icn-hva",
180 "clk-icn-cpu",
181 "clk-tx-icn-dmu",
182 "clk-mmc-0",
183 "clk-mmc-1",
184 "clk-jpegdec",
185 "clk-ext2fa9",
186 "clk-ic-bdisp-0",
187 "clk-ic-bdisp-1",
188 "clk-pp-dmu",
189 "clk-vid-dmu",
190 "clk-dss-lpc",
191 "clk-st231-aud-0",
192 "clk-st231-gp-1",
193 "clk-st231-dmu",
194 "clk-icn-lmi",
195 "clk-tx-icn-disp-1",
196 "clk-icn-sbc",
197 "clk-stfe-frc2",
198 "clk-eth-phy",
199 "clk-eth-ref-phyclk",
200 "clk-flash-promip",
201 "clk-main-disp",
202 "clk-aux-disp",
203 "clk-compo-dvp",
204 "clk-tx-icn-hades",
205 "clk-rx-icn-hades",
206 "clk-icn-reg-16",
207 "clk-pp-hades",
208 "clk-clust-hades",
209 "clk-hwpe-hades",
210 "clk-fc-hades";
211 clock-critical = <CLK_ICN_CPU>,
219 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
220 #clock-cells = <1>;
226 clock-output-names = "clk-s-d0-fs0-ch0",
227 "clk-s-d0-fs0-ch1",
228 "clk-s-d0-fs0-ch2",
229 "clk-s-d0-fs0-ch3";
232 clockgen-d0@09104000 {
233 compatible = "st,clkgen-c32";
236 clk_s_d0_flexgen: clk-s-d0-flexgen {
237 #clock-cells = <1>;
238 compatible = "st,flexgen-audio", "st,flexgen";
246 clock-output-names = "clk-pcm-0",
247 "clk-pcm-1",
248 "clk-pcm-2",
249 "clk-spdiff",
250 "clk-pcmr10-master",
251 "clk-usb2-phy";
255 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
256 #clock-cells = <1>;
262 clock-output-names = "clk-s-d2-fs0-ch0",
263 "clk-s-d2-fs0-ch1",
264 "clk-s-d2-fs0-ch2",
265 "clk-s-d2-fs0-ch3";
268 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
269 #clock-cells = <0>;
270 compatible = "fixed-clock";
271 clock-frequency = <0>;
274 clockgen-d2@x9106000 {
275 compatible = "st,clkgen-c32";
278 clk_s_d2_flexgen: clk-s-d2-flexgen {
279 #clock-cells = <1>;
280 compatible = "st,flexgen-video", "st,flexgen";
290 clock-output-names = "clk-pix-main-disp",
291 "clk-pix-pip",
292 "clk-pix-gdp1",
293 "clk-pix-gdp2",
294 "clk-pix-gdp3",
295 "clk-pix-gdp4",
296 "clk-pix-aux-disp",
297 "clk-denc",
298 "clk-pix-hddac",
299 "clk-hddac",
300 "clk-sddac",
301 "clk-pix-dvo",
302 "clk-dvo",
303 "clk-pix-hdmi",
304 "clk-tmds-hdmi",
305 "clk-ref-hdmiphy";
309 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
310 #clock-cells = <1>;
316 clock-output-names = "clk-s-d3-fs0-ch0",
317 "clk-s-d3-fs0-ch1",
318 "clk-s-d3-fs0-ch2",
319 "clk-s-d3-fs0-ch3";
322 clockgen-d3@9107000 {
323 compatible = "st,clkgen-c32";
326 clk_s_d3_flexgen: clk-s-d3-flexgen {
327 #clock-cells = <1>;
336 clock-output-names = "clk-stfe-frc1",
337 "clk-tsout-0",
338 "clk-tsout-1",
339 "clk-mchi",
340 "clk-vsens-compo",
341 "clk-frc1-remote",
342 "clk-lpc-0",
343 "clk-lpc-1";