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Searched defs:UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h649 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Duvd_4_0_sh_mask.h755 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000 macro
H A Duvd_4_2_sh_mask.h526 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 macro
H A Duvd_3_1_sh_mask.h522 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h560 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h558 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1169 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2679 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2675 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h32 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3737 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3983 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4018 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT … macro