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Searched defs:UVD_SEMA_CMD__MODE_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h616 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L macro
H A Duvd_4_2_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
H A Duvd_3_1_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
H A Duvd_5_0_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h299 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2958 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3159 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3290 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4046 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4290 #define UVD_SEMA_CMD__MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4333 #define UVD_SEMA_CMD__MODE_MASK … macro