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Searched defs:UVD_MPC_SET_MUXA1__VARA_7_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h614 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Duvd_4_0_sh_mask.h510 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L macro
H A Duvd_4_2_sh_mask.h495 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
H A Duvd_3_1_sh_mask.h491 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
H A Duvd_6_0_sh_mask.h529 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
H A Duvd_5_0_sh_mask.h527 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1121 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_2_5_sh_mask.h2862 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2627 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2854 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3935 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4185 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4228 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro