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Searched defs:UVD_MPC_SET_MUXA1__VARA_6__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h610 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Duvd_4_0_sh_mask.h509 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006 macro
H A Duvd_4_2_sh_mask.h494 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 macro
H A Duvd_3_1_sh_mask.h490 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 macro
H A Duvd_6_0_sh_mask.h528 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 macro
H A Duvd_5_0_sh_mask.h526 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1117 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2858 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2623 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2850 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3931 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4181 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4224 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT … macro