Home
last modified time | relevance | path

Searched defs:UVD_MPC_SET_MUXA1__VARA_6_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h613 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Duvd_4_0_sh_mask.h508 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L macro
H A Duvd_4_2_sh_mask.h493 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
H A Duvd_3_1_sh_mask.h489 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
H A Duvd_6_0_sh_mask.h527 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
H A Duvd_5_0_sh_mask.h525 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1120 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_2_5_sh_mask.h2861 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2626 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2853 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3934 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4184 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4227 #define UVD_MPC_SET_MUXA1__VARA_6_MASK … macro