Home
last modified time | relevance | path

Searched defs:UVD_MPC_SET_MUXA0__VARA_4__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h602 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Duvd_4_0_sh_mask.h505 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 macro
H A Duvd_4_2_sh_mask.h490 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_3_1_sh_mask.h486 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_6_0_sh_mask.h524 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_5_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1109 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2850 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2615 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2842 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3923 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4173 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4216 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro