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Searched defs:UVD_MPC_SET_MUXA0__VARA_0__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h598 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Duvd_4_0_sh_mask.h497 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000 macro
H A Duvd_4_2_sh_mask.h482 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
H A Duvd_3_1_sh_mask.h478 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h516 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h514 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1105 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2846 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2611 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2838 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3919 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4169 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4212 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro