1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include <linux/bitfield.h> 21 #include <linux/bitops.h> 22 #include "sdram_phy_ast2600.h" 23 24 /* in order to speed up DRAM init time, write pre-defined values to registers 25 * directly */ 26 #define AST2600_SDRAMMC_MANUAL_CLK 27 28 /* register offset */ 29 #define AST_SCU_FPGA_STATUS 0x004 30 #define AST_SCU_HANDSHAKE 0x100 31 #define AST_SCU_MPLL 0x220 32 #define AST_SCU_MPLL_EXT 0x224 33 #define AST_SCU_FPGA_PLL 0x400 34 #define AST_SCU_HW_STRAP 0x500 35 #define AST_SCU_EFUSE_DATA 0x594 36 37 38 /* bit-field of AST_SCU_HW_STRAP */ 39 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 40 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 41 42 /* bit-field of AST_SCU_EFUSE_DATA */ 43 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 44 45 /* bit-field of AST_SCU_HANDSHAKE */ 46 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 47 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 48 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 49 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 50 #define SCU_HANDSHAKE_MASK \ 51 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 52 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 53 54 /* bit-field of AST_SCU_MPLL */ 55 #define SCU_MPLL_RESET BIT(25) 56 #define SCU_MPLL_BYPASS BIT(24) 57 #define SCU_MPLL_TURN_OFF BIT(23) 58 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 59 60 #define SCU_MPLL_FREQ_400M 0x0008405F 61 #define SCU_MPLL_EXT_400M 0x0000002F 62 //#define SCU_MPLL_FREQ_400M 0x0038007F 63 //#define SCU_MPLL_EXT_400M 0x0000003F 64 #define SCU_MPLL_FREQ_333M 0x00488299 65 #define SCU_MPLL_EXT_333M 0x0000014C 66 #define SCU_MPLL_FREQ_200M 0x0078007F 67 #define SCU_MPLL_EXT_200M 0x0000003F 68 #define SCU_MPLL_FREQ_100M 0x0078003F 69 #define SCU_MPLL_EXT_100M 0x0000001F 70 /* MPLL configuration */ 71 #if defined(CONFIG_ASPEED_DDR4_1600) 72 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 73 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 74 #elif defined(CONFIG_ASPEED_DDR4_1333) 75 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 76 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 77 #elif defined(CONFIG_ASPEED_DDR4_800) 78 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 79 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 80 #elif defined(CONFIG_ASPEED_DDR4_400) 81 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 82 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 83 #else 84 #error "undefined DDR4 target rate\n" 85 #endif 86 87 /** 88 * MR01[26:24] - ODT configuration (DRAM side) 89 * b'001 : 60 ohm 90 * b'101 : 48 ohm 91 * b'011 : 40 ohm (default) 92 */ 93 #if defined(CONFIG_ASPEED_DDR4_DRAM_ODT60) 94 #define MR01_DRAM_ODT (0x1 << 24) 95 #elif defined(CONFIG_ASPEED_DDR4_DRAM_ODT48) 96 #define MR01_DRAM_ODT (0x5 << 24) 97 #else 98 #define MR01_DRAM_ODT (0x3 << 24) 99 #endif 100 101 /* AC timing and SDRAM mode registers */ 102 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 103 /* mode register settings for FPGA are fixed */ 104 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010100) 105 #define DDR4_MR23_MODE 0x00000000 106 #define DDR4_MR45_MODE 0x04C00000 107 #define DDR4_MR6_MODE 0x00000050 108 #define DDR4_TRFC_FPGA 0x17263434 109 #define DDR4_TRFI 0x5d 110 111 /* FPGA need for an additional initialization procedure: search read window */ 112 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 113 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 114 #define SEARCH_RDWIN_PTRN_0 0x12345678 115 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 116 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 117 #else 118 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 119 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010510) 120 #define DDR4_MR23_MODE 0x00000000 121 #define DDR4_MR45_MODE 0x04000000 122 #define DDR4_MR6_MODE 0x00000400 123 #define DDR4_TRFC_1600 0x467299f1 124 #define DDR4_TRFC_1333 0x3a5f80c9 125 #define DDR4_TRFC_800 0x23394c78 126 #define DDR4_TRFC_400 0x111c263c 127 /* 128 * tRFI calculation 129 * DDR4 spec. : 130 * tRFI = 7.8 us if temperature is Less/equal than 85 degree celsius 131 * tRFI = 3.9 us if temperature is greater than 85 degree celsius 132 * 133 * tRFI in MCR0C = floor(tRFI * 12.5M) - margin 134 * normal temp. -> floor(7.8 * 12.5) - 2 = 0x5f 135 * high temp. -> floor(3.9 * 12.5) - 1 = 0x2f 136 */ 137 #ifdef CONFIG_ASPEED_HI_TEMP_TRFI 138 #define DDR4_TRFI 0x2f /* High temperature tRFI */ 139 #else 140 #define DDR4_TRFI 0x5f /* Normal temperature tRFI */ 141 #endif /* end of "#ifdef CONFIG_ASPEED_HI_TEMP_TRFI" */ 142 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 143 defined(CONFIG_ASPEED_PALLADIUM)" */ 144 145 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 146 #define DDR4_TRFC DDR4_TRFC_FPGA 147 #else 148 /* real chip setting */ 149 #if defined(CONFIG_ASPEED_DDR4_1600) 150 #define DDR4_TRFC DDR4_TRFC_1600 151 #define DDR4_PHY_TRAIN_TRFC 0xc30 152 #elif defined(CONFIG_ASPEED_DDR4_1333) 153 #define DDR4_TRFC DDR4_TRFC_1333 154 #define DDR4_PHY_TRAIN_TRFC 0xa25 155 #elif defined(CONFIG_ASPEED_DDR4_800) 156 #define DDR4_TRFC DDR4_TRFC_800 157 #define DDR4_PHY_TRAIN_TRFC 0x618 158 #elif defined(CONFIG_ASPEED_DDR4_400) 159 #define DDR4_TRFC DDR4_TRFC_400 160 #define DDR4_PHY_TRAIN_TRFC 0x30c 161 #else 162 #error "undefined tRFC setting" 163 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 164 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 165 defined(CONFIG_ASPEED_PALLADIUM)" */ 166 167 /* supported SDRAM size */ 168 #define SDRAM_SIZE_1KB (1024U) 169 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 170 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 171 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 172 173 174 DECLARE_GLOBAL_DATA_PTR; 175 176 /* 177 * Bandwidth configuration parameters for different SDRAM requests. 178 * These are hardcoded settings taken from Aspeed SDK. 179 */ 180 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 181 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 182 0x00000140 }; 183 184 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 185 0x88888888 }; 186 #else 187 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 188 0x00001240 }; 189 190 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 191 0x44444444 }; 192 #endif 193 194 struct dram_info { 195 struct ram_info info; 196 struct clk ddr_clk; 197 struct ast2600_sdrammc_regs *regs; 198 void __iomem *scu; 199 struct ast2600_ddr_phy *phy; 200 void __iomem *phy_setting; 201 void __iomem *phy_status; 202 ulong clock_rate; 203 }; 204 205 static void ast2600_sdramphy_kick_training(struct dram_info *info) 206 { 207 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 208 struct ast2600_sdrammc_regs *regs = info->regs; 209 u32 volatile data; 210 211 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 212 udelay(5); 213 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 214 udelay(1000); 215 216 while (1) { 217 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 218 if (~data) { 219 break; 220 } 221 } 222 223 #if 0 224 while (1) { 225 data = readl(0x1e6e0400) & BIT(1); 226 if (data) { 227 break; 228 } 229 } 230 #endif 231 #endif 232 } 233 234 /** 235 * @brief load DDR-PHY configurations table to the PHY registers 236 * @param[in] p_tbl - pointer to the configuration table 237 * @param[in] info - pointer to the DRAM info struct 238 * 239 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 240 * system: one is in the SDRAM MC (memory controller) which is used in run 241 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 242 * training. 243 */ 244 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 245 { 246 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 247 u32 reg_base = (u32)info->phy_setting; 248 u32 addr = p_tbl[0]; 249 u32 data; 250 int i = 1; 251 252 writel(0, &info->regs->phy_ctrl[0]); 253 udelay(10); 254 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 255 256 /* load PHY configuration table into PHY-setting registers */ 257 while (1) { 258 if (addr < reg_base) { 259 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 260 break; 261 } 262 data = p_tbl[i++]; 263 264 if (data == DDR_PHY_TBL_END) { 265 break; 266 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 267 addr = p_tbl[i++]; 268 } else { 269 writel(data, addr); 270 addr += 4; 271 } 272 } 273 274 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 275 data |= DDR4_PHY_TRAIN_TRFC; 276 writel(data, info->phy_setting + 0x84); 277 #endif 278 } 279 280 static int ast2600_sdramphy_check_status(struct dram_info *info) 281 { 282 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 283 u32 value, tmp; 284 u32 reg_base = (u32)info->phy_status; 285 int need_retrain = 0; 286 287 debug("\nSDRAM PHY training report:\n"); 288 /* training status */ 289 value = readl(reg_base + 0x00); 290 debug("\nrO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 291 if (value & BIT(3)) 292 debug("\tinitial PVT calibration fail\n"); 293 294 if (value & BIT(5)) 295 debug("\truntime calibration fail\n"); 296 297 /* PU & PD */ 298 value = readl(reg_base + 0x30); 299 debug("\nrO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 300 debug(" PU = 0x%02lx\n", FIELD_GET(GENMASK(7, 0), value)); 301 debug(" PD = 0x%02lx\n", FIELD_GET(GENMASK(23, 16), value)); 302 303 /* read eye window */ 304 value = readl(reg_base + 0x68); 305 if (FIELD_GET(GENMASK(7, 0), value) == 0) 306 need_retrain = 1; 307 308 debug("\nrO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 309 debug(" rising edge of read data eye training pass window\n"); 310 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 311 debug(" B0:%d%%\n", tmp); 312 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 313 debug(" B1:%d%%\n", tmp); 314 315 value = readl(reg_base + 0xC8); 316 debug("\nrO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 317 debug(" falling edge of read data eye training pass window\n"); 318 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 319 debug(" B0:%d%%\n", tmp); 320 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 321 debug(" B1:%d%%\n", tmp); 322 323 /* write eye window */ 324 value = readl(reg_base + 0x7c); 325 if (FIELD_GET(GENMASK(7, 0), value) == 0) 326 need_retrain = 1; 327 328 debug("\nrO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 329 debug(" write data eye training pass window\n"); 330 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 331 debug(" B0:%d%%\n", tmp); 332 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 333 debug(" B1:%d%%\n", tmp); 334 335 /* read Vref (PHY side) training result */ 336 value = readl(reg_base + 0x88); 337 debug("\nrO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 338 debug(" Read VrefDQ training result\n"); 339 tmp = FIELD_GET(GENMASK(7, 0), value) * 10000 / 128; 340 debug(" B0:%d.%d%%\n", tmp / 100, tmp % 100); 341 tmp = FIELD_GET(GENMASK(15, 8), value) * 10000 / 128; 342 debug(" B1:%d.%d%%\n", tmp / 100, tmp % 100); 343 344 /* write Vref (DRAM side) training result */ 345 value = readl(reg_base + 0x90); 346 debug("\nrO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 347 tmp = readl(info->phy_setting + 0x60) & BIT(6); 348 if (tmp) { 349 value = 4500 + 65 * value; 350 debug(" Write Vref training result: %d.%d%% (range 2)\n", 351 value / 100, value % 100); 352 } else { 353 value = 6000 + 65 * value; 354 debug(" Write Vref training result: %d.%d%% (range 1)\n", 355 value / 100, value % 100); 356 } 357 358 /* gate train */ 359 value = readl(reg_base + 0x50); 360 debug("\nrO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 361 if ((FIELD_GET(GENMASK(15, 0), value) == 0) || 362 (FIELD_GET(GENMASK(31, 16), value) == 0)) 363 need_retrain = 1; 364 365 debug(" gate training pass window\n"); 366 debug(" module 0: 0x%04lx\n", FIELD_GET(GENMASK(15, 0), value)); 367 debug(" module 1: 0x%04lx\n", FIELD_GET(GENMASK(31, 16), value)); 368 369 return need_retrain; 370 #else 371 return 0; 372 #endif 373 } 374 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 375 #define MC_TEST_PATTERN_N 8 376 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 377 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 378 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 379 }; 380 381 #define TIMEOUT_DRAM 5000000 382 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 383 { 384 unsigned int data; 385 unsigned int timeout = 0; 386 struct ast2600_sdrammc_regs *regs = info->regs; 387 388 writel(0, ®s->ecc_test_ctrl); 389 if (mode == 0) 390 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 391 else 392 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 393 394 do { 395 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 396 397 if (data & BIT(13)) 398 return 0; 399 400 if (++timeout > TIMEOUT_DRAM) { 401 printf("Timeout!!\n"); 402 writel(0, ®s->ecc_test_ctrl); 403 404 return 0; 405 } 406 } while (!data); 407 408 writel(0, ®s->ecc_test_ctrl); 409 410 return 1; 411 } 412 413 int ast2600_sdrammc_cbr_test(struct dram_info *info) 414 { 415 struct ast2600_sdrammc_regs *regs = info->regs; 416 u32 i; 417 418 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 419 420 /* single */ 421 for (i = 0; i < 8; i++) { 422 if (!ast2600_sdrammc_dg_test(info, i, 0)) 423 return (0); 424 } 425 426 /* burst */ 427 for (i = 0; i < 8; i++) { 428 if (!ast2600_sdrammc_dg_test(info, i, i)) 429 return (0); 430 } 431 432 return(1); 433 } 434 435 static int ast2600_sdrammc_test(struct dram_info *info) 436 { 437 struct ast2600_sdrammc_regs *regs = info->regs; 438 439 u32 pass_cnt = 0; 440 u32 fail_cnt = 0; 441 u32 target_cnt = 2; 442 u32 test_cnt = 0; 443 u32 pattern; 444 u32 i = 0; 445 bool finish = false; 446 447 debug("sdram mc test:\n"); 448 while (finish == false) { 449 pattern = as2600_sdrammc_test_pattern[i++]; 450 i = i % MC_TEST_PATTERN_N; 451 debug(" pattern = %08x : ", pattern); 452 writel(pattern, ®s->test_init_val); 453 454 if (!ast2600_sdrammc_cbr_test(info)) { 455 debug("fail\n"); 456 fail_cnt++; 457 } else { 458 debug("pass\n"); 459 pass_cnt++; 460 } 461 462 if (++test_cnt == target_cnt) { 463 finish = true; 464 } 465 } 466 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 467 target_cnt); 468 return fail_cnt; 469 } 470 #endif 471 /** 472 * scu500[14:13] 473 * 2b'00: VGA memory size = 16MB 474 * 2b'01: VGA memory size = 16MB 475 * 2b'10: VGA memory size = 32MB 476 * 2b'11: VGA memory size = 64MB 477 * 478 * mcr04[3:2] 479 * 2b'00: VGA memory size = 8MB 480 * 2b'01: VGA memory size = 16MB 481 * 2b'10: VGA memory size = 32MB 482 * 2b'11: VGA memory size = 64MB 483 */ 484 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 485 { 486 u32 vga_hwconf; 487 size_t vga_mem_size_base = 8 * 1024 * 1024; 488 489 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 490 SCU_HWSTRAP_VGAMEM_MASK) >> 491 SCU_HWSTRAP_VGAMEM_SHIFT; 492 493 if (vga_hwconf == 0) { 494 vga_hwconf = 1; 495 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 496 info->scu + AST_SCU_HW_STRAP); 497 } 498 499 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 500 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 501 SDRAM_CONF_VGA_SIZE_MASK)); 502 503 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 504 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 505 return 0; 506 507 return vga_mem_size_base << vga_hwconf; 508 } 509 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 510 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 511 { 512 u32 data; 513 u32 scu_base = (u32)info->scu; 514 515 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 516 517 do { 518 data = readl(scu_base + AST_SCU_FPGA_STATUS); 519 } while (!(data & 0x100)); 520 521 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 522 } 523 524 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 525 { 526 u32 pll, pll_min, pll_max, dat1, offset; 527 u32 win = 0x03, gwin = 0, gwinsize = 0; 528 u32 phy_setting = (u32)info->phy_setting; 529 530 #ifdef CONFIG_ASPEED_PALLADIUM 531 writel(0xc, phy_setting + 0x0000); 532 return 1; 533 #endif 534 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 535 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 536 537 while (gwin == 0) { 538 while (!(win & 0x80)) { 539 debug("Window = 0x%X\n", win); 540 writel(win, phy_setting + 0x0000); 541 542 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 543 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 544 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 545 ast2600_sdrammc_fpga_set_pll(info); 546 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 547 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 548 } 549 550 pll_min = 0xfff; 551 pll_max = 0x0; 552 pll = 0; 553 while (pll_max > 0 || pll < 256) { 554 ast2600_sdrammc_fpga_set_pll(info); 555 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 556 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 557 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 558 if (pll_min > pll) 559 pll_min = pll; 560 561 if (pll_max < pll) 562 pll_max = pll; 563 564 debug("%3d_(%3d:%3d)\n", pll, pll_min, 565 pll_max); 566 } else if (pll_max > 0) { 567 pll_min = pll_max - pll_min; 568 if (gwinsize < pll_min) { 569 gwin = win; 570 gwinsize = pll_min; 571 } 572 break; 573 } 574 pll += 1; 575 } 576 577 if (gwin != 0 && pll_max == 0) 578 break; 579 580 win = win << 1; 581 } 582 if (gwin == 0) 583 win = 0x7; 584 } 585 debug("Set PLL Read Gating Window = %x\n", gwin); 586 writel(gwin, phy_setting + 0x0000); 587 588 debug("PLL Read Window training\n"); 589 pll_min = 0xfff; 590 pll_max = 0x0; 591 592 debug("Search Window Start\n"); 593 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 594 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 595 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 596 ast2600_sdrammc_fpga_set_pll(info); 597 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 598 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 599 } 600 601 debug("Search Window Margin\n"); 602 pll = 0; 603 while (pll_max > 0 || pll < 256) { 604 ast2600_sdrammc_fpga_set_pll(info); 605 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 606 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 607 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 608 if (pll_min > pll) 609 pll_min = pll; 610 611 if (pll_max < pll) 612 pll_max = pll; 613 614 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 615 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 616 break; 617 } else if (pll_max > 0) { 618 pll_min = 0xfff; 619 pll_max = 0x0; 620 } 621 pll += 1; 622 } 623 if (pll_min < pll_max) { 624 debug("PLL Read window = %d\n", (pll_max - pll_min)); 625 offset = (pll_max - pll_min) >> 1; 626 pll_min = 0xfff; 627 pll = 0; 628 while (pll < (pll_min + offset)) { 629 ast2600_sdrammc_fpga_set_pll(info); 630 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 631 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 632 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 633 if (pll_min > pll) { 634 pll_min = pll; 635 } 636 debug("%d\n", pll); 637 } else { 638 pll_min = 0xfff; 639 pll_max = 0x0; 640 } 641 pll += 1; 642 } 643 return (1); 644 } else { 645 debug("PLL Read window training fail\n"); 646 return 0; 647 } 648 } 649 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 650 defined(CONFIG_ASPEED_PALLADIUM)" */ 651 652 /* 653 * Find out RAM size and save it in dram_info 654 * 655 * The procedure is taken from Aspeed SDK 656 */ 657 static void ast2600_sdrammc_calc_size(struct dram_info *info) 658 { 659 /* The controller supports 256/512/1024/2048 MB ram */ 660 size_t ram_size = SDRAM_MIN_SIZE; 661 const int write_test_offset = 0x100000; 662 u32 test_pattern = 0xdeadbeef; 663 u32 cap_param = SDRAM_CONF_CAP_2048M; 664 u32 refresh_timing_param = DDR4_TRFC; 665 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 666 667 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 668 ram_size >>= 1) { 669 writel(test_pattern, write_addr_base + (ram_size >> 1)); 670 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 671 } 672 673 /* One last write to overwrite all wrapped values */ 674 writel(test_pattern, write_addr_base); 675 676 /* Reset the pattern and see which value was really written */ 677 test_pattern = 0xdeadbeef; 678 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 679 ram_size >>= 1) { 680 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 681 break; 682 683 --cap_param; 684 refresh_timing_param >>= 8; 685 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 686 } 687 688 clrsetbits_le32(&info->regs->ac_timing[1], 689 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 690 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 691 << SDRAM_AC_TRFC_SHIFT)); 692 693 info->info.base = CONFIG_SYS_SDRAM_BASE; 694 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 695 696 clrsetbits_le32( 697 &info->regs->config, SDRAM_CONF_CAP_MASK, 698 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 699 } 700 701 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 702 { 703 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 704 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 705 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 706 (0x1 << MCR34_ODT_EXT_SHIFT); 707 708 /* init SDRAM-PHY only on real chip */ 709 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 710 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 711 &info->regs->power_ctrl); 712 udelay(5); 713 ast2600_sdramphy_kick_training(info); 714 udelay(500); 715 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 716 717 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 718 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 719 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 720 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 721 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 722 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 723 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 724 &info->regs->mode_setting_control); 725 726 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 727 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT), 728 &info->regs->refresh_timing); 729 730 /* wait self-refresh idle */ 731 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 732 ; 733 734 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 735 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 736 SDRAM_REFRESH_ZQCS_EN | 737 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 738 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 739 &info->regs->refresh_timing); 740 #else 741 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 742 SDRAM_REFRESH_ZQCS_EN | 743 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 744 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 745 &info->regs->refresh_timing); 746 #endif 747 748 writel(power_ctrl, &info->regs->power_ctrl); 749 udelay(500); 750 751 #if defined(CONFIG_FPGA_ASPEED) 752 /* toggle Vref training */ 753 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 754 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 755 &info->regs->mode_setting_control); 756 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 757 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 758 &info->regs->mode_setting_control); 759 #endif 760 return 0; 761 } 762 763 static void ast2600_sdrammc_unlock(struct dram_info *info) 764 { 765 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 766 while (!readl(&info->regs->protection_key)) 767 ; 768 } 769 770 static void ast2600_sdrammc_lock(struct dram_info *info) 771 { 772 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 773 while (readl(&info->regs->protection_key)) 774 ; 775 } 776 777 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 778 { 779 int i; 780 781 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 782 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 783 /* [6:0] : Group 1 request queued number = 16 784 * [14:8] : Group 2 request queued number = 16 785 * [20:16] : R/W max-grant count for RQ output arbitration = 16 786 */ 787 writel(0x101010, ®s->arbitration_ctrl); 788 /* Request Queued Limitation for REQ8/9 USB1/2 */ 789 writel(0x0FFF3CEF, ®s->req_limit_mask); 790 791 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 792 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 793 794 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 795 796 /* FIXME: the sample code does NOT match the datasheet */ 797 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 798 799 writel(0, ®s->ecc_test_ctrl); 800 writel(0x80000001, ®s->test_addr); 801 writel(0, ®s->test_fail_dq_bit); 802 writel(0, ®s->test_init_val); 803 804 writel(0xFFFFFFFF, ®s->req_input_ctrl); 805 writel(0x300, ®s->req_high_pri_ctrl); 806 807 udelay(600); 808 809 #ifdef CONFIG_ASPEED_DDR4_DUALX8 810 writel(0xa037, ®s->config); 811 #else 812 writel(0xa017, ®s->config); 813 #endif 814 815 /* load controller setting */ 816 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 817 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 818 819 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 820 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 821 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 822 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 823 } 824 /* 825 * Update size info according to the ECC HW setting 826 * 827 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 828 * don't need to calculate the ECC size again but read from MCR04 and derive the 829 * size from its value. 830 */ 831 static void ast2600_sdrammc_update_size(struct dram_info *info) 832 { 833 struct ast2600_sdrammc_regs *regs = info->regs; 834 size_t hw_size; 835 size_t ram_size = SDRAM_MAX_SIZE; 836 u32 cap_param; 837 838 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 839 switch (cap_param) 840 { 841 case SDRAM_CONF_CAP_2048M: 842 ram_size = 2048 * SDRAM_SIZE_1MB; 843 break; 844 case SDRAM_CONF_CAP_1024M: 845 ram_size = 1024 * SDRAM_SIZE_1MB; 846 break; 847 case SDRAM_CONF_CAP_512M: 848 ram_size = 512 * SDRAM_SIZE_1MB; 849 break; 850 case SDRAM_CONF_CAP_256M: 851 ram_size = 256 * SDRAM_SIZE_1MB; 852 break; 853 } 854 855 info->info.base = CONFIG_SYS_SDRAM_BASE; 856 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 857 858 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 859 return; 860 861 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 862 hw_size += (1 << 20); 863 864 info->info.size = hw_size; 865 } 866 #ifdef CONFIG_ASPEED_ECC 867 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 868 { 869 struct ast2600_sdrammc_regs *regs = info->regs; 870 size_t conf_size; 871 u32 reg; 872 873 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 874 if (conf_size > info->info.size) { 875 printf("warning: ECC configured %dMB but actual size is %dMB\n", 876 CONFIG_ASPEED_ECC_SIZE, 877 info->info.size / SDRAM_SIZE_1MB); 878 conf_size = info->info.size; 879 } else if (conf_size == 0) { 880 conf_size = info->info.size; 881 } 882 883 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 884 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 885 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 886 writel(reg, ®s->config); 887 888 writel(0, ®s->test_init_val); 889 writel(0x80000001, ®s->test_addr); 890 writel(0x221, ®s->ecc_test_ctrl); 891 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 892 ; 893 writel(0, ®s->ecc_test_ctrl); 894 writel(BIT(31), ®s->intr_ctrl); 895 writel(0, ®s->intr_ctrl); 896 } 897 #endif 898 899 static int ast2600_sdrammc_probe(struct udevice *dev) 900 { 901 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 902 struct ast2600_sdrammc_regs *regs = priv->regs; 903 struct udevice *clk_dev; 904 int ret; 905 volatile uint32_t reg; 906 907 /* find SCU base address from clock device */ 908 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 909 &clk_dev); 910 if (ret) { 911 debug("clock device not defined\n"); 912 return ret; 913 } 914 915 priv->scu = devfdt_get_addr_ptr(clk_dev); 916 if (IS_ERR(priv->scu)) { 917 debug("%s(): can't get SCU\n", __func__); 918 return PTR_ERR(priv->scu); 919 } 920 921 reg = readl(priv->scu + AST_SCU_HANDSHAKE); 922 if (reg & SCU_SDRAM_INIT_READY_MASK) { 923 printf("already initialized, "); 924 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 925 ast2600_sdrammc_update_size(priv); 926 return 0; 927 } 928 929 #ifdef AST2600_SDRAMMC_MANUAL_CLK 930 reg = readl(priv->scu + AST_SCU_MPLL); 931 reg &= ~(BIT(24) | GENMASK(22, 0)); 932 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 933 writel(reg, priv->scu + AST_SCU_MPLL); 934 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 935 udelay(100); 936 reg &= ~(BIT(25) | BIT(23)); 937 writel(reg, priv->scu + AST_SCU_MPLL); 938 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 939 ; 940 #else 941 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 942 if (ret) { 943 debug("DDR:No CLK\n"); 944 return ret; 945 } 946 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 947 #endif 948 949 #if 0 950 /* FIXME: enable the following code if reset-driver is ready */ 951 struct reset_ctl reset_ctl; 952 ret = reset_get_by_index(dev, 0, &reset_ctl); 953 if (ret) { 954 debug("%s(): Failed to get reset signal\n", __func__); 955 return ret; 956 } 957 958 ret = reset_assert(&reset_ctl); 959 if (ret) { 960 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 961 return ret; 962 } 963 #endif 964 965 ast2600_sdrammc_unlock(priv); 966 ast2600_sdrammc_common_init(regs); 967 L_ast2600_sdramphy_train: 968 ast2600_sdrammc_init_ddr4(priv); 969 970 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 971 ast2600_sdrammc_search_read_window(priv); 972 #else 973 /* make sure DDR-PHY is ready before access */ 974 do { 975 reg = readl(priv->phy_status) & BIT(1); 976 } while (reg == 0); 977 #endif 978 979 ret = ast2600_sdramphy_check_status(priv); 980 if (ret) { 981 printf("DDR4 PHY training fail, retrain\n"); 982 goto L_ast2600_sdramphy_train; 983 } 984 985 ast2600_sdrammc_calc_size(priv); 986 987 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 988 ret = ast2600_sdrammc_test(priv); 989 if (ret) { 990 printf("%s: DDR4 init fail\n", __func__); 991 return -EINVAL; 992 } 993 #endif 994 995 #ifdef CONFIG_ASPEED_ECC 996 ast2600_sdrammc_ecc_enable(priv); 997 #endif 998 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 999 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 1000 ast2600_sdrammc_lock(priv); 1001 return 0; 1002 } 1003 1004 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 1005 { 1006 struct dram_info *priv = dev_get_priv(dev); 1007 1008 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 1009 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 1010 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 1011 1012 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 1013 "clock-frequency", 0); 1014 if (!priv->clock_rate) { 1015 debug("DDR Clock Rate not defined\n"); 1016 return -EINVAL; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 1023 { 1024 struct dram_info *priv = dev_get_priv(dev); 1025 1026 *info = priv->info; 1027 1028 return 0; 1029 } 1030 1031 static struct ram_ops ast2600_sdrammc_ops = { 1032 .get_info = ast2600_sdrammc_get_info, 1033 }; 1034 1035 static const struct udevice_id ast2600_sdrammc_ids[] = { 1036 { .compatible = "aspeed,ast2600-sdrammc" }, 1037 { } 1038 }; 1039 1040 U_BOOT_DRIVER(sdrammc_ast2600) = { 1041 .name = "aspeed_ast2600_sdrammc", 1042 .id = UCLASS_RAM, 1043 .of_match = ast2600_sdrammc_ids, 1044 .ops = &ast2600_sdrammc_ops, 1045 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1046 .probe = ast2600_sdrammc_probe, 1047 .priv_auto_alloc_size = sizeof(struct dram_info), 1048 }; 1049