1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 45 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 46 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 47 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 48 #define SCU_HANDSHAKE_MASK \ 49 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 50 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 51 52 /* bit-field of AST_SCU_MPLL */ 53 #define SCU_MPLL_RESET BIT(25) 54 #define SCU_MPLL_BYPASS BIT(24) 55 #define SCU_MPLL_TURN_OFF BIT(23) 56 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 57 58 #define SCU_MPLL_FREQ_400M 0x0008405F 59 #define SCU_MPLL_EXT_400M 0x0000002F 60 //#define SCU_MPLL_FREQ_400M 0x0038007F 61 //#define SCU_MPLL_EXT_400M 0x0000003F 62 #define SCU_MPLL_FREQ_333M 0x00488299 63 #define SCU_MPLL_EXT_333M 0x0000014C 64 #define SCU_MPLL_FREQ_200M 0x0078007F 65 #define SCU_MPLL_EXT_200M 0x0000003F 66 #define SCU_MPLL_FREQ_100M 0x0078003F 67 #define SCU_MPLL_EXT_100M 0x0000001F 68 /* MPLL configuration */ 69 #if defined(CONFIG_ASPEED_DDR4_1600) 70 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 71 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 72 #elif defined(CONFIG_ASPEED_DDR4_1333) 73 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 74 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 75 #elif defined(CONFIG_ASPEED_DDR4_800) 76 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 77 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 78 #elif defined(CONFIG_ASPEED_DDR4_400) 79 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 80 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 81 #else 82 #error "undefined DDR4 target rate\n" 83 #endif 84 85 /* AC timing and SDRAM mode registers */ 86 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 87 /* mode register settings for FPGA are fixed */ 88 #define DDR4_MR01_MODE 0x03010100 89 #define DDR4_MR23_MODE 0x00000000 90 #define DDR4_MR45_MODE 0x04C00000 91 #define DDR4_MR6_MODE 0x00000050 92 #define DDR4_TRFC_FPGA 0x17263434 93 #define DDR4_TRFI 0x5d 94 95 /* FPGA need for an additional initialization procedure: search read window */ 96 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 97 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 98 #define SEARCH_RDWIN_PTRN_0 0x12345678 99 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 100 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 101 #else 102 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 103 #define DDR4_MR01_MODE 0x03010510 104 #define DDR4_MR23_MODE 0x00000000 105 #define DDR4_MR45_MODE 0x04000000 106 #define DDR4_MR6_MODE 0x00000400 107 #define DDR4_TRFC_1600 0x467299f1 108 #define DDR4_TRFC_1333 0x3a5f80c9 109 #define DDR4_TRFC_800 0x23394c78 110 #define DDR4_TRFC_400 0x111c263c 111 /* 112 * tRFI calculation 113 * DDR4 spec. : 114 * tRFI = 7.8 us if temperature is Less/equal than 85 degree celsius 115 * tRFI = 3.9 us if temperature is greater than 85 degree celsius 116 * 117 * tRFI in MCR0C = floor(tRFI * 12.5M) - margin 118 * normal temp. -> floor(7.8 * 12.5) - 2 = 0x5f 119 * high temp. -> floor(3.9 * 12.5) - 1 = 0x2f 120 */ 121 #ifdef CONFIG_ASPEED_HI_TEMP_TRFI 122 #define DDR4_TRFI 0x2f /* High temperature tRFI */ 123 #else 124 #define DDR4_TRFI 0x5f /* Normal temperature tRFI */ 125 #endif /* end of "#ifdef CONFIG_ASPEED_HI_TEMP_TRFI" */ 126 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 127 defined(CONFIG_ASPEED_PALLADIUM)" */ 128 129 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 130 #define DDR4_TRFC DDR4_TRFC_FPGA 131 #else 132 /* real chip setting */ 133 #if defined(CONFIG_ASPEED_DDR4_1600) 134 #define DDR4_TRFC DDR4_TRFC_1600 135 #define DDR4_PHY_TRAIN_TRFC 0xc30 136 #elif defined(CONFIG_ASPEED_DDR4_1333) 137 #define DDR4_TRFC DDR4_TRFC_1333 138 #define DDR4_PHY_TRAIN_TRFC 0xa25 139 #elif defined(CONFIG_ASPEED_DDR4_800) 140 #define DDR4_TRFC DDR4_TRFC_800 141 #define DDR4_PHY_TRAIN_TRFC 0x618 142 #elif defined(CONFIG_ASPEED_DDR4_400) 143 #define DDR4_TRFC DDR4_TRFC_400 144 #define DDR4_PHY_TRAIN_TRFC 0x30c 145 #else 146 #error "undefined tRFC setting" 147 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 148 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 149 defined(CONFIG_ASPEED_PALLADIUM)" */ 150 151 /* supported SDRAM size */ 152 #define SDRAM_SIZE_1KB (1024U) 153 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 154 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 155 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 156 157 158 DECLARE_GLOBAL_DATA_PTR; 159 160 /* 161 * Bandwidth configuration parameters for different SDRAM requests. 162 * These are hardcoded settings taken from Aspeed SDK. 163 */ 164 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 165 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 166 0x00000140 }; 167 168 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 169 0x88888888 }; 170 #else 171 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 172 0x00001240 }; 173 174 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 175 0x44444444 }; 176 #endif 177 178 struct dram_info { 179 struct ram_info info; 180 struct clk ddr_clk; 181 struct ast2600_sdrammc_regs *regs; 182 void __iomem *scu; 183 struct ast2600_ddr_phy *phy; 184 void __iomem *phy_setting; 185 void __iomem *phy_status; 186 ulong clock_rate; 187 }; 188 189 static void ast2600_sdramphy_kick_training(struct dram_info *info) 190 { 191 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 192 struct ast2600_sdrammc_regs *regs = info->regs; 193 u32 volatile data; 194 195 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 196 udelay(5); 197 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 198 udelay(1000); 199 200 while (1) { 201 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 202 if (~data) { 203 break; 204 } 205 } 206 207 #if 0 208 while (1) { 209 data = readl(0x1e6e0400) & BIT(1); 210 if (data) { 211 break; 212 } 213 } 214 #endif 215 #endif 216 } 217 218 /** 219 * @brief load DDR-PHY configurations table to the PHY registers 220 * @param[in] p_tbl - pointer to the configuration table 221 * @param[in] info - pointer to the DRAM info struct 222 * 223 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 224 * system: one is in the SDRAM MC (memory controller) which is used in run 225 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 226 * training. 227 */ 228 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 229 { 230 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 231 u32 reg_base = (u32)info->phy_setting; 232 u32 addr = p_tbl[0]; 233 u32 data; 234 int i = 1; 235 236 writel(0, &info->regs->phy_ctrl[0]); 237 udelay(10); 238 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 239 240 /* load PHY configuration table into PHY-setting registers */ 241 while (1) { 242 if (addr < reg_base) { 243 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 244 break; 245 } 246 data = p_tbl[i++]; 247 248 if (data == DDR_PHY_TBL_END) { 249 break; 250 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 251 addr = p_tbl[i++]; 252 } else { 253 writel(data, addr); 254 addr += 4; 255 } 256 } 257 258 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 259 data |= DDR4_PHY_TRAIN_TRFC; 260 writel(data, info->phy_setting + 0x84); 261 #endif 262 } 263 264 static int ast2600_sdramphy_check_status(struct dram_info *info) 265 { 266 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 267 u32 value, tmp; 268 u32 reg_base = (u32)info->phy_status; 269 int need_retrain = 0; 270 271 debug("\nSDRAM PHY training report:\n"); 272 /* training status */ 273 value = readl(reg_base + 0x00); 274 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 275 if (value & BIT(3)) { 276 debug("\tinitial PVT calibration fail\n"); 277 } 278 if (value & BIT(5)) { 279 debug("\truntime calibration fail\n"); 280 } 281 282 /* PU & PD */ 283 value = readl(reg_base + 0x30); 284 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 285 debug(" PU = 0x%02x\n", value & 0xff); 286 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 287 288 /* read eye window */ 289 value = readl(reg_base + 0x68); 290 if (0 == (value & GENMASK(7, 0))) { 291 need_retrain = 1; 292 } 293 294 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 295 debug(" rising edge of read data eye training pass window\n"); 296 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 297 debug(" B0:%d%%\n", tmp); 298 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 299 debug(" B1:%d%%\n", tmp); 300 301 value = readl(reg_base + 0xC8); 302 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 303 debug(" falling edge of read data eye training pass window\n"); 304 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 305 debug(" B0:%d%%\n", tmp); 306 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 307 debug(" B1:%d%%\n", tmp); 308 309 /* write eye window */ 310 value = readl(reg_base + 0x7c); 311 if (0 == (value & GENMASK(7, 0))) { 312 need_retrain = 1; 313 } 314 315 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 316 debug(" rising edge of write data eye training pass window\n"); 317 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 318 debug(" B0:%d%%\n", tmp); 319 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 320 debug(" B1:%d%%\n", tmp); 321 322 /* read Vref (PHY side) training result */ 323 value = readl(reg_base + 0x88); 324 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 325 326 /* write Vref (DRAM side) training result */ 327 value = readl(reg_base + 0x90); 328 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 329 330 /* gate train */ 331 value = readl(reg_base + 0x50); 332 if ((0 == (value & GENMASK(15, 0))) || 333 (0 == (value & GENMASK(31, 16)))) { 334 need_retrain = 1; 335 } 336 #if 0 337 if (((value >> 24) & 0xff) < 3) 338 need_retrain = 1; 339 else 340 need_retrain = 0; 341 #endif 342 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 343 #if 0 344 debug(" gate training pass window\n"); 345 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 346 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 347 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 348 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 349 #endif 350 351 return need_retrain; 352 #else 353 return 0; 354 #endif 355 } 356 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 357 #define MC_TEST_PATTERN_N 8 358 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 359 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 360 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 361 }; 362 363 #define TIMEOUT_DRAM 5000000 364 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 365 { 366 unsigned int data; 367 unsigned int timeout = 0; 368 struct ast2600_sdrammc_regs *regs = info->regs; 369 370 writel(0, ®s->ecc_test_ctrl); 371 if (mode == 0) 372 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 373 else 374 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 375 376 do { 377 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 378 379 if (data & BIT(13)) 380 return 0; 381 382 if (++timeout > TIMEOUT_DRAM) { 383 printf("Timeout!!\n"); 384 writel(0, ®s->ecc_test_ctrl); 385 386 return 0; 387 } 388 } while (!data); 389 390 writel(0, ®s->ecc_test_ctrl); 391 392 return 1; 393 } 394 395 int ast2600_sdrammc_cbr_test(struct dram_info *info) 396 { 397 struct ast2600_sdrammc_regs *regs = info->regs; 398 u32 i; 399 400 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 401 402 /* single */ 403 for (i = 0; i < 8; i++) { 404 if (!ast2600_sdrammc_dg_test(info, i, 0)) 405 return (0); 406 } 407 408 /* burst */ 409 for (i = 0; i < 8; i++) { 410 if (!ast2600_sdrammc_dg_test(info, i, i)) 411 return (0); 412 } 413 414 return(1); 415 } 416 417 static int ast2600_sdrammc_test(struct dram_info *info) 418 { 419 struct ast2600_sdrammc_regs *regs = info->regs; 420 421 u32 pass_cnt = 0; 422 u32 fail_cnt = 0; 423 u32 target_cnt = 2; 424 u32 test_cnt = 0; 425 u32 pattern; 426 u32 i = 0; 427 bool finish = false; 428 429 debug("sdram mc test:\n"); 430 while (finish == false) { 431 pattern = as2600_sdrammc_test_pattern[i++]; 432 i = i % MC_TEST_PATTERN_N; 433 debug(" pattern = %08x : ", pattern); 434 writel(pattern, ®s->test_init_val); 435 436 if (!ast2600_sdrammc_cbr_test(info)) { 437 debug("fail\n"); 438 fail_cnt++; 439 } else { 440 debug("pass\n"); 441 pass_cnt++; 442 } 443 444 if (++test_cnt == target_cnt) { 445 finish = true; 446 } 447 } 448 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 449 target_cnt); 450 return fail_cnt; 451 } 452 #endif 453 /** 454 * scu500[14:13] 455 * 2b'00: VGA memory size = 16MB 456 * 2b'01: VGA memory size = 16MB 457 * 2b'10: VGA memory size = 32MB 458 * 2b'11: VGA memory size = 64MB 459 * 460 * mcr04[3:2] 461 * 2b'00: VGA memory size = 8MB 462 * 2b'01: VGA memory size = 16MB 463 * 2b'10: VGA memory size = 32MB 464 * 2b'11: VGA memory size = 64MB 465 */ 466 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 467 { 468 u32 vga_hwconf; 469 size_t vga_mem_size_base = 8 * 1024 * 1024; 470 471 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 472 SCU_HWSTRAP_VGAMEM_MASK) >> 473 SCU_HWSTRAP_VGAMEM_SHIFT; 474 475 if (vga_hwconf == 0) { 476 vga_hwconf = 1; 477 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 478 info->scu + AST_SCU_HW_STRAP); 479 } 480 481 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 482 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 483 SDRAM_CONF_VGA_SIZE_MASK)); 484 485 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 486 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 487 return 0; 488 489 return vga_mem_size_base << vga_hwconf; 490 } 491 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 492 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 493 { 494 u32 data; 495 u32 scu_base = (u32)info->scu; 496 497 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 498 499 do { 500 data = readl(scu_base + AST_SCU_FPGA_STATUS); 501 } while (!(data & 0x100)); 502 503 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 504 } 505 506 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 507 { 508 u32 pll, pll_min, pll_max, dat1, offset; 509 u32 win = 0x03, gwin = 0, gwinsize = 0; 510 u32 phy_setting = (u32)info->phy_setting; 511 512 #ifdef CONFIG_ASPEED_PALLADIUM 513 writel(0xc, phy_setting + 0x0000); 514 return 1; 515 #endif 516 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 517 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 518 519 while (gwin == 0) { 520 while (!(win & 0x80)) { 521 debug("Window = 0x%X\n", win); 522 writel(win, phy_setting + 0x0000); 523 524 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 525 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 526 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 527 ast2600_sdrammc_fpga_set_pll(info); 528 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 529 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 530 } 531 532 pll_min = 0xfff; 533 pll_max = 0x0; 534 pll = 0; 535 while (pll_max > 0 || pll < 256) { 536 ast2600_sdrammc_fpga_set_pll(info); 537 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 538 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 539 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 540 if (pll_min > pll) 541 pll_min = pll; 542 543 if (pll_max < pll) 544 pll_max = pll; 545 546 debug("%3d_(%3d:%3d)\n", pll, pll_min, 547 pll_max); 548 } else if (pll_max > 0) { 549 pll_min = pll_max - pll_min; 550 if (gwinsize < pll_min) { 551 gwin = win; 552 gwinsize = pll_min; 553 } 554 break; 555 } 556 pll += 1; 557 } 558 559 if (gwin != 0 && pll_max == 0) 560 break; 561 562 win = win << 1; 563 } 564 if (gwin == 0) 565 win = 0x7; 566 } 567 debug("Set PLL Read Gating Window = %x\n", gwin); 568 writel(gwin, phy_setting + 0x0000); 569 570 debug("PLL Read Window training\n"); 571 pll_min = 0xfff; 572 pll_max = 0x0; 573 574 debug("Search Window Start\n"); 575 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 576 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 577 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 578 ast2600_sdrammc_fpga_set_pll(info); 579 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 580 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 581 } 582 583 debug("Search Window Margin\n"); 584 pll = 0; 585 while (pll_max > 0 || pll < 256) { 586 ast2600_sdrammc_fpga_set_pll(info); 587 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 588 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 589 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 590 if (pll_min > pll) 591 pll_min = pll; 592 593 if (pll_max < pll) 594 pll_max = pll; 595 596 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 597 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 598 break; 599 } else if (pll_max > 0) { 600 pll_min = 0xfff; 601 pll_max = 0x0; 602 } 603 pll += 1; 604 } 605 if (pll_min < pll_max) { 606 debug("PLL Read window = %d\n", (pll_max - pll_min)); 607 offset = (pll_max - pll_min) >> 1; 608 pll_min = 0xfff; 609 pll = 0; 610 while (pll < (pll_min + offset)) { 611 ast2600_sdrammc_fpga_set_pll(info); 612 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 613 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 614 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 615 if (pll_min > pll) { 616 pll_min = pll; 617 } 618 debug("%d\n", pll); 619 } else { 620 pll_min = 0xfff; 621 pll_max = 0x0; 622 } 623 pll += 1; 624 } 625 return (1); 626 } else { 627 debug("PLL Read window training fail\n"); 628 return 0; 629 } 630 } 631 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 632 defined(CONFIG_ASPEED_PALLADIUM)" */ 633 634 /* 635 * Find out RAM size and save it in dram_info 636 * 637 * The procedure is taken from Aspeed SDK 638 */ 639 static void ast2600_sdrammc_calc_size(struct dram_info *info) 640 { 641 /* The controller supports 256/512/1024/2048 MB ram */ 642 size_t ram_size = SDRAM_MIN_SIZE; 643 const int write_test_offset = 0x100000; 644 u32 test_pattern = 0xdeadbeef; 645 u32 cap_param = SDRAM_CONF_CAP_2048M; 646 u32 refresh_timing_param = DDR4_TRFC; 647 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 648 649 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 650 ram_size >>= 1) { 651 writel(test_pattern, write_addr_base + (ram_size >> 1)); 652 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 653 } 654 655 /* One last write to overwrite all wrapped values */ 656 writel(test_pattern, write_addr_base); 657 658 /* Reset the pattern and see which value was really written */ 659 test_pattern = 0xdeadbeef; 660 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 661 ram_size >>= 1) { 662 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 663 break; 664 665 --cap_param; 666 refresh_timing_param >>= 8; 667 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 668 } 669 670 clrsetbits_le32(&info->regs->ac_timing[1], 671 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 672 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 673 << SDRAM_AC_TRFC_SHIFT)); 674 675 info->info.base = CONFIG_SYS_SDRAM_BASE; 676 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 677 678 clrsetbits_le32( 679 &info->regs->config, SDRAM_CONF_CAP_MASK, 680 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 681 } 682 683 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 684 { 685 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 686 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 687 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 688 (0x1 << MCR34_ODT_EXT_SHIFT); 689 690 /* init SDRAM-PHY only on real chip */ 691 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 692 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 693 &info->regs->power_ctrl); 694 udelay(5); 695 ast2600_sdramphy_kick_training(info); 696 udelay(500); 697 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 698 699 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 700 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 701 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 702 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 703 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 704 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 705 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 706 &info->regs->mode_setting_control); 707 708 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 709 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT), 710 &info->regs->refresh_timing); 711 712 /* wait self-refresh idle */ 713 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 714 ; 715 716 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 717 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 718 SDRAM_REFRESH_ZQCS_EN | 719 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 720 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 721 &info->regs->refresh_timing); 722 #else 723 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 724 SDRAM_REFRESH_ZQCS_EN | 725 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 726 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 727 &info->regs->refresh_timing); 728 #endif 729 730 writel(power_ctrl, &info->regs->power_ctrl); 731 udelay(500); 732 733 #if defined(CONFIG_FPGA_ASPEED) 734 /* toggle Vref training */ 735 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 736 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 737 &info->regs->mode_setting_control); 738 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 739 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 740 &info->regs->mode_setting_control); 741 #endif 742 return 0; 743 } 744 745 static void ast2600_sdrammc_unlock(struct dram_info *info) 746 { 747 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 748 while (!readl(&info->regs->protection_key)) 749 ; 750 } 751 752 static void ast2600_sdrammc_lock(struct dram_info *info) 753 { 754 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 755 while (readl(&info->regs->protection_key)) 756 ; 757 } 758 759 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 760 { 761 int i; 762 763 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 764 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 765 /* [6:0] : Group 1 request queued number = 16 766 * [14:8] : Group 2 request queued number = 16 767 * [20:16] : R/W max-grant count for RQ output arbitration = 16 768 */ 769 writel(0x101010, ®s->arbitration_ctrl); 770 /* Request Queued Limitation for REQ8/9 USB1/2 */ 771 writel(0x0FFF3CEF, ®s->req_limit_mask); 772 773 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 774 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 775 776 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 777 778 /* FIXME: the sample code does NOT match the datasheet */ 779 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 780 781 writel(0, ®s->ecc_test_ctrl); 782 writel(0x80000001, ®s->test_addr); 783 writel(0, ®s->test_fail_dq_bit); 784 writel(0, ®s->test_init_val); 785 786 writel(0xFFFFFFFF, ®s->req_input_ctrl); 787 writel(0x300, ®s->req_high_pri_ctrl); 788 789 udelay(600); 790 791 #ifdef CONFIG_ASPEED_DDR4_DUALX8 792 writel(0xa037, ®s->config); 793 #else 794 writel(0xa017, ®s->config); 795 #endif 796 797 /* load controller setting */ 798 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 799 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 800 801 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 802 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 803 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 804 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 805 } 806 /* 807 * Update size info according to the ECC HW setting 808 * 809 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 810 * don't need to calculate the ECC size again but read from MCR04 and derive the 811 * size from its value. 812 */ 813 static void ast2600_sdrammc_update_size(struct dram_info *info) 814 { 815 struct ast2600_sdrammc_regs *regs = info->regs; 816 size_t hw_size; 817 size_t ram_size = SDRAM_MAX_SIZE; 818 u32 cap_param; 819 820 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 821 switch (cap_param) 822 { 823 case SDRAM_CONF_CAP_2048M: 824 ram_size = 2048 * SDRAM_SIZE_1MB; 825 break; 826 case SDRAM_CONF_CAP_1024M: 827 ram_size = 1024 * SDRAM_SIZE_1MB; 828 break; 829 case SDRAM_CONF_CAP_512M: 830 ram_size = 512 * SDRAM_SIZE_1MB; 831 break; 832 case SDRAM_CONF_CAP_256M: 833 ram_size = 256 * SDRAM_SIZE_1MB; 834 break; 835 } 836 837 info->info.base = CONFIG_SYS_SDRAM_BASE; 838 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 839 840 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 841 return; 842 843 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 844 hw_size += (1 << 20); 845 846 info->info.size = hw_size; 847 } 848 #ifdef CONFIG_ASPEED_ECC 849 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 850 { 851 struct ast2600_sdrammc_regs *regs = info->regs; 852 size_t conf_size; 853 u32 reg; 854 855 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 856 if (conf_size > info->info.size) { 857 printf("warning: ECC configured %dMB but actual size is %dMB\n", 858 CONFIG_ASPEED_ECC_SIZE, 859 info->info.size / SDRAM_SIZE_1MB); 860 conf_size = info->info.size; 861 } else if (conf_size == 0) { 862 conf_size = info->info.size; 863 } 864 865 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 866 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 867 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 868 writel(reg, ®s->config); 869 870 writel(0, ®s->test_init_val); 871 writel(0x80000001, ®s->test_addr); 872 writel(0x221, ®s->ecc_test_ctrl); 873 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 874 ; 875 writel(0, ®s->ecc_test_ctrl); 876 writel(BIT(31), ®s->intr_ctrl); 877 writel(0, ®s->intr_ctrl); 878 } 879 #endif 880 881 static int ast2600_sdrammc_probe(struct udevice *dev) 882 { 883 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 884 struct ast2600_sdrammc_regs *regs = priv->regs; 885 struct udevice *clk_dev; 886 int ret; 887 volatile uint32_t reg; 888 889 /* find SCU base address from clock device */ 890 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 891 &clk_dev); 892 if (ret) { 893 debug("clock device not defined\n"); 894 return ret; 895 } 896 897 priv->scu = devfdt_get_addr_ptr(clk_dev); 898 if (IS_ERR(priv->scu)) { 899 debug("%s(): can't get SCU\n", __func__); 900 return PTR_ERR(priv->scu); 901 } 902 903 reg = readl(priv->scu + AST_SCU_HANDSHAKE); 904 if (reg & SCU_SDRAM_INIT_READY_MASK) { 905 printf("already initialized, "); 906 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 907 ast2600_sdrammc_update_size(priv); 908 return 0; 909 } 910 911 #ifdef AST2600_SDRAMMC_MANUAL_CLK 912 reg = readl(priv->scu + AST_SCU_MPLL); 913 reg &= ~(BIT(24) | GENMASK(22, 0)); 914 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 915 writel(reg, priv->scu + AST_SCU_MPLL); 916 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 917 udelay(100); 918 reg &= ~(BIT(25) | BIT(23)); 919 writel(reg, priv->scu + AST_SCU_MPLL); 920 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 921 ; 922 #else 923 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 924 if (ret) { 925 debug("DDR:No CLK\n"); 926 return ret; 927 } 928 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 929 #endif 930 931 #if 0 932 /* FIXME: enable the following code if reset-driver is ready */ 933 struct reset_ctl reset_ctl; 934 ret = reset_get_by_index(dev, 0, &reset_ctl); 935 if (ret) { 936 debug("%s(): Failed to get reset signal\n", __func__); 937 return ret; 938 } 939 940 ret = reset_assert(&reset_ctl); 941 if (ret) { 942 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 943 return ret; 944 } 945 #endif 946 947 ast2600_sdrammc_unlock(priv); 948 ast2600_sdrammc_common_init(regs); 949 L_ast2600_sdramphy_train: 950 ast2600_sdrammc_init_ddr4(priv); 951 952 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 953 ast2600_sdrammc_search_read_window(priv); 954 #else 955 /* make sure DDR-PHY is ready before access */ 956 do { 957 reg = readl(priv->phy_status) & BIT(1); 958 } while (reg == 0); 959 #endif 960 961 ret = ast2600_sdramphy_check_status(priv); 962 if (ret) { 963 printf("DDR4 PHY training fail, retrain\n"); 964 goto L_ast2600_sdramphy_train; 965 } 966 967 ast2600_sdrammc_calc_size(priv); 968 969 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 970 ret = ast2600_sdrammc_test(priv); 971 if (ret) { 972 printf("%s: DDR4 init fail\n", __func__); 973 return -EINVAL; 974 } 975 #endif 976 977 #ifdef CONFIG_ASPEED_ECC 978 ast2600_sdrammc_ecc_enable(priv); 979 #endif 980 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 981 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 982 ast2600_sdrammc_lock(priv); 983 return 0; 984 } 985 986 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 987 { 988 struct dram_info *priv = dev_get_priv(dev); 989 990 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 991 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 992 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 993 994 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 995 "clock-frequency", 0); 996 if (!priv->clock_rate) { 997 debug("DDR Clock Rate not defined\n"); 998 return -EINVAL; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 1005 { 1006 struct dram_info *priv = dev_get_priv(dev); 1007 1008 *info = priv->info; 1009 1010 return 0; 1011 } 1012 1013 static struct ram_ops ast2600_sdrammc_ops = { 1014 .get_info = ast2600_sdrammc_get_info, 1015 }; 1016 1017 static const struct udevice_id ast2600_sdrammc_ids[] = { 1018 { .compatible = "aspeed,ast2600-sdrammc" }, 1019 { } 1020 }; 1021 1022 U_BOOT_DRIVER(sdrammc_ast2600) = { 1023 .name = "aspeed_ast2600_sdrammc", 1024 .id = UCLASS_RAM, 1025 .of_match = ast2600_sdrammc_ids, 1026 .ops = &ast2600_sdrammc_ops, 1027 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1028 .probe = ast2600_sdrammc_probe, 1029 .priv_auto_alloc_size = sizeof(struct dram_info), 1030 }; 1031