1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 45 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 46 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 47 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 48 #define SCU_HANDSHAKE_MASK \ 49 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 50 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 51 52 /* bit-field of AST_SCU_MPLL */ 53 #define SCU_MPLL_RESET BIT(25) 54 #define SCU_MPLL_BYPASS BIT(24) 55 #define SCU_MPLL_TURN_OFF BIT(23) 56 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 57 58 #define SCU_MPLL_FREQ_400M 0x0008405F 59 #define SCU_MPLL_EXT_400M 0x0000002F 60 //#define SCU_MPLL_FREQ_400M 0x0038007F 61 //#define SCU_MPLL_EXT_400M 0x0000003F 62 #define SCU_MPLL_FREQ_333M 0x00488299 63 #define SCU_MPLL_EXT_333M 0x0000014C 64 #define SCU_MPLL_FREQ_200M 0x0078007F 65 #define SCU_MPLL_EXT_200M 0x0000003F 66 #define SCU_MPLL_FREQ_100M 0x0078003F 67 #define SCU_MPLL_EXT_100M 0x0000001F 68 /* MPLL configuration */ 69 #if defined(CONFIG_ASPEED_DDR4_1600) 70 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 71 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 72 #elif defined(CONFIG_ASPEED_DDR4_1333) 73 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 74 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 75 #elif defined(CONFIG_ASPEED_DDR4_800) 76 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 77 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 78 #elif defined(CONFIG_ASPEED_DDR4_400) 79 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 80 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 81 #else 82 #error "undefined DDR4 target rate\n" 83 #endif 84 85 /* AC timing and SDRAM mode registers */ 86 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 87 /* mode register settings for FPGA are fixed */ 88 #define DDR4_MR01_MODE 0x03010100 89 #define DDR4_MR23_MODE 0x00000000 90 #define DDR4_MR45_MODE 0x04C00000 91 #define DDR4_MR6_MODE 0x00000050 92 #define DDR4_TRFC_FPGA 0x17263434 93 94 /* FPGA need for an additional initialization procedure: search read window */ 95 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 96 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 97 #define SEARCH_RDWIN_PTRN_0 0x12345678 98 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 99 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 100 #else 101 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 102 #define DDR4_MR01_MODE 0x03010510 103 #define DDR4_MR23_MODE 0x00000000 104 #define DDR4_MR45_MODE 0x04000000 105 #define DDR4_MR6_MODE 0x00000400 106 #define DDR4_TRFC_1600 0x467299f1 107 #define DDR4_TRFC_1333 0x3a5f80c9 108 #define DDR4_TRFC_800 0x23394c78 109 #define DDR4_TRFC_400 0x111c263c 110 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 111 defined(CONFIG_ASPEED_PALLADIUM)" */ 112 113 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 114 #define DDR4_TRFC DDR4_TRFC_FPGA 115 #else 116 /* real chip setting */ 117 #if defined(CONFIG_ASPEED_DDR4_1600) 118 #define DDR4_TRFC DDR4_TRFC_1600 119 #define DDR4_PHY_TRAIN_TRFC 0xc30 120 #elif defined(CONFIG_ASPEED_DDR4_1333) 121 #define DDR4_TRFC DDR4_TRFC_1333 122 #define DDR4_PHY_TRAIN_TRFC 0xa25 123 #elif defined(CONFIG_ASPEED_DDR4_800) 124 #define DDR4_TRFC DDR4_TRFC_800 125 #define DDR4_PHY_TRAIN_TRFC 0x618 126 #elif defined(CONFIG_ASPEED_DDR4_400) 127 #define DDR4_TRFC DDR4_TRFC_400 128 #define DDR4_PHY_TRAIN_TRFC 0x30c 129 #else 130 #error "undefined tRFC setting" 131 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 132 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 133 defined(CONFIG_ASPEED_PALLADIUM)" */ 134 135 /* supported SDRAM size */ 136 #define SDRAM_SIZE_1KB (1024U) 137 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 138 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 139 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 140 141 142 DECLARE_GLOBAL_DATA_PTR; 143 144 /* 145 * Bandwidth configuration parameters for different SDRAM requests. 146 * These are hardcoded settings taken from Aspeed SDK. 147 */ 148 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 149 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 150 0x00000140 }; 151 152 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 153 0x88888888 }; 154 #else 155 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 156 0x00001240 }; 157 158 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 159 0x44444444 }; 160 #endif 161 162 struct dram_info { 163 struct ram_info info; 164 struct clk ddr_clk; 165 struct ast2600_sdrammc_regs *regs; 166 void __iomem *scu; 167 struct ast2600_ddr_phy *phy; 168 void __iomem *phy_setting; 169 void __iomem *phy_status; 170 ulong clock_rate; 171 }; 172 173 static void ast2600_sdramphy_kick_training(struct dram_info *info) 174 { 175 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 176 struct ast2600_sdrammc_regs *regs = info->regs; 177 u32 volatile data; 178 179 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 180 udelay(5); 181 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 182 udelay(1000); 183 184 while (1) { 185 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 186 if (~data) { 187 break; 188 } 189 } 190 191 #if 0 192 while (1) { 193 data = readl(0x1e6e0400) & BIT(1); 194 if (data) { 195 break; 196 } 197 } 198 #endif 199 #endif 200 } 201 202 /** 203 * @brief load DDR-PHY configurations table to the PHY registers 204 * @param[in] p_tbl - pointer to the configuration table 205 * @param[in] info - pointer to the DRAM info struct 206 * 207 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 208 * system: one is in the SDRAM MC (memory controller) which is used in run 209 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 210 * training. 211 */ 212 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 213 { 214 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 215 u32 reg_base = (u32)info->phy_setting; 216 u32 addr = p_tbl[0]; 217 u32 data; 218 int i = 1; 219 220 writel(0, &info->regs->phy_ctrl[0]); 221 udelay(10); 222 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 223 224 /* load PHY configuration table into PHY-setting registers */ 225 while (1) { 226 if (addr < reg_base) { 227 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 228 break; 229 } 230 data = p_tbl[i++]; 231 232 if (data == DDR_PHY_TBL_END) { 233 break; 234 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 235 addr = p_tbl[i++]; 236 } else { 237 writel(data, addr); 238 addr += 4; 239 } 240 } 241 242 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 243 data |= DDR4_PHY_TRAIN_TRFC; 244 writel(data, info->phy_setting + 0x84); 245 #endif 246 } 247 248 static int ast2600_sdramphy_check_status(struct dram_info *info) 249 { 250 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 251 u32 value, tmp; 252 u32 reg_base = (u32)info->phy_status; 253 int need_retrain = 0; 254 255 debug("\nSDRAM PHY training report:\n"); 256 /* training status */ 257 value = readl(reg_base + 0x00); 258 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 259 if (value & BIT(3)) { 260 debug("\tinitial PVT calibration fail\n"); 261 } 262 if (value & BIT(5)) { 263 debug("\truntime calibration fail\n"); 264 } 265 266 /* PU & PD */ 267 value = readl(reg_base + 0x30); 268 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 269 debug(" PU = 0x%02x\n", value & 0xff); 270 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 271 272 /* read eye window */ 273 value = readl(reg_base + 0x68); 274 if (0 == (value & GENMASK(7, 0))) { 275 need_retrain = 1; 276 } 277 278 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 279 debug(" rising edge of read data eye training pass window\n"); 280 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 281 debug(" B0:%d%%\n", tmp); 282 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 283 debug(" B1:%d%%\n", tmp); 284 285 value = readl(reg_base + 0xC8); 286 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 287 debug(" falling edge of read data eye training pass window\n"); 288 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 289 debug(" B0:%d%%\n", tmp); 290 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 291 debug(" B1:%d%%\n", tmp); 292 293 /* write eye window */ 294 value = readl(reg_base + 0x7c); 295 if (0 == (value & GENMASK(7, 0))) { 296 need_retrain = 1; 297 } 298 299 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 300 debug(" rising edge of write data eye training pass window\n"); 301 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 302 debug(" B0:%d%%\n", tmp); 303 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 304 debug(" B1:%d%%\n", tmp); 305 306 /* read Vref training result */ 307 value = readl(reg_base + 0x88); 308 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 309 310 /* write Vref training result */ 311 value = readl(reg_base + 0x90); 312 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 313 #if 0 314 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 315 debug(" write Vref training result = %d%%\n", tmp); 316 #endif 317 318 /* gate train */ 319 value = readl(reg_base + 0x50); 320 if ((0 == (value & GENMASK(15, 0))) || 321 (0 == (value & GENMASK(31, 16)))) { 322 need_retrain = 1; 323 } 324 #if 0 325 if (((value >> 24) & 0xff) < 3) 326 need_retrain = 1; 327 else 328 need_retrain = 0; 329 #endif 330 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 331 #if 0 332 debug(" gate training pass window\n"); 333 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 334 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 335 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 336 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 337 #endif 338 339 return need_retrain; 340 #else 341 return 0; 342 #endif 343 } 344 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 345 #define MC_TEST_PATTERN_N 8 346 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 347 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 348 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 349 }; 350 351 #define TIMEOUT_DRAM 5000000 352 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 353 { 354 unsigned int data; 355 unsigned int timeout = 0; 356 struct ast2600_sdrammc_regs *regs = info->regs; 357 358 writel(0, ®s->ecc_test_ctrl); 359 if (mode == 0) 360 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 361 else 362 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 363 364 do { 365 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 366 367 if (data & BIT(13)) 368 return 0; 369 370 if (++timeout > TIMEOUT_DRAM) { 371 printf("Timeout!!\n"); 372 writel(0, ®s->ecc_test_ctrl); 373 374 return 0; 375 } 376 } while (!data); 377 378 writel(0, ®s->ecc_test_ctrl); 379 380 return 1; 381 } 382 383 int ast2600_sdrammc_cbr_test(struct dram_info *info) 384 { 385 struct ast2600_sdrammc_regs *regs = info->regs; 386 u32 i; 387 388 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 389 390 /* single */ 391 for (i = 0; i < 8; i++) { 392 if (!ast2600_sdrammc_dg_test(info, i, 0)) 393 return (0); 394 } 395 396 /* burst */ 397 for (i = 0; i < 8; i++) { 398 if (!ast2600_sdrammc_dg_test(info, i, i)) 399 return (0); 400 } 401 402 return(1); 403 } 404 405 static int ast2600_sdrammc_test(struct dram_info *info) 406 { 407 struct ast2600_sdrammc_regs *regs = info->regs; 408 409 u32 pass_cnt = 0; 410 u32 fail_cnt = 0; 411 u32 target_cnt = 2; 412 u32 test_cnt = 0; 413 u32 pattern; 414 u32 i = 0; 415 bool finish = false; 416 417 debug("sdram mc test:\n"); 418 while (finish == false) { 419 pattern = as2600_sdrammc_test_pattern[i++]; 420 i = i % MC_TEST_PATTERN_N; 421 debug(" pattern = %08X : ", pattern); 422 writel(pattern, ®s->test_init_val); 423 424 if (!ast2600_sdrammc_cbr_test(info)) { 425 debug("fail\n"); 426 fail_cnt++; 427 } else { 428 debug("pass\n"); 429 pass_cnt++; 430 } 431 432 if (++test_cnt == target_cnt) { 433 finish = true; 434 } 435 } 436 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 437 target_cnt); 438 return fail_cnt; 439 } 440 #endif 441 /** 442 * scu500[14:13] 443 * 2b'00: VGA memory size = 16MB 444 * 2b'01: VGA memory size = 16MB 445 * 2b'10: VGA memory size = 32MB 446 * 2b'11: VGA memory size = 64MB 447 * 448 * mcr04[3:2] 449 * 2b'00: VGA memory size = 8MB 450 * 2b'01: VGA memory size = 16MB 451 * 2b'10: VGA memory size = 32MB 452 * 2b'11: VGA memory size = 64MB 453 */ 454 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 455 { 456 u32 vga_hwconf; 457 size_t vga_mem_size_base = 8 * 1024 * 1024; 458 459 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 460 SCU_HWSTRAP_VGAMEM_MASK) >> 461 SCU_HWSTRAP_VGAMEM_SHIFT; 462 463 if (vga_hwconf == 0) { 464 vga_hwconf = 1; 465 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 466 info->scu + AST_SCU_HW_STRAP); 467 } 468 469 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 470 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 471 SDRAM_CONF_VGA_SIZE_MASK)); 472 473 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 474 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 475 return 0; 476 477 return vga_mem_size_base << vga_hwconf; 478 } 479 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 480 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 481 { 482 u32 data; 483 u32 scu_base = (u32)info->scu; 484 485 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 486 487 do { 488 data = readl(scu_base + AST_SCU_FPGA_STATUS); 489 } while (!(data & 0x100)); 490 491 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 492 } 493 494 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 495 { 496 u32 pll, pll_min, pll_max, dat1, offset; 497 u32 win = 0x03, gwin = 0, gwinsize = 0; 498 u32 phy_setting = (u32)info->phy_setting; 499 500 #ifdef CONFIG_ASPEED_PALLADIUM 501 writel(0xc, phy_setting + 0x0000); 502 return 1; 503 #endif 504 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 505 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 506 507 while (gwin == 0) { 508 while (!(win & 0x80)) { 509 debug("Window = 0x%X\n", win); 510 writel(win, phy_setting + 0x0000); 511 512 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 513 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 514 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 515 ast2600_sdrammc_fpga_set_pll(info); 516 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 517 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 518 } 519 520 pll_min = 0xfff; 521 pll_max = 0x0; 522 pll = 0; 523 while (pll_max > 0 || pll < 256) { 524 ast2600_sdrammc_fpga_set_pll(info); 525 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 526 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 527 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 528 if (pll_min > pll) 529 pll_min = pll; 530 531 if (pll_max < pll) 532 pll_max = pll; 533 534 debug("%3d_(%3d:%3d)\n", pll, pll_min, 535 pll_max); 536 } else if (pll_max > 0) { 537 pll_min = pll_max - pll_min; 538 if (gwinsize < pll_min) { 539 gwin = win; 540 gwinsize = pll_min; 541 } 542 break; 543 } 544 pll += 1; 545 } 546 547 if (gwin != 0 && pll_max == 0) 548 break; 549 550 win = win << 1; 551 } 552 if (gwin == 0) 553 win = 0x7; 554 } 555 debug("Set PLL Read Gating Window = %x\n", gwin); 556 writel(gwin, phy_setting + 0x0000); 557 558 debug("PLL Read Window training\n"); 559 pll_min = 0xfff; 560 pll_max = 0x0; 561 562 debug("Search Window Start\n"); 563 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 564 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 565 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 566 ast2600_sdrammc_fpga_set_pll(info); 567 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 568 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 569 } 570 571 debug("Search Window Margin\n"); 572 pll = 0; 573 while (pll_max > 0 || pll < 256) { 574 ast2600_sdrammc_fpga_set_pll(info); 575 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 576 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 577 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 578 if (pll_min > pll) 579 pll_min = pll; 580 581 if (pll_max < pll) 582 pll_max = pll; 583 584 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 585 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 586 break; 587 } else if (pll_max > 0) { 588 pll_min = 0xfff; 589 pll_max = 0x0; 590 } 591 pll += 1; 592 } 593 if (pll_min < pll_max) { 594 debug("PLL Read window = %d\n", (pll_max - pll_min)); 595 offset = (pll_max - pll_min) >> 1; 596 pll_min = 0xfff; 597 pll = 0; 598 while (pll < (pll_min + offset)) { 599 ast2600_sdrammc_fpga_set_pll(info); 600 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 601 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 602 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 603 if (pll_min > pll) { 604 pll_min = pll; 605 } 606 debug("%d\n", pll); 607 } else { 608 pll_min = 0xfff; 609 pll_max = 0x0; 610 } 611 pll += 1; 612 } 613 return (1); 614 } else { 615 debug("PLL Read window training fail\n"); 616 return 0; 617 } 618 } 619 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 620 defined(CONFIG_ASPEED_PALLADIUM)" */ 621 622 /* 623 * Find out RAM size and save it in dram_info 624 * 625 * The procedure is taken from Aspeed SDK 626 */ 627 static void ast2600_sdrammc_calc_size(struct dram_info *info) 628 { 629 /* The controller supports 256/512/1024/2048 MB ram */ 630 size_t ram_size = SDRAM_MIN_SIZE; 631 const int write_test_offset = 0x100000; 632 u32 test_pattern = 0xdeadbeef; 633 u32 cap_param = SDRAM_CONF_CAP_2048M; 634 u32 refresh_timing_param = DDR4_TRFC; 635 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 636 637 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 638 ram_size >>= 1) { 639 writel(test_pattern, write_addr_base + (ram_size >> 1)); 640 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 641 } 642 643 /* One last write to overwrite all wrapped values */ 644 writel(test_pattern, write_addr_base); 645 646 /* Reset the pattern and see which value was really written */ 647 test_pattern = 0xdeadbeef; 648 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 649 ram_size >>= 1) { 650 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 651 break; 652 653 --cap_param; 654 refresh_timing_param >>= 8; 655 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 656 } 657 658 clrsetbits_le32(&info->regs->ac_timing[1], 659 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 660 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 661 << SDRAM_AC_TRFC_SHIFT)); 662 663 info->info.base = CONFIG_SYS_SDRAM_BASE; 664 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 665 666 clrsetbits_le32( 667 &info->regs->config, SDRAM_CONF_CAP_MASK, 668 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 669 } 670 671 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 672 { 673 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 674 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 675 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 676 (0x1 << MCR34_ODT_EXT_SHIFT); 677 678 /* init SDRAM-PHY only on real chip */ 679 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 680 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 681 &info->regs->power_ctrl); 682 udelay(5); 683 ast2600_sdramphy_kick_training(info); 684 udelay(500); 685 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 686 687 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 688 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 689 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 690 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 691 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 692 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 693 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 694 &info->regs->mode_setting_control); 695 696 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 697 698 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 699 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 700 &info->regs->refresh_timing); 701 #else 702 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 703 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 704 &info->regs->refresh_timing); 705 #endif 706 707 /* wait self-refresh idle */ 708 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 709 ; 710 711 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 712 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 713 SDRAM_REFRESH_ZQCS_EN | 714 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 715 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 716 &info->regs->refresh_timing); 717 #else 718 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 719 SDRAM_REFRESH_ZQCS_EN | 720 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 721 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 722 &info->regs->refresh_timing); 723 #endif 724 725 writel(power_ctrl, &info->regs->power_ctrl); 726 udelay(500); 727 728 #if defined(CONFIG_FPGA_ASPEED) 729 /* toggle Vref training */ 730 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 731 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 732 &info->regs->mode_setting_control); 733 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 734 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 735 &info->regs->mode_setting_control); 736 #endif 737 return 0; 738 } 739 740 static void ast2600_sdrammc_unlock(struct dram_info *info) 741 { 742 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 743 while (!readl(&info->regs->protection_key)) 744 ; 745 } 746 747 static void ast2600_sdrammc_lock(struct dram_info *info) 748 { 749 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 750 while (readl(&info->regs->protection_key)) 751 ; 752 } 753 754 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 755 { 756 int i; 757 758 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 759 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 760 /* [6:0] : Group 1 request queued number = 16 761 * [14:8] : Group 2 request queued number = 16 762 * [20:16] : R/W max-grant count for RQ output arbitration = 16 763 */ 764 writel(0x101010, ®s->arbitration_ctrl); 765 /* Request Queued Limitation for REQ8/9 USB1/2 */ 766 writel(0x0FFF3CEF, ®s->req_limit_mask); 767 768 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 769 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 770 771 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 772 773 /* FIXME: the sample code does NOT match the datasheet */ 774 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 775 776 writel(0, ®s->ecc_test_ctrl); 777 writel(0x80000001, ®s->test_addr); 778 writel(0, ®s->test_fail_dq_bit); 779 writel(0, ®s->test_init_val); 780 781 writel(0xFFFFFFFF, ®s->req_input_ctrl); 782 writel(0x300, ®s->req_high_pri_ctrl); 783 784 udelay(600); 785 786 #ifdef CONFIG_ASPEED_DDR4_DUALX8 787 writel(0xa037, ®s->config); 788 #else 789 writel(0xa017, ®s->config); 790 #endif 791 792 /* load controller setting */ 793 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 794 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 795 796 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 797 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 798 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 799 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 800 } 801 /* 802 * Update size info according to the ECC HW setting 803 * 804 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 805 * don't need to calculate the ECC size again but read from MCR04 and derive the 806 * size from its value. 807 */ 808 static void ast2600_sdrammc_update_size(struct dram_info *info) 809 { 810 struct ast2600_sdrammc_regs *regs = info->regs; 811 size_t hw_size; 812 size_t ram_size = SDRAM_MAX_SIZE; 813 u32 cap_param; 814 815 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 816 switch (cap_param) 817 { 818 case SDRAM_CONF_CAP_2048M: 819 ram_size = 2048 * SDRAM_SIZE_1MB; 820 break; 821 case SDRAM_CONF_CAP_1024M: 822 ram_size = 1024 * SDRAM_SIZE_1MB; 823 break; 824 case SDRAM_CONF_CAP_512M: 825 ram_size = 512 * SDRAM_SIZE_1MB; 826 break; 827 case SDRAM_CONF_CAP_256M: 828 ram_size = 256 * SDRAM_SIZE_1MB; 829 break; 830 } 831 832 info->info.base = CONFIG_SYS_SDRAM_BASE; 833 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 834 835 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 836 return; 837 838 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 839 hw_size += (1 << 20); 840 841 info->info.size = hw_size; 842 } 843 #ifdef CONFIG_ASPEED_ECC 844 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 845 { 846 struct ast2600_sdrammc_regs *regs = info->regs; 847 size_t conf_size; 848 u32 reg; 849 850 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 851 if (conf_size > info->info.size) { 852 printf("warning: ECC configured %dMB but actual size is %dMB\n", 853 CONFIG_ASPEED_ECC_SIZE, 854 info->info.size / SDRAM_SIZE_1MB); 855 conf_size = info->info.size; 856 } else if (conf_size == 0) { 857 conf_size = info->info.size; 858 } 859 860 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 861 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 862 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 863 writel(reg, ®s->config); 864 865 writel(0, ®s->test_init_val); 866 writel(0x80000001, ®s->test_addr); 867 writel(0x221, ®s->ecc_test_ctrl); 868 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 869 ; 870 writel(0, ®s->ecc_test_ctrl); 871 writel(BIT(31), ®s->intr_ctrl); 872 writel(0, ®s->intr_ctrl); 873 } 874 #endif 875 876 static int ast2600_sdrammc_probe(struct udevice *dev) 877 { 878 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 879 struct ast2600_sdrammc_regs *regs = priv->regs; 880 struct udevice *clk_dev; 881 int ret; 882 volatile uint32_t reg; 883 884 /* find SCU base address from clock device */ 885 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 886 &clk_dev); 887 if (ret) { 888 debug("clock device not defined\n"); 889 return ret; 890 } 891 892 priv->scu = devfdt_get_addr_ptr(clk_dev); 893 if (IS_ERR(priv->scu)) { 894 debug("%s(): can't get SCU\n", __func__); 895 return PTR_ERR(priv->scu); 896 } 897 898 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 899 printf("already initialized, "); 900 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 901 ast2600_sdrammc_update_size(priv); 902 return 0; 903 } 904 905 #ifdef AST2600_SDRAMMC_MANUAL_CLK 906 reg = readl(priv->scu + AST_SCU_MPLL); 907 reg &= ~(BIT(24) | GENMASK(22, 0)); 908 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 909 writel(reg, priv->scu + AST_SCU_MPLL); 910 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 911 udelay(100); 912 reg &= ~(BIT(25) | BIT(23)); 913 writel(reg, priv->scu + AST_SCU_MPLL); 914 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 915 ; 916 #else 917 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 918 if (ret) { 919 debug("DDR:No CLK\n"); 920 return ret; 921 } 922 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 923 #endif 924 925 #if 0 926 /* FIXME: enable the following code if reset-driver is ready */ 927 struct reset_ctl reset_ctl; 928 ret = reset_get_by_index(dev, 0, &reset_ctl); 929 if (ret) { 930 debug("%s(): Failed to get reset signal\n", __func__); 931 return ret; 932 } 933 934 ret = reset_assert(&reset_ctl); 935 if (ret) { 936 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 937 return ret; 938 } 939 #endif 940 941 ast2600_sdrammc_unlock(priv); 942 ast2600_sdrammc_common_init(regs); 943 L_ast2600_sdramphy_train: 944 ast2600_sdrammc_init_ddr4(priv); 945 946 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 947 ast2600_sdrammc_search_read_window(priv); 948 #else 949 /* make sure DDR-PHY is ready before access */ 950 do { 951 reg = readl(priv->phy_status) & BIT(1); 952 } while (reg == 0); 953 #endif 954 955 if (0 != ast2600_sdramphy_check_status(priv)) { 956 printf("DDR4 PHY training fail, retrain\n"); 957 goto L_ast2600_sdramphy_train; 958 } 959 960 ast2600_sdrammc_calc_size(priv); 961 962 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 963 if (0 != ast2600_sdrammc_test(priv)) { 964 printf("%s: DDR4 init fail\n", __func__); 965 return -EINVAL; 966 } 967 #endif 968 969 #ifdef CONFIG_ASPEED_ECC 970 ast2600_sdrammc_ecc_enable(priv); 971 #endif 972 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 973 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 974 ast2600_sdrammc_lock(priv); 975 return 0; 976 } 977 978 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 979 { 980 struct dram_info *priv = dev_get_priv(dev); 981 982 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 983 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 984 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 985 986 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 987 "clock-frequency", 0); 988 if (!priv->clock_rate) { 989 debug("DDR Clock Rate not defined\n"); 990 return -EINVAL; 991 } 992 993 return 0; 994 } 995 996 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 997 { 998 struct dram_info *priv = dev_get_priv(dev); 999 1000 *info = priv->info; 1001 1002 return 0; 1003 } 1004 1005 static struct ram_ops ast2600_sdrammc_ops = { 1006 .get_info = ast2600_sdrammc_get_info, 1007 }; 1008 1009 static const struct udevice_id ast2600_sdrammc_ids[] = { 1010 { .compatible = "aspeed,ast2600-sdrammc" }, 1011 { } 1012 }; 1013 1014 U_BOOT_DRIVER(sdrammc_ast2600) = { 1015 .name = "aspeed_ast2600_sdrammc", 1016 .id = UCLASS_RAM, 1017 .of_match = ast2600_sdrammc_ids, 1018 .ops = &ast2600_sdrammc_ops, 1019 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1020 .probe = ast2600_sdrammc_probe, 1021 .priv_auto_alloc_size = sizeof(struct dram_info), 1022 }; 1023