#
73064edf |
| 20-Feb-2023 |
Jesper Devantier <j.devantier@samsung.com> |
hw/nvme: flexible data placement emulation
Add emulation of TP4146 ("Flexible Data Placement").
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Jesper Devantier <j.devantier@samsung.com
hw/nvme: flexible data placement emulation
Add emulation of TP4146 ("Flexible Data Placement").
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Jesper Devantier <j.devantier@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
e181d3da |
| 20-Feb-2023 |
Gollu Appalanaidu <anaidu.gollu@samsung.com> |
hw/nvme: basic directives support
Add support for the Directive Send and Recv commands and the Identify directive.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Gollu Appalanaidu <ana
hw/nvme: basic directives support
Add support for the Directive Send and Recv commands and the Identify directive.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
771dbc3a |
| 20-Feb-2023 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add basic endurance group support
Add the mandatory Endurance Group identify data structures and log pages.
For now, all namespaces in a subsystem belongs to a single Endurance Group.
Rev
hw/nvme: add basic endurance group support
Add the mandatory Endurance Group identify data structures and log pages.
For now, all namespaces in a subsystem belongs to a single Endurance Group.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
43f76aac |
| 07-Jul-2022 |
Darren Kenny <darren.kenny@oracle.com> |
nvme: Fix misleading macro when mixed with ternary operator
Using the Parfait source code analyser and issue was found in hw/nvme/ctrl.c where the macros NVME_CAP_SET_CMBS and NVME_CAP_SET_PMRS are
nvme: Fix misleading macro when mixed with ternary operator
Using the Parfait source code analyser and issue was found in hw/nvme/ctrl.c where the macros NVME_CAP_SET_CMBS and NVME_CAP_SET_PMRS are called with a ternary operatore in the second parameter, resulting in a potentially unexpected expansion of the form:
x ? a: b & FLAG_TEST
which will result in a different result to:
(x ? a: b) & FLAG_TEST.
The macros should wrap each of the parameters in brackets to ensure the correct result on expansion.
Signed-off-by: Darren Kenny <darren.kenny@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
3f7fe8de |
| 16-Jun-2022 |
Jinhao Fan <fanjinhao21s@ict.ac.cn> |
hw/nvme: Implement shadow doorbell buffer support
Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3) and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13 in N
hw/nvme: Implement shadow doorbell buffer support
Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3) and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13 in NVMe Spec 1.3). For queues created before the Doorbell Buffer Config command, the nvme_dbbuf_config function tries to associate each existing SQ and CQ with its Shadow Doorbel buffer and EventIdx buffer address. Queues created after the Doorbell Buffer Config command will have the doorbell buffers associated with them when they are initialized.
In nvme_process_sq and nvme_post_cqe, proactively check for Shadow Doorbell buffer changes instead of wait for doorbell register changes. This reduces the number of MMIOs.
In nvme_process_db(), update the shadow doorbell buffer value with the doorbell register value if it is the admin queue. This is a hack since hosts like Linux NVMe driver and SPDK do not use shadow doorbell buffer for the admin queue. Copying the doorbell register value to the shadow doorbell buffer allows us to support these hosts as well as spec-compliant hosts that use shadow doorbell buffer for the admin queue.
Signed-off-by: Jinhao Fan <fanjinhao21s@ict.ac.cn> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> [k.jensen: rebased] Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
11871f53 |
| 09-May-2022 |
Łukasz Gieryk <lukasz.gieryk@linux.intel.com> |
hw/nvme: Add support for the Virtualization Management command
With the new command one can: - assign flexible resources (queues, interrupts) to primary and secondary controllers, - toggle the
hw/nvme: Add support for the Virtualization Management command
With the new command one can: - assign flexible resources (queues, interrupts) to primary and secondary controllers, - toggle the online/offline state of given controller.
Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
746d42b1 |
| 09-May-2022 |
Łukasz Gieryk <lukasz.gieryk@linux.intel.com> |
hw/nvme: Initialize capability structures for primary/secondary controllers
With four new properties: - sriov_v{i,q}_flexible, - sriov_max_v{i,q}_per_vf, one can configure the number of available
hw/nvme: Initialize capability structures for primary/secondary controllers
With four new properties: - sriov_v{i,q}_flexible, - sriov_max_v{i,q}_per_vf, one can configure the number of available flexible resources, as well as the limits. The primary and secondary controller capability structures are initialized accordingly.
Since the number of available queues (interrupts) now varies between VF/PF, BAR size calculation is also adjusted.
Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
99f48ae7 |
| 09-May-2022 |
Lukasz Maniak <lukasz.maniak@linux.intel.com> |
hw/nvme: Add support for Secondary Controller List
Introduce handling for Secondary Controller List (Identify command with CNS value of 15h).
Secondary controller ids are unique in the subsystem, h
hw/nvme: Add support for Secondary Controller List
Introduce handling for Secondary Controller List (Identify command with CNS value of 15h).
Secondary controller ids are unique in the subsystem, hence they are reserved by it upon initialization of the primary controller to the number of sriov_max_vfs.
ID reservation requires the addition of an intermediate controller slot state, so the reserved controller has the address 0xFFFF. A secondary controller is in the reserved state when it has no virtual function assigned, but its primary controller is realized. Secondary controller reservations are released to NULL when its primary controller is unregistered.
Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
5e6f963f |
| 09-May-2022 |
Lukasz Maniak <lukasz.maniak@linux.intel.com> |
hw/nvme: Add support for Primary Controller Capabilities
Implementation of Primary Controller Capabilities data structure (Identify command with CNS value of 14h).
Currently, the command returns on
hw/nvme: Add support for Primary Controller Capabilities
Implementation of Primary Controller Capabilities data structure (Identify command with CNS value of 14h).
Currently, the command returns only ID of a primary controller. Handling of remaining fields are added in subsequent patches implementing virtualization enhancements.
Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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Revision tags: v6.2.0 |
|
#
44219b60 |
| 16-Nov-2021 |
Naveen Nagar <naveen.n1@samsung.com> |
hw/nvme: 64-bit pi support
This adds support for one possible new protection information format introduced in TP4068 (and integrated in NVMe 2.0): the 64-bit CRC guard and 48-bit reference tag. This
hw/nvme: 64-bit pi support
This adds support for one possible new protection information format introduced in TP4068 (and integrated in NVMe 2.0): the 64-bit CRC guard and 48-bit reference tag. This version does not support storage tags.
Like the CRC16 support already present, this uses a software implementation of CRC64 (so it is naturally pretty slow). But its good enough for verification purposes.
This may go nicely hand-in-hand with the support that Keith submitted for the Linux kernel[1].
[1]: https://lore.kernel.org/linux-nvme/20220126165214.GA1782352@dhcp-10-100-145-180.wdc.com/T/
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
763c05df |
| 06-Oct-2021 |
Naveen Nagar <naveen.n1@samsung.com> |
hw/nvme: add support for the lbafee hbs feature
Add support for up to 64 LBA formats through the LBAFEE field of the Host Behavior Support feature.
Reviewed-by: Keith Busch <kbusch@kernel.org> Sign
hw/nvme: add support for the lbafee hbs feature
Add support for up to 64 LBA formats through the LBAFEE field of the Host Behavior Support feature.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
d0c0697b |
| 06-Oct-2021 |
Naveen Nagar <naveen.n1@samsung.com> |
hw/nvme: add host behavior support feature
Add support for getting and setting the Host Behavior Support feature.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1
hw/nvme: add host behavior support feature
Add support for getting and setting the Host Behavior Support feature.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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Revision tags: v6.1.0 |
|
#
e321b4cd |
| 04-Mar-2021 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add support for zoned random write area
Add support for TP 4076 ("Zoned Random Write Area"), v2021.08.23 ("Ratified").
This adds three new namespace parameters: "zoned.numzrwa" (number of
hw/nvme: add support for zoned random write area
Add support for TP 4076 ("Zoned Random Write Area"), v2021.08.23 ("Ratified").
This adds three new namespace parameters: "zoned.numzrwa" (number of zrwa resources, i.e. number of zones that can have a zrwa), "zoned.zrwas" (zrwa size in LBAs), "zoned.zrwafg" (granularity in LBAs for flushes).
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
25872031 |
| 22-Nov-2021 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add ozcs enum
Add enumeration for OZCS values.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
|
#
6190d92f |
| 22-Nov-2021 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add struct for zone management send
Add struct for Zone Management Send in preparation for more zone send flags.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k
hw/nvme: add struct for zone management send
Add struct for Zone Management Send in preparation for more zone send flags.
Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
07a3dfa7 |
| 23-Aug-2021 |
Naveen Nagar <naveen.n1@samsung.com> |
hw/nvme: fix verification of select field in namespace attachment
Fix is added to check for reserved value in select field for namespace attachment
CC: Minwoo Im <minwoo.im.dev@gmail.com> Signed-of
hw/nvme: fix verification of select field in namespace attachment
Fix is added to check for reserved value in select field for namespace attachment
CC: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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#
69ea12b1 |
| 28-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-07-27' into staging Miscellaneous patches for 2021-07-27 # gpg: Signature made Tue 27 Jul 2021 16:19:35 BST # gp
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-07-27' into staging Miscellaneous patches for 2021-07-27 # gpg: Signature made Tue 27 Jul 2021 16:19:35 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2021-07-27: vl: Don't continue after -smp help. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
9ae1246a |
| 27-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210727' into staging target-arm queue: * hw/arm/smmuv3: Check 31st bit to see if CD is valid * qemu-options.hx
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210727' into staging target-arm queue: * hw/arm/smmuv3: Check 31st bit to see if CD is valid * qemu-options.hx: Fix formatting of -machine memory-backend option * hw: aspeed_gpio: Fix memory size * hw/arm/nseries: Display hexadecimal value with '0x' prefix * Add sve-default-vector-length cpu property * docs: Update path that mentions deprecated.rst * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts * target/arm: Report M-profile alignment faults correctly to the guest * target/arm: Add missing 'return's after calling v7m_exception_taken() * target/arm: Enforce that M-profile SP low 2 bits are always zero # gpg: Signature made Tue 27 Jul 2021 11:46:17 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210727: hw: aspeed_gpio: Fix memory size hw/arm/nseries: Display hexadecimal value with '0x' prefix target/arm: Add sve-default-vector-length cpu property target/arm: Export aarch64_sve_zcr_get_valid_len target/arm: Correctly bound length in sve_zcr_get_valid_len docs: Update path that mentions deprecated.rst hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts target/arm: Report M-profile alignment faults correctly to the guest target/arm: Add missing 'return's after calling v7m_exception_taken() target/arm: Enforce that M-profile SP low 2 bits are always zero qemu-options.hx: Fix formatting of -machine memory-backend option hw/arm/smmuv3: Check 31st bit to see if CD is valid Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
202abcd3 |
| 27-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging hw/nvme fixes * new PMR test (Gollu Appalanaidu) * pmr/sgl mapping fix (Padmakar Kalghatgi)
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging hw/nvme fixes * new PMR test (Gollu Appalanaidu) * pmr/sgl mapping fix (Padmakar Kalghatgi) * hotplug fixes (me) * mmio out-of-bound read fix (me) * big-endian host fixes (me) # gpg: Signature made Mon 26 Jul 2021 20:18:12 BST # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * remotes/nvme/tags/nvme-next-pull-request: tests/qtest/nvme-test: add mmio read test hw/nvme: fix mmio read hw/nvme: fix out-of-bounds reads hw/nvme: use symbolic names for registers hw/nvme: split pmrmsc register into upper and lower hw/nvme: fix controller hot unplugging tests/qtest/nvme-test: add persistent memory region test hw/nvme: error handling for too many mappings hw/nvme: unregister controller with subsystem at exit hw/nvme: mark nvme-subsys non-hotpluggable hw/nvme: remove NvmeCtrl parameter from ns setup/check functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a316aa50 |
| 13-Jul-2021 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: use symbolic names for registers Add the NvmeBarRegs enum and use these instead of explicit register offsets. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Rev
hw/nvme: use symbolic names for registers Add the NvmeBarRegs enum and use these instead of explicit register offsets. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
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#
5d45edbe |
| 13-Jul-2021 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: split pmrmsc register into upper and lower The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to make up the 64 bit logical PMRMSC register. Make it s
hw/nvme: split pmrmsc register into upper and lower The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to make up the 64 bit logical PMRMSC register. Make it so. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
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#
9516034d |
| 11-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-2' into staging Some qemu updates for IPMI and I2C Move some ADC file to where they belong and move some sensors to
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-2' into staging Some qemu updates for IPMI and I2C Move some ADC file to where they belong and move some sensors to a sensor directory, since with new BMCs coming in lots of different sensors should be coming in. Keep from cluttering things up. Add support for I2C PMBus devices. Replace the confusing and error-prone i2c_send_recv and i2c_transfer with specific send and receive functions. Several errors have already been made with these, avoid any new errors. Fix the watchdog_expired field in the IPMI watchdog, it's not a bool, it's a u8. After a vmstate transfer, the new value could be wrong. # gpg: Signature made Fri 09 Jul 2021 17:25:04 BST # gpg: using RSA key FD0D5CE67CE0F59A6688268661F38C90919BFF81 # gpg: Good signature from "Corey Minyard <cminyard@mvista.com>" [unknown] # gpg: aka "Corey Minyard <minyard@acm.org>" [unknown] # gpg: aka "Corey Minyard <corey@minyard.net>" [unknown] # gpg: aka "Corey Minyard <minyard@mvista.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FD0D 5CE6 7CE0 F59A 6688 2686 61F3 8C90 919B FF81 * remotes/cminyard/tags/for-qemu-6.1-2: (24 commits) tests/qtest: add tests for MAX34451 device model hw/misc: add MAX34451 device tests/qtest: add tests for ADM1272 device model hw/misc: add ADM1272 device hw/i2c: add support for PMBus ipmi/sim: fix watchdog_expired data type error in IPMIBmcSim struct hw/i2c: Introduce i2c_start_recv() and i2c_start_send() hw/i2c: Extract i2c_do_start_transfer() from i2c_start_transfer() hw/i2c: Make i2c_start_transfer() direction argument a boolean hw/i2c: Rename i2c_set_slave_address() -> i2c_slave_set_address() hw/i2c: Remove confusing i2c_send_recv() hw/misc/auxbus: Replace i2c_send_recv() by i2c_recv() & i2c_send() hw/misc/auxbus: Replace 'is_write' boolean by its value hw/misc/auxbus: Explode READ_I2C / WRITE_I2C_MOT cases hw/misc/auxbus: Fix MOT/classic I2C mode hw/i2c/ppc4xx_i2c: Replace i2c_send_recv() by i2c_recv() & i2c_send() hw/i2c/ppc4xx_i2c: Add reference to datasheet hw/display/sm501: Replace i2c_send_recv() by i2c_recv() & i2c_send() hw/display/sm501: Simplify sm501_i2c_write() logic hw/input/lm832x: Define TYPE_LM8323 in public header ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
9c2647f7 |
| 02-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging Block layer patches - Supporting changing 'file' in x-blockdev-reopen - ssh: add support for sha256 h
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging Block layer patches - Supporting changing 'file' in x-blockdev-reopen - ssh: add support for sha256 host key fingerprints - vhost-user-blk: Implement reconnection during realize - introduce QEMU_AUTO_VFREE - Don't require password of encrypted backing file for image creation - Code cleanups # gpg: Signature made Wed 30 Jun 2021 17:00:55 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (24 commits) vhost-user-blk: Implement reconnection during realize vhost-user-blk: Factor out vhost_user_blk_realize_connect() vhost: Distinguish errors in vhost_dev_get_config() vhost-user-blk: Add Error parameter to vhost_user_blk_start() vhost: Return 0/-errno in vhost_dev_init() vhost: Distinguish errors in vhost_backend_init() vhost: Add Error parameter to vhost_dev_init() block/ssh: add support for sha256 host key fingerprints block/commit: use QEMU_AUTO_VFREE introduce QEMU_AUTO_VFREE iotests: Test replacing files with x-blockdev-reopen block: Allow changing bs->file on reopen block: BDRVReopenState: drop replace_backing_bs field block: move supports_backing check to bdrv_set_file_or_backing_noperm() block: bdrv_reopen_parse_backing(): simplify handling implicit filters block: bdrv_reopen_parse_backing(): don't check frozen child block: bdrv_reopen_parse_backing(): don't check aio context block: introduce bdrv_set_file_or_backing_noperm() block: introduce bdrv_remove_file_or_backing_child() block: comment graph-modifying function not updating permissions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
5a67d773 |
| 02-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging Hide build time dependancy on gnutls fom non-crypto code # gpg: Signature made Wed 30
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging Hide build time dependancy on gnutls fom non-crypto code # gpg: Signature made Wed 30 Jun 2021 12:18:47 BST # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange-gitlab/tags/tls-deps-pull-request: crypto: Make QCryptoTLSCreds* structures private ui/vnc: Use qcrypto_tls_creds_check_endpoint() migration/tls: Use qcrypto_tls_creds_check_endpoint() chardev/socket: Use qcrypto_tls_creds_check_endpoint() qemu-nbd: Use qcrypto_tls_creds_check_endpoint() block/nbd: Use qcrypto_tls_creds_check_endpoint() crypto/tlscreds: Introduce qcrypto_tls_creds_check_endpoint() helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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67e25eed |
| 01-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into staging TranslatorOps conversion for target/avr TranslatorOps conversion for target/cris TranslatorOps c
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into staging TranslatorOps conversion for target/avr TranslatorOps conversion for target/cris TranslatorOps conversion for target/nios2 Simple vector operations on TCGv_i32 Host signal fixes for *BSD Improvements to tcg bswap operations # gpg: Signature made Tue 29 Jun 2021 19:51:03 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210629: (63 commits) tcg/riscv: Remove MO_BSWAP handling tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP target/mips: Fix gen_mxu_s32ldd_s32lddr target/sh4: Improve swap.b translation target/i386: Improve bswap translation target/arm: Improve REVSH target/arm: Improve vector REV target/arm: Improve REV32 tcg: Make use of bswap flags in tcg_gen_qemu_st_* tcg: Make use of bswap flags in tcg_gen_qemu_ld_* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 tcg: Handle new bswap flags during optimize tcg/tci: Support bswap flags tcg/mips: Support bswap flags in tcg_out_bswap32 tcg/mips: Support bswap flags in tcg_out_bswap16 tcg/s390: Support bswap flags tcg/ppc: Use power10 byte-reverse instructions tcg/ppc: Support bswap flags tcg/ppc: Split out tcg_out_bswap64 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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