1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint8_t rsvd24[4]; 11 uint32_t csts; 12 uint32_t nssr; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint32_t bpinfo; 19 uint32_t bprsel; 20 uint64_t bpmbl; 21 uint64_t cmbmsc; 22 uint32_t cmbsts; 23 uint8_t rsvd92[3492]; 24 uint32_t pmrcap; 25 uint32_t pmrctl; 26 uint32_t pmrsts; 27 uint32_t pmrebs; 28 uint32_t pmrswtp; 29 uint32_t pmrmscl; 30 uint32_t pmrmscu; 31 uint8_t css[484]; 32 } NvmeBar; 33 34 enum NvmeBarRegs { 35 NVME_REG_CAP = offsetof(NvmeBar, cap), 36 NVME_REG_VS = offsetof(NvmeBar, vs), 37 NVME_REG_INTMS = offsetof(NvmeBar, intms), 38 NVME_REG_INTMC = offsetof(NvmeBar, intmc), 39 NVME_REG_CC = offsetof(NvmeBar, cc), 40 NVME_REG_CSTS = offsetof(NvmeBar, csts), 41 NVME_REG_NSSR = offsetof(NvmeBar, nssr), 42 NVME_REG_AQA = offsetof(NvmeBar, aqa), 43 NVME_REG_ASQ = offsetof(NvmeBar, asq), 44 NVME_REG_ACQ = offsetof(NvmeBar, acq), 45 NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc), 46 NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz), 47 NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo), 48 NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel), 49 NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl), 50 NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc), 51 NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts), 52 NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap), 53 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl), 54 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts), 55 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs), 56 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp), 57 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl), 58 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu), 59 }; 60 61 typedef struct QEMU_PACKED NvmeEndGrpLog { 62 uint8_t critical_warning; 63 uint8_t rsvd[2]; 64 uint8_t avail_spare; 65 uint8_t avail_spare_thres; 66 uint8_t percet_used; 67 uint8_t rsvd1[26]; 68 uint64_t end_estimate[2]; 69 uint64_t data_units_read[2]; 70 uint64_t data_units_written[2]; 71 uint64_t media_units_written[2]; 72 uint64_t host_read_commands[2]; 73 uint64_t host_write_commands[2]; 74 uint64_t media_integrity_errors[2]; 75 uint64_t no_err_info_log_entries[2]; 76 uint8_t rsvd2[352]; 77 } NvmeEndGrpLog; 78 79 enum NvmeCapShift { 80 CAP_MQES_SHIFT = 0, 81 CAP_CQR_SHIFT = 16, 82 CAP_AMS_SHIFT = 17, 83 CAP_TO_SHIFT = 24, 84 CAP_DSTRD_SHIFT = 32, 85 CAP_NSSRS_SHIFT = 36, 86 CAP_CSS_SHIFT = 37, 87 CAP_MPSMIN_SHIFT = 48, 88 CAP_MPSMAX_SHIFT = 52, 89 CAP_PMRS_SHIFT = 56, 90 CAP_CMBS_SHIFT = 57, 91 }; 92 93 enum NvmeCapMask { 94 CAP_MQES_MASK = 0xffff, 95 CAP_CQR_MASK = 0x1, 96 CAP_AMS_MASK = 0x3, 97 CAP_TO_MASK = 0xff, 98 CAP_DSTRD_MASK = 0xf, 99 CAP_NSSRS_MASK = 0x1, 100 CAP_CSS_MASK = 0xff, 101 CAP_MPSMIN_MASK = 0xf, 102 CAP_MPSMAX_MASK = 0xf, 103 CAP_PMRS_MASK = 0x1, 104 CAP_CMBS_MASK = 0x1, 105 }; 106 107 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 108 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 109 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 110 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 111 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 112 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 113 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 114 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 115 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 116 #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 117 #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) 118 119 #define NVME_CAP_SET_MQES(cap, val) \ 120 ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT) 121 #define NVME_CAP_SET_CQR(cap, val) \ 122 ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT) 123 #define NVME_CAP_SET_AMS(cap, val) \ 124 ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT) 125 #define NVME_CAP_SET_TO(cap, val) \ 126 ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT) 127 #define NVME_CAP_SET_DSTRD(cap, val) \ 128 ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT) 129 #define NVME_CAP_SET_NSSRS(cap, val) \ 130 ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT) 131 #define NVME_CAP_SET_CSS(cap, val) \ 132 ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT) 133 #define NVME_CAP_SET_MPSMIN(cap, val) \ 134 ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT) 135 #define NVME_CAP_SET_MPSMAX(cap, val) \ 136 ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT) 137 #define NVME_CAP_SET_PMRS(cap, val) \ 138 ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT) 139 #define NVME_CAP_SET_CMBS(cap, val) \ 140 ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) 141 142 enum NvmeCapCss { 143 NVME_CAP_CSS_NVM = 1 << 0, 144 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 145 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 146 }; 147 148 enum NvmeCcShift { 149 CC_EN_SHIFT = 0, 150 CC_CSS_SHIFT = 4, 151 CC_MPS_SHIFT = 7, 152 CC_AMS_SHIFT = 11, 153 CC_SHN_SHIFT = 14, 154 CC_IOSQES_SHIFT = 16, 155 CC_IOCQES_SHIFT = 20, 156 }; 157 158 enum NvmeCcMask { 159 CC_EN_MASK = 0x1, 160 CC_CSS_MASK = 0x7, 161 CC_MPS_MASK = 0xf, 162 CC_AMS_MASK = 0x7, 163 CC_SHN_MASK = 0x3, 164 CC_IOSQES_MASK = 0xf, 165 CC_IOCQES_MASK = 0xf, 166 }; 167 168 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 169 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 170 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 171 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 172 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 173 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 174 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 175 176 enum NvmeCcCss { 177 NVME_CC_CSS_NVM = 0x0, 178 NVME_CC_CSS_CSI = 0x6, 179 NVME_CC_CSS_ADMIN_ONLY = 0x7, 180 }; 181 182 #define NVME_SET_CC_EN(cc, val) \ 183 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 184 #define NVME_SET_CC_CSS(cc, val) \ 185 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 186 #define NVME_SET_CC_MPS(cc, val) \ 187 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 188 #define NVME_SET_CC_AMS(cc, val) \ 189 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 190 #define NVME_SET_CC_SHN(cc, val) \ 191 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 192 #define NVME_SET_CC_IOSQES(cc, val) \ 193 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 194 #define NVME_SET_CC_IOCQES(cc, val) \ 195 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 196 197 enum NvmeCstsShift { 198 CSTS_RDY_SHIFT = 0, 199 CSTS_CFS_SHIFT = 1, 200 CSTS_SHST_SHIFT = 2, 201 CSTS_NSSRO_SHIFT = 4, 202 }; 203 204 enum NvmeCstsMask { 205 CSTS_RDY_MASK = 0x1, 206 CSTS_CFS_MASK = 0x1, 207 CSTS_SHST_MASK = 0x3, 208 CSTS_NSSRO_MASK = 0x1, 209 }; 210 211 enum NvmeCsts { 212 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 213 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 214 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 215 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 216 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 217 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 218 }; 219 220 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 221 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 222 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 223 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 224 225 enum NvmeAqaShift { 226 AQA_ASQS_SHIFT = 0, 227 AQA_ACQS_SHIFT = 16, 228 }; 229 230 enum NvmeAqaMask { 231 AQA_ASQS_MASK = 0xfff, 232 AQA_ACQS_MASK = 0xfff, 233 }; 234 235 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 236 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 237 238 enum NvmeCmblocShift { 239 CMBLOC_BIR_SHIFT = 0, 240 CMBLOC_CQMMS_SHIFT = 3, 241 CMBLOC_CQPDS_SHIFT = 4, 242 CMBLOC_CDPMLS_SHIFT = 5, 243 CMBLOC_CDPCILS_SHIFT = 6, 244 CMBLOC_CDMMMS_SHIFT = 7, 245 CMBLOC_CQDA_SHIFT = 8, 246 CMBLOC_OFST_SHIFT = 12, 247 }; 248 249 enum NvmeCmblocMask { 250 CMBLOC_BIR_MASK = 0x7, 251 CMBLOC_CQMMS_MASK = 0x1, 252 CMBLOC_CQPDS_MASK = 0x1, 253 CMBLOC_CDPMLS_MASK = 0x1, 254 CMBLOC_CDPCILS_MASK = 0x1, 255 CMBLOC_CDMMMS_MASK = 0x1, 256 CMBLOC_CQDA_MASK = 0x1, 257 CMBLOC_OFST_MASK = 0xfffff, 258 }; 259 260 #define NVME_CMBLOC_BIR(cmbloc) \ 261 ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) 262 #define NVME_CMBLOC_CQMMS(cmbloc) \ 263 ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) 264 #define NVME_CMBLOC_CQPDS(cmbloc) \ 265 ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) 266 #define NVME_CMBLOC_CDPMLS(cmbloc) \ 267 ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) 268 #define NVME_CMBLOC_CDPCILS(cmbloc) \ 269 ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) 270 #define NVME_CMBLOC_CDMMMS(cmbloc) \ 271 ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) 272 #define NVME_CMBLOC_CQDA(cmbloc) \ 273 ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) 274 #define NVME_CMBLOC_OFST(cmbloc) \ 275 ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) 276 277 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 278 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 279 #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ 280 (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) 281 #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ 282 (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) 283 #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ 284 (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) 285 #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ 286 (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) 287 #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ 288 (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) 289 #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ 290 (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) 291 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 292 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 293 294 #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ 295 (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) 296 297 enum NvmeCmbszShift { 298 CMBSZ_SQS_SHIFT = 0, 299 CMBSZ_CQS_SHIFT = 1, 300 CMBSZ_LISTS_SHIFT = 2, 301 CMBSZ_RDS_SHIFT = 3, 302 CMBSZ_WDS_SHIFT = 4, 303 CMBSZ_SZU_SHIFT = 8, 304 CMBSZ_SZ_SHIFT = 12, 305 }; 306 307 enum NvmeCmbszMask { 308 CMBSZ_SQS_MASK = 0x1, 309 CMBSZ_CQS_MASK = 0x1, 310 CMBSZ_LISTS_MASK = 0x1, 311 CMBSZ_RDS_MASK = 0x1, 312 CMBSZ_WDS_MASK = 0x1, 313 CMBSZ_SZU_MASK = 0xf, 314 CMBSZ_SZ_MASK = 0xfffff, 315 }; 316 317 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 318 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 319 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 320 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 321 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 322 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 323 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 324 325 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 326 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 327 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 328 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 329 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 330 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 331 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 332 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 333 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 334 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 335 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 336 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 337 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 338 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 339 340 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 341 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 342 343 enum NvmeCmbmscShift { 344 CMBMSC_CRE_SHIFT = 0, 345 CMBMSC_CMSE_SHIFT = 1, 346 CMBMSC_CBA_SHIFT = 12, 347 }; 348 349 enum NvmeCmbmscMask { 350 CMBMSC_CRE_MASK = 0x1, 351 CMBMSC_CMSE_MASK = 0x1, 352 CMBMSC_CBA_MASK = ((1ULL << 52) - 1), 353 }; 354 355 #define NVME_CMBMSC_CRE(cmbmsc) \ 356 ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) 357 #define NVME_CMBMSC_CMSE(cmbmsc) \ 358 ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) 359 #define NVME_CMBMSC_CBA(cmbmsc) \ 360 ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) 361 362 363 #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ 364 (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) 365 #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ 366 (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) 367 #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ 368 (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) 369 370 enum NvmeCmbstsShift { 371 CMBSTS_CBAI_SHIFT = 0, 372 }; 373 enum NvmeCmbstsMask { 374 CMBSTS_CBAI_MASK = 0x1, 375 }; 376 377 #define NVME_CMBSTS_CBAI(cmbsts) \ 378 ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) 379 380 #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ 381 (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) 382 383 enum NvmePmrcapShift { 384 PMRCAP_RDS_SHIFT = 3, 385 PMRCAP_WDS_SHIFT = 4, 386 PMRCAP_BIR_SHIFT = 5, 387 PMRCAP_PMRTU_SHIFT = 8, 388 PMRCAP_PMRWBM_SHIFT = 10, 389 PMRCAP_PMRTO_SHIFT = 16, 390 PMRCAP_CMSS_SHIFT = 24, 391 }; 392 393 enum NvmePmrcapMask { 394 PMRCAP_RDS_MASK = 0x1, 395 PMRCAP_WDS_MASK = 0x1, 396 PMRCAP_BIR_MASK = 0x7, 397 PMRCAP_PMRTU_MASK = 0x3, 398 PMRCAP_PMRWBM_MASK = 0xf, 399 PMRCAP_PMRTO_MASK = 0xff, 400 PMRCAP_CMSS_MASK = 0x1, 401 }; 402 403 #define NVME_PMRCAP_RDS(pmrcap) \ 404 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 405 #define NVME_PMRCAP_WDS(pmrcap) \ 406 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 407 #define NVME_PMRCAP_BIR(pmrcap) \ 408 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 409 #define NVME_PMRCAP_PMRTU(pmrcap) \ 410 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 411 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 412 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 413 #define NVME_PMRCAP_PMRTO(pmrcap) \ 414 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 415 #define NVME_PMRCAP_CMSS(pmrcap) \ 416 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 417 418 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 419 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 420 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 421 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 422 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 423 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 424 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 425 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 426 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 427 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 428 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 429 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 430 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 431 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 432 433 enum NvmePmrctlShift { 434 PMRCTL_EN_SHIFT = 0, 435 }; 436 437 enum NvmePmrctlMask { 438 PMRCTL_EN_MASK = 0x1, 439 }; 440 441 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 442 443 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 444 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 445 446 enum NvmePmrstsShift { 447 PMRSTS_ERR_SHIFT = 0, 448 PMRSTS_NRDY_SHIFT = 8, 449 PMRSTS_HSTS_SHIFT = 9, 450 PMRSTS_CBAI_SHIFT = 12, 451 }; 452 453 enum NvmePmrstsMask { 454 PMRSTS_ERR_MASK = 0xff, 455 PMRSTS_NRDY_MASK = 0x1, 456 PMRSTS_HSTS_MASK = 0x7, 457 PMRSTS_CBAI_MASK = 0x1, 458 }; 459 460 #define NVME_PMRSTS_ERR(pmrsts) \ 461 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 462 #define NVME_PMRSTS_NRDY(pmrsts) \ 463 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 464 #define NVME_PMRSTS_HSTS(pmrsts) \ 465 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 466 #define NVME_PMRSTS_CBAI(pmrsts) \ 467 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 468 469 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 470 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 471 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 472 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 473 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 474 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 475 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 476 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 477 478 enum NvmePmrebsShift { 479 PMREBS_PMRSZU_SHIFT = 0, 480 PMREBS_RBB_SHIFT = 4, 481 PMREBS_PMRWBZ_SHIFT = 8, 482 }; 483 484 enum NvmePmrebsMask { 485 PMREBS_PMRSZU_MASK = 0xf, 486 PMREBS_RBB_MASK = 0x1, 487 PMREBS_PMRWBZ_MASK = 0xffffff, 488 }; 489 490 #define NVME_PMREBS_PMRSZU(pmrebs) \ 491 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 492 #define NVME_PMREBS_RBB(pmrebs) \ 493 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 494 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 495 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 496 497 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 498 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 499 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 500 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 501 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 502 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 503 504 enum NvmePmrswtpShift { 505 PMRSWTP_PMRSWTU_SHIFT = 0, 506 PMRSWTP_PMRSWTV_SHIFT = 8, 507 }; 508 509 enum NvmePmrswtpMask { 510 PMRSWTP_PMRSWTU_MASK = 0xf, 511 PMRSWTP_PMRSWTV_MASK = 0xffffff, 512 }; 513 514 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 515 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 516 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 517 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 518 519 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 520 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 521 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 522 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 523 524 enum NvmePmrmsclShift { 525 PMRMSCL_CMSE_SHIFT = 1, 526 PMRMSCL_CBA_SHIFT = 12, 527 }; 528 529 enum NvmePmrmsclMask { 530 PMRMSCL_CMSE_MASK = 0x1, 531 PMRMSCL_CBA_MASK = 0xfffff, 532 }; 533 534 #define NVME_PMRMSCL_CMSE(pmrmscl) \ 535 ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) 536 #define NVME_PMRMSCL_CBA(pmrmscl) \ 537 ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) 538 539 #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ 540 (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) 541 #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ 542 (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) 543 544 enum NvmeSglDescriptorType { 545 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 546 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 547 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 548 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 549 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 550 551 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 552 }; 553 554 enum NvmeSglDescriptorSubtype { 555 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 556 }; 557 558 typedef struct QEMU_PACKED NvmeSglDescriptor { 559 uint64_t addr; 560 uint32_t len; 561 uint8_t rsvd[3]; 562 uint8_t type; 563 } NvmeSglDescriptor; 564 565 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 566 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 567 568 typedef union NvmeCmdDptr { 569 struct { 570 uint64_t prp1; 571 uint64_t prp2; 572 }; 573 574 NvmeSglDescriptor sgl; 575 } NvmeCmdDptr; 576 577 enum NvmePsdt { 578 NVME_PSDT_PRP = 0x0, 579 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 580 NVME_PSDT_SGL_MPTR_SGL = 0x2, 581 }; 582 583 typedef struct QEMU_PACKED NvmeCmd { 584 uint8_t opcode; 585 uint8_t flags; 586 uint16_t cid; 587 uint32_t nsid; 588 uint64_t res1; 589 uint64_t mptr; 590 NvmeCmdDptr dptr; 591 uint32_t cdw10; 592 uint32_t cdw11; 593 uint32_t cdw12; 594 uint32_t cdw13; 595 uint32_t cdw14; 596 uint32_t cdw15; 597 } NvmeCmd; 598 599 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 600 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 601 602 enum NvmeAdminCommands { 603 NVME_ADM_CMD_DELETE_SQ = 0x00, 604 NVME_ADM_CMD_CREATE_SQ = 0x01, 605 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 606 NVME_ADM_CMD_DELETE_CQ = 0x04, 607 NVME_ADM_CMD_CREATE_CQ = 0x05, 608 NVME_ADM_CMD_IDENTIFY = 0x06, 609 NVME_ADM_CMD_ABORT = 0x08, 610 NVME_ADM_CMD_SET_FEATURES = 0x09, 611 NVME_ADM_CMD_GET_FEATURES = 0x0a, 612 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 613 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 614 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 615 NVME_ADM_CMD_NS_ATTACHMENT = 0x15, 616 NVME_ADM_CMD_VIRT_MNGMT = 0x1c, 617 NVME_ADM_CMD_DBBUF_CONFIG = 0x7c, 618 NVME_ADM_CMD_FORMAT_NVM = 0x80, 619 NVME_ADM_CMD_SECURITY_SEND = 0x81, 620 NVME_ADM_CMD_SECURITY_RECV = 0x82, 621 }; 622 623 enum NvmeIoCommands { 624 NVME_CMD_FLUSH = 0x00, 625 NVME_CMD_WRITE = 0x01, 626 NVME_CMD_READ = 0x02, 627 NVME_CMD_WRITE_UNCOR = 0x04, 628 NVME_CMD_COMPARE = 0x05, 629 NVME_CMD_WRITE_ZEROES = 0x08, 630 NVME_CMD_DSM = 0x09, 631 NVME_CMD_VERIFY = 0x0c, 632 NVME_CMD_COPY = 0x19, 633 NVME_CMD_ZONE_MGMT_SEND = 0x79, 634 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 635 NVME_CMD_ZONE_APPEND = 0x7d, 636 }; 637 638 typedef struct QEMU_PACKED NvmeDeleteQ { 639 uint8_t opcode; 640 uint8_t flags; 641 uint16_t cid; 642 uint32_t rsvd1[9]; 643 uint16_t qid; 644 uint16_t rsvd10; 645 uint32_t rsvd11[5]; 646 } NvmeDeleteQ; 647 648 typedef struct QEMU_PACKED NvmeCreateCq { 649 uint8_t opcode; 650 uint8_t flags; 651 uint16_t cid; 652 uint32_t rsvd1[5]; 653 uint64_t prp1; 654 uint64_t rsvd8; 655 uint16_t cqid; 656 uint16_t qsize; 657 uint16_t cq_flags; 658 uint16_t irq_vector; 659 uint32_t rsvd12[4]; 660 } NvmeCreateCq; 661 662 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 663 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 664 665 enum NvmeFlagsCq { 666 NVME_CQ_PC = 1, 667 NVME_CQ_IEN = 2, 668 }; 669 670 typedef struct QEMU_PACKED NvmeCreateSq { 671 uint8_t opcode; 672 uint8_t flags; 673 uint16_t cid; 674 uint32_t rsvd1[5]; 675 uint64_t prp1; 676 uint64_t rsvd8; 677 uint16_t sqid; 678 uint16_t qsize; 679 uint16_t sq_flags; 680 uint16_t cqid; 681 uint32_t rsvd12[4]; 682 } NvmeCreateSq; 683 684 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 685 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 686 687 enum NvmeFlagsSq { 688 NVME_SQ_PC = 1, 689 690 NVME_SQ_PRIO_URGENT = 0, 691 NVME_SQ_PRIO_HIGH = 1, 692 NVME_SQ_PRIO_NORMAL = 2, 693 NVME_SQ_PRIO_LOW = 3, 694 }; 695 696 typedef struct QEMU_PACKED NvmeIdentify { 697 uint8_t opcode; 698 uint8_t flags; 699 uint16_t cid; 700 uint32_t nsid; 701 uint64_t rsvd2[2]; 702 uint64_t prp1; 703 uint64_t prp2; 704 uint8_t cns; 705 uint8_t rsvd10; 706 uint16_t ctrlid; 707 uint16_t nvmsetid; 708 uint8_t rsvd11; 709 uint8_t csi; 710 uint32_t rsvd12[4]; 711 } NvmeIdentify; 712 713 typedef struct QEMU_PACKED NvmeRwCmd { 714 uint8_t opcode; 715 uint8_t flags; 716 uint16_t cid; 717 uint32_t nsid; 718 uint32_t cdw2; 719 uint32_t cdw3; 720 uint64_t mptr; 721 NvmeCmdDptr dptr; 722 uint64_t slba; 723 uint16_t nlb; 724 uint16_t control; 725 uint32_t dsmgmt; 726 uint32_t reftag; 727 uint16_t apptag; 728 uint16_t appmask; 729 } NvmeRwCmd; 730 731 enum { 732 NVME_RW_LR = 1 << 15, 733 NVME_RW_FUA = 1 << 14, 734 NVME_RW_DSM_FREQ_UNSPEC = 0, 735 NVME_RW_DSM_FREQ_TYPICAL = 1, 736 NVME_RW_DSM_FREQ_RARE = 2, 737 NVME_RW_DSM_FREQ_READS = 3, 738 NVME_RW_DSM_FREQ_WRITES = 4, 739 NVME_RW_DSM_FREQ_RW = 5, 740 NVME_RW_DSM_FREQ_ONCE = 6, 741 NVME_RW_DSM_FREQ_PREFETCH = 7, 742 NVME_RW_DSM_FREQ_TEMP = 8, 743 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 744 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 745 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 746 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 747 NVME_RW_DSM_SEQ_REQ = 1 << 6, 748 NVME_RW_DSM_COMPRESSED = 1 << 7, 749 NVME_RW_PIREMAP = 1 << 9, 750 NVME_RW_PRINFO_PRACT = 1 << 13, 751 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 752 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 753 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 754 NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, 755 }; 756 757 #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) 758 759 enum { 760 NVME_PRINFO_PRACT = 1 << 3, 761 NVME_PRINFO_PRCHK_GUARD = 1 << 2, 762 NVME_PRINFO_PRCHK_APP = 1 << 1, 763 NVME_PRINFO_PRCHK_REF = 1 << 0, 764 NVME_PRINFO_PRCHK_MASK = 7 << 0, 765 }; 766 767 typedef struct QEMU_PACKED NvmeDsmCmd { 768 uint8_t opcode; 769 uint8_t flags; 770 uint16_t cid; 771 uint32_t nsid; 772 uint64_t rsvd2[2]; 773 NvmeCmdDptr dptr; 774 uint32_t nr; 775 uint32_t attributes; 776 uint32_t rsvd12[4]; 777 } NvmeDsmCmd; 778 779 enum { 780 NVME_DSMGMT_IDR = 1 << 0, 781 NVME_DSMGMT_IDW = 1 << 1, 782 NVME_DSMGMT_AD = 1 << 2, 783 }; 784 785 typedef struct QEMU_PACKED NvmeDsmRange { 786 uint32_t cattr; 787 uint32_t nlb; 788 uint64_t slba; 789 } NvmeDsmRange; 790 791 enum { 792 NVME_COPY_FORMAT_0 = 0x0, 793 NVME_COPY_FORMAT_1 = 0x1, 794 }; 795 796 typedef struct QEMU_PACKED NvmeCopyCmd { 797 uint8_t opcode; 798 uint8_t flags; 799 uint16_t cid; 800 uint32_t nsid; 801 uint32_t cdw2; 802 uint32_t cdw3; 803 uint32_t rsvd2[2]; 804 NvmeCmdDptr dptr; 805 uint64_t sdlba; 806 uint8_t nr; 807 uint8_t control[3]; 808 uint16_t rsvd13; 809 uint16_t dspec; 810 uint32_t reftag; 811 uint16_t apptag; 812 uint16_t appmask; 813 } NvmeCopyCmd; 814 815 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0 { 816 uint8_t rsvd0[8]; 817 uint64_t slba; 818 uint16_t nlb; 819 uint8_t rsvd18[6]; 820 uint32_t reftag; 821 uint16_t apptag; 822 uint16_t appmask; 823 } NvmeCopySourceRangeFormat0; 824 825 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1 { 826 uint8_t rsvd0[8]; 827 uint64_t slba; 828 uint16_t nlb; 829 uint8_t rsvd18[8]; 830 uint8_t sr[10]; 831 uint16_t apptag; 832 uint16_t appmask; 833 } NvmeCopySourceRangeFormat1; 834 835 enum NvmeAsyncEventRequest { 836 NVME_AER_TYPE_ERROR = 0, 837 NVME_AER_TYPE_SMART = 1, 838 NVME_AER_TYPE_NOTICE = 2, 839 NVME_AER_TYPE_IO_SPECIFIC = 6, 840 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 841 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 842 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 843 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 844 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 845 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 846 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 847 NVME_AER_INFO_SMART_RELIABILITY = 0, 848 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 849 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 850 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, 851 }; 852 853 typedef struct QEMU_PACKED NvmeAerResult { 854 uint8_t event_type; 855 uint8_t event_info; 856 uint8_t log_page; 857 uint8_t resv; 858 } NvmeAerResult; 859 860 typedef struct QEMU_PACKED NvmeZonedResult { 861 uint64_t slba; 862 } NvmeZonedResult; 863 864 typedef struct QEMU_PACKED NvmeCqe { 865 uint32_t result; 866 uint32_t dw1; 867 uint16_t sq_head; 868 uint16_t sq_id; 869 uint16_t cid; 870 uint16_t status; 871 } NvmeCqe; 872 873 enum NvmeStatusCodes { 874 NVME_SUCCESS = 0x0000, 875 NVME_INVALID_OPCODE = 0x0001, 876 NVME_INVALID_FIELD = 0x0002, 877 NVME_CID_CONFLICT = 0x0003, 878 NVME_DATA_TRAS_ERROR = 0x0004, 879 NVME_POWER_LOSS_ABORT = 0x0005, 880 NVME_INTERNAL_DEV_ERROR = 0x0006, 881 NVME_CMD_ABORT_REQ = 0x0007, 882 NVME_CMD_ABORT_SQ_DEL = 0x0008, 883 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 884 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 885 NVME_INVALID_NSID = 0x000b, 886 NVME_CMD_SEQ_ERROR = 0x000c, 887 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 888 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 889 NVME_DATA_SGL_LEN_INVALID = 0x000f, 890 NVME_MD_SGL_LEN_INVALID = 0x0010, 891 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 892 NVME_INVALID_USE_OF_CMB = 0x0012, 893 NVME_INVALID_PRP_OFFSET = 0x0013, 894 NVME_CMD_SET_CMB_REJECTED = 0x002b, 895 NVME_INVALID_CMD_SET = 0x002c, 896 NVME_LBA_RANGE = 0x0080, 897 NVME_CAP_EXCEEDED = 0x0081, 898 NVME_NS_NOT_READY = 0x0082, 899 NVME_NS_RESV_CONFLICT = 0x0083, 900 NVME_FORMAT_IN_PROGRESS = 0x0084, 901 NVME_INVALID_CQID = 0x0100, 902 NVME_INVALID_QID = 0x0101, 903 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 904 NVME_ACL_EXCEEDED = 0x0103, 905 NVME_RESERVED = 0x0104, 906 NVME_AER_LIMIT_EXCEEDED = 0x0105, 907 NVME_INVALID_FW_SLOT = 0x0106, 908 NVME_INVALID_FW_IMAGE = 0x0107, 909 NVME_INVALID_IRQ_VECTOR = 0x0108, 910 NVME_INVALID_LOG_ID = 0x0109, 911 NVME_INVALID_FORMAT = 0x010a, 912 NVME_FW_REQ_RESET = 0x010b, 913 NVME_INVALID_QUEUE_DEL = 0x010c, 914 NVME_FID_NOT_SAVEABLE = 0x010d, 915 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 916 NVME_FEAT_NOT_NS_SPEC = 0x010f, 917 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 918 NVME_NS_ALREADY_ATTACHED = 0x0118, 919 NVME_NS_PRIVATE = 0x0119, 920 NVME_NS_NOT_ATTACHED = 0x011a, 921 NVME_NS_CTRL_LIST_INVALID = 0x011c, 922 NVME_INVALID_CTRL_ID = 0x011f, 923 NVME_INVALID_SEC_CTRL_STATE = 0x0120, 924 NVME_INVALID_NUM_RESOURCES = 0x0121, 925 NVME_INVALID_RESOURCE_ID = 0x0122, 926 NVME_CONFLICTING_ATTRS = 0x0180, 927 NVME_INVALID_PROT_INFO = 0x0181, 928 NVME_WRITE_TO_RO = 0x0182, 929 NVME_CMD_SIZE_LIMIT = 0x0183, 930 NVME_INVALID_ZONE_OP = 0x01b6, 931 NVME_NOZRWA = 0x01b7, 932 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 933 NVME_ZONE_FULL = 0x01b9, 934 NVME_ZONE_READ_ONLY = 0x01ba, 935 NVME_ZONE_OFFLINE = 0x01bb, 936 NVME_ZONE_INVALID_WRITE = 0x01bc, 937 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 938 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 939 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 940 NVME_WRITE_FAULT = 0x0280, 941 NVME_UNRECOVERED_READ = 0x0281, 942 NVME_E2E_GUARD_ERROR = 0x0282, 943 NVME_E2E_APP_ERROR = 0x0283, 944 NVME_E2E_REF_ERROR = 0x0284, 945 NVME_CMP_FAILURE = 0x0285, 946 NVME_ACCESS_DENIED = 0x0286, 947 NVME_DULB = 0x0287, 948 NVME_E2E_STORAGE_TAG_ERROR = 0x0288, 949 NVME_MORE = 0x2000, 950 NVME_DNR = 0x4000, 951 NVME_NO_COMPLETE = 0xffff, 952 }; 953 954 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 955 uint8_t afi; 956 uint8_t reserved1[7]; 957 uint8_t frs1[8]; 958 uint8_t frs2[8]; 959 uint8_t frs3[8]; 960 uint8_t frs4[8]; 961 uint8_t frs5[8]; 962 uint8_t frs6[8]; 963 uint8_t frs7[8]; 964 uint8_t reserved2[448]; 965 } NvmeFwSlotInfoLog; 966 967 typedef struct QEMU_PACKED NvmeErrorLog { 968 uint64_t error_count; 969 uint16_t sqid; 970 uint16_t cid; 971 uint16_t status_field; 972 uint16_t param_error_location; 973 uint64_t lba; 974 uint32_t nsid; 975 uint8_t vs; 976 uint8_t resv[35]; 977 } NvmeErrorLog; 978 979 typedef struct QEMU_PACKED NvmeSmartLog { 980 uint8_t critical_warning; 981 uint16_t temperature; 982 uint8_t available_spare; 983 uint8_t available_spare_threshold; 984 uint8_t percentage_used; 985 uint8_t reserved1[26]; 986 uint64_t data_units_read[2]; 987 uint64_t data_units_written[2]; 988 uint64_t host_read_commands[2]; 989 uint64_t host_write_commands[2]; 990 uint64_t controller_busy_time[2]; 991 uint64_t power_cycles[2]; 992 uint64_t power_on_hours[2]; 993 uint64_t unsafe_shutdowns[2]; 994 uint64_t media_errors[2]; 995 uint64_t number_of_error_log_entries[2]; 996 uint8_t reserved2[320]; 997 } NvmeSmartLog; 998 999 #define NVME_SMART_WARN_MAX 6 1000 enum NvmeSmartWarn { 1001 NVME_SMART_SPARE = 1 << 0, 1002 NVME_SMART_TEMPERATURE = 1 << 1, 1003 NVME_SMART_RELIABILITY = 1 << 2, 1004 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 1005 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 1006 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 1007 }; 1008 1009 typedef struct NvmeEffectsLog { 1010 uint32_t acs[256]; 1011 uint32_t iocs[256]; 1012 uint8_t resv[2048]; 1013 } NvmeEffectsLog; 1014 1015 enum { 1016 NVME_CMD_EFF_CSUPP = 1 << 0, 1017 NVME_CMD_EFF_LBCC = 1 << 1, 1018 NVME_CMD_EFF_NCC = 1 << 2, 1019 NVME_CMD_EFF_NIC = 1 << 3, 1020 NVME_CMD_EFF_CCC = 1 << 4, 1021 NVME_CMD_EFF_CSE_MASK = 3 << 16, 1022 NVME_CMD_EFF_UUID_SEL = 1 << 19, 1023 }; 1024 1025 enum NvmeLogIdentifier { 1026 NVME_LOG_ERROR_INFO = 0x01, 1027 NVME_LOG_SMART_INFO = 0x02, 1028 NVME_LOG_FW_SLOT_INFO = 0x03, 1029 NVME_LOG_CHANGED_NSLIST = 0x04, 1030 NVME_LOG_CMD_EFFECTS = 0x05, 1031 NVME_LOG_ENDGRP = 0x09, 1032 }; 1033 1034 typedef struct QEMU_PACKED NvmePSD { 1035 uint16_t mp; 1036 uint16_t reserved; 1037 uint32_t enlat; 1038 uint32_t exlat; 1039 uint8_t rrt; 1040 uint8_t rrl; 1041 uint8_t rwt; 1042 uint8_t rwl; 1043 uint8_t resv[16]; 1044 } NvmePSD; 1045 1046 #define NVME_CONTROLLER_LIST_SIZE 2048 1047 #define NVME_IDENTIFY_DATA_SIZE 4096 1048 1049 enum NvmeIdCns { 1050 NVME_ID_CNS_NS = 0x00, 1051 NVME_ID_CNS_CTRL = 0x01, 1052 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 1053 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 1054 NVME_ID_CNS_CS_NS = 0x05, 1055 NVME_ID_CNS_CS_CTRL = 0x06, 1056 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 1057 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 1058 NVME_ID_CNS_NS_PRESENT = 0x11, 1059 NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, 1060 NVME_ID_CNS_CTRL_LIST = 0x13, 1061 NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, 1062 NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, 1063 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 1064 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 1065 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 1066 }; 1067 1068 typedef struct QEMU_PACKED NvmeIdCtrl { 1069 uint16_t vid; 1070 uint16_t ssvid; 1071 uint8_t sn[20]; 1072 uint8_t mn[40]; 1073 uint8_t fr[8]; 1074 uint8_t rab; 1075 uint8_t ieee[3]; 1076 uint8_t cmic; 1077 uint8_t mdts; 1078 uint16_t cntlid; 1079 uint32_t ver; 1080 uint32_t rtd3r; 1081 uint32_t rtd3e; 1082 uint32_t oaes; 1083 uint32_t ctratt; 1084 uint8_t rsvd100[11]; 1085 uint8_t cntrltype; 1086 uint8_t fguid[16]; 1087 uint8_t rsvd128[128]; 1088 uint16_t oacs; 1089 uint8_t acl; 1090 uint8_t aerl; 1091 uint8_t frmw; 1092 uint8_t lpa; 1093 uint8_t elpe; 1094 uint8_t npss; 1095 uint8_t avscc; 1096 uint8_t apsta; 1097 uint16_t wctemp; 1098 uint16_t cctemp; 1099 uint16_t mtfa; 1100 uint32_t hmpre; 1101 uint32_t hmmin; 1102 uint8_t tnvmcap[16]; 1103 uint8_t unvmcap[16]; 1104 uint32_t rpmbs; 1105 uint16_t edstt; 1106 uint8_t dsto; 1107 uint8_t fwug; 1108 uint16_t kas; 1109 uint16_t hctma; 1110 uint16_t mntmt; 1111 uint16_t mxtmt; 1112 uint32_t sanicap; 1113 uint8_t rsvd332[6]; 1114 uint16_t nsetidmax; 1115 uint16_t endgidmax; 1116 uint8_t rsvd342[170]; 1117 uint8_t sqes; 1118 uint8_t cqes; 1119 uint16_t maxcmd; 1120 uint32_t nn; 1121 uint16_t oncs; 1122 uint16_t fuses; 1123 uint8_t fna; 1124 uint8_t vwc; 1125 uint16_t awun; 1126 uint16_t awupf; 1127 uint8_t nvscc; 1128 uint8_t rsvd531; 1129 uint16_t acwu; 1130 uint16_t ocfs; 1131 uint32_t sgls; 1132 uint8_t rsvd540[228]; 1133 uint8_t subnqn[256]; 1134 uint8_t rsvd1024[1024]; 1135 NvmePSD psd[32]; 1136 uint8_t vs[1024]; 1137 } NvmeIdCtrl; 1138 1139 typedef struct NvmeIdCtrlZoned { 1140 uint8_t zasl; 1141 uint8_t rsvd1[4095]; 1142 } NvmeIdCtrlZoned; 1143 1144 typedef struct NvmeIdCtrlNvm { 1145 uint8_t vsl; 1146 uint8_t wzsl; 1147 uint8_t wusl; 1148 uint8_t dmrl; 1149 uint32_t dmrsl; 1150 uint64_t dmsl; 1151 uint8_t rsvd16[4080]; 1152 } NvmeIdCtrlNvm; 1153 1154 enum NvmeIdCtrlOaes { 1155 NVME_OAES_NS_ATTR = 1 << 8, 1156 }; 1157 1158 enum NvmeIdCtrlCtratt { 1159 NVME_CTRATT_ENDGRPS = 1 << 4, 1160 NVME_CTRATT_ELBAS = 1 << 15, 1161 }; 1162 1163 enum NvmeIdCtrlOacs { 1164 NVME_OACS_SECURITY = 1 << 0, 1165 NVME_OACS_FORMAT = 1 << 1, 1166 NVME_OACS_FW = 1 << 2, 1167 NVME_OACS_NS_MGMT = 1 << 3, 1168 NVME_OACS_DBBUF = 1 << 8, 1169 }; 1170 1171 enum NvmeIdCtrlOncs { 1172 NVME_ONCS_COMPARE = 1 << 0, 1173 NVME_ONCS_WRITE_UNCORR = 1 << 1, 1174 NVME_ONCS_DSM = 1 << 2, 1175 NVME_ONCS_WRITE_ZEROES = 1 << 3, 1176 NVME_ONCS_FEATURES = 1 << 4, 1177 NVME_ONCS_RESRVATIONS = 1 << 5, 1178 NVME_ONCS_TIMESTAMP = 1 << 6, 1179 NVME_ONCS_VERIFY = 1 << 7, 1180 NVME_ONCS_COPY = 1 << 8, 1181 }; 1182 1183 enum NvmeIdCtrlOcfs { 1184 NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0, 1185 NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1, 1186 }; 1187 1188 enum NvmeIdctrlVwc { 1189 NVME_VWC_PRESENT = 1 << 0, 1190 NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, 1191 NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, 1192 NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, 1193 NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, 1194 }; 1195 1196 enum NvmeIdCtrlFrmw { 1197 NVME_FRMW_SLOT1_RO = 1 << 0, 1198 }; 1199 1200 enum NvmeIdCtrlLpa { 1201 NVME_LPA_NS_SMART = 1 << 0, 1202 NVME_LPA_CSE = 1 << 1, 1203 NVME_LPA_EXTENDED = 1 << 2, 1204 }; 1205 1206 enum NvmeIdCtrlCmic { 1207 NVME_CMIC_MULTI_CTRL = 1 << 1, 1208 }; 1209 1210 enum NvmeNsAttachmentOperation { 1211 NVME_NS_ATTACHMENT_ATTACH = 0x0, 1212 NVME_NS_ATTACHMENT_DETACH = 0x1, 1213 }; 1214 1215 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 1216 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 1217 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 1218 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 1219 1220 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 1221 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 1222 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 1223 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 1224 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 1225 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 1226 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 1227 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 1228 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 1229 1230 #define NVME_ARB_AB(arb) (arb & 0x7) 1231 #define NVME_ARB_AB_NOLIMIT 0x7 1232 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 1233 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 1234 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 1235 1236 #define NVME_INTC_THR(intc) (intc & 0xff) 1237 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 1238 1239 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 1240 1241 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 1242 #define NVME_TEMP_THSEL_OVER 0x0 1243 #define NVME_TEMP_THSEL_UNDER 0x1 1244 1245 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 1246 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 1247 1248 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 1249 1250 #define NVME_AEC_SMART(aec) (aec & 0xff) 1251 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 1252 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 1253 #define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1) 1254 1255 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 1256 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 1257 1258 enum NvmeFeatureIds { 1259 NVME_ARBITRATION = 0x1, 1260 NVME_POWER_MANAGEMENT = 0x2, 1261 NVME_LBA_RANGE_TYPE = 0x3, 1262 NVME_TEMPERATURE_THRESHOLD = 0x4, 1263 NVME_ERROR_RECOVERY = 0x5, 1264 NVME_VOLATILE_WRITE_CACHE = 0x6, 1265 NVME_NUMBER_OF_QUEUES = 0x7, 1266 NVME_INTERRUPT_COALESCING = 0x8, 1267 NVME_INTERRUPT_VECTOR_CONF = 0x9, 1268 NVME_WRITE_ATOMICITY = 0xa, 1269 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1270 NVME_TIMESTAMP = 0xe, 1271 NVME_HOST_BEHAVIOR_SUPPORT = 0x16, 1272 NVME_COMMAND_SET_PROFILE = 0x19, 1273 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1274 NVME_FID_MAX = 0x100, 1275 }; 1276 1277 typedef enum NvmeFeatureCap { 1278 NVME_FEAT_CAP_SAVE = 1 << 0, 1279 NVME_FEAT_CAP_NS = 1 << 1, 1280 NVME_FEAT_CAP_CHANGE = 1 << 2, 1281 } NvmeFeatureCap; 1282 1283 typedef enum NvmeGetFeatureSelect { 1284 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1285 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1286 NVME_GETFEAT_SELECT_SAVED = 0x2, 1287 NVME_GETFEAT_SELECT_CAP = 0x3, 1288 } NvmeGetFeatureSelect; 1289 1290 #define NVME_GETSETFEAT_FID_MASK 0xff 1291 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1292 1293 #define NVME_GETFEAT_SELECT_SHIFT 8 1294 #define NVME_GETFEAT_SELECT_MASK 0x7 1295 #define NVME_GETFEAT_SELECT(dw10) \ 1296 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1297 1298 #define NVME_SETFEAT_SAVE_SHIFT 31 1299 #define NVME_SETFEAT_SAVE_MASK 0x1 1300 #define NVME_SETFEAT_SAVE(dw10) \ 1301 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1302 1303 typedef struct QEMU_PACKED NvmeRangeType { 1304 uint8_t type; 1305 uint8_t attributes; 1306 uint8_t rsvd2[14]; 1307 uint64_t slba; 1308 uint64_t nlb; 1309 uint8_t guid[16]; 1310 uint8_t rsvd48[16]; 1311 } NvmeRangeType; 1312 1313 typedef struct NvmeHostBehaviorSupport { 1314 uint8_t acre; 1315 uint8_t etdas; 1316 uint8_t lbafee; 1317 uint8_t rsvd3[509]; 1318 } NvmeHostBehaviorSupport; 1319 1320 typedef struct QEMU_PACKED NvmeLBAF { 1321 uint16_t ms; 1322 uint8_t ds; 1323 uint8_t rp; 1324 } NvmeLBAF; 1325 1326 typedef struct QEMU_PACKED NvmeLBAFE { 1327 uint64_t zsze; 1328 uint8_t zdes; 1329 uint8_t rsvd9[7]; 1330 } NvmeLBAFE; 1331 1332 #define NVME_NSID_BROADCAST 0xffffffff 1333 #define NVME_MAX_NLBAF 64 1334 1335 typedef struct QEMU_PACKED NvmeIdNs { 1336 uint64_t nsze; 1337 uint64_t ncap; 1338 uint64_t nuse; 1339 uint8_t nsfeat; 1340 uint8_t nlbaf; 1341 uint8_t flbas; 1342 uint8_t mc; 1343 uint8_t dpc; 1344 uint8_t dps; 1345 uint8_t nmic; 1346 uint8_t rescap; 1347 uint8_t fpi; 1348 uint8_t dlfeat; 1349 uint16_t nawun; 1350 uint16_t nawupf; 1351 uint16_t nacwu; 1352 uint16_t nabsn; 1353 uint16_t nabo; 1354 uint16_t nabspf; 1355 uint16_t noiob; 1356 uint8_t nvmcap[16]; 1357 uint16_t npwg; 1358 uint16_t npwa; 1359 uint16_t npdg; 1360 uint16_t npda; 1361 uint16_t nows; 1362 uint16_t mssrl; 1363 uint32_t mcl; 1364 uint8_t msrc; 1365 uint8_t rsvd81[18]; 1366 uint8_t nsattr; 1367 uint16_t nvmsetid; 1368 uint16_t endgid; 1369 uint8_t nguid[16]; 1370 uint64_t eui64; 1371 NvmeLBAF lbaf[NVME_MAX_NLBAF]; 1372 uint8_t vs[3712]; 1373 } NvmeIdNs; 1374 1375 #define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3) 1376 1377 typedef struct QEMU_PACKED NvmeIdNsNvm { 1378 uint64_t lbstm; 1379 uint8_t pic; 1380 uint8_t rsvd9[3]; 1381 uint32_t elbaf[NVME_MAX_NLBAF]; 1382 uint8_t rsvd268[3828]; 1383 } NvmeIdNsNvm; 1384 1385 typedef struct QEMU_PACKED NvmeIdNsDescr { 1386 uint8_t nidt; 1387 uint8_t nidl; 1388 uint8_t rsvd2[2]; 1389 } NvmeIdNsDescr; 1390 1391 enum NvmeNsIdentifierLength { 1392 NVME_NIDL_EUI64 = 8, 1393 NVME_NIDL_NGUID = 16, 1394 NVME_NIDL_UUID = 16, 1395 NVME_NIDL_CSI = 1, 1396 }; 1397 1398 enum NvmeNsIdentifierType { 1399 NVME_NIDT_EUI64 = 0x01, 1400 NVME_NIDT_NGUID = 0x02, 1401 NVME_NIDT_UUID = 0x03, 1402 NVME_NIDT_CSI = 0x04, 1403 }; 1404 1405 enum NvmeIdNsNmic { 1406 NVME_NMIC_NS_SHARED = 1 << 0, 1407 }; 1408 1409 enum NvmeCsi { 1410 NVME_CSI_NVM = 0x00, 1411 NVME_CSI_ZONED = 0x02, 1412 }; 1413 1414 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1415 1416 typedef struct QEMU_PACKED NvmeIdNsZoned { 1417 uint16_t zoc; 1418 uint16_t ozcs; 1419 uint32_t mar; 1420 uint32_t mor; 1421 uint32_t rrl; 1422 uint32_t frl; 1423 uint8_t rsvd12[24]; 1424 uint32_t numzrwa; 1425 uint16_t zrwafg; 1426 uint16_t zrwas; 1427 uint8_t zrwacap; 1428 uint8_t rsvd53[2763]; 1429 NvmeLBAFE lbafe[16]; 1430 uint8_t rsvd3072[768]; 1431 uint8_t vs[256]; 1432 } NvmeIdNsZoned; 1433 1434 enum NvmeIdNsZonedOzcs { 1435 NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0, 1436 NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1, 1437 }; 1438 1439 enum NvmeIdNsZonedZrwacap { 1440 NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0, 1441 }; 1442 1443 /*Deallocate Logical Block Features*/ 1444 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1445 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1446 1447 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1448 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1449 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1450 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1451 1452 1453 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1454 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1455 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1456 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1457 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1458 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1459 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1460 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1461 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1462 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1463 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1464 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1465 1466 enum NvmeIdNsDps { 1467 NVME_ID_NS_DPS_TYPE_NONE = 0, 1468 NVME_ID_NS_DPS_TYPE_1 = 1, 1469 NVME_ID_NS_DPS_TYPE_2 = 2, 1470 NVME_ID_NS_DPS_TYPE_3 = 3, 1471 NVME_ID_NS_DPS_TYPE_MASK = 0x7, 1472 NVME_ID_NS_DPS_FIRST_EIGHT = 8, 1473 }; 1474 1475 enum NvmeIdNsFlbas { 1476 NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, 1477 }; 1478 1479 enum NvmeIdNsMc { 1480 NVME_ID_NS_MC_EXTENDED = 1 << 0, 1481 NVME_ID_NS_MC_SEPARATE = 1 << 1, 1482 }; 1483 1484 #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) 1485 1486 enum NvmePIFormat { 1487 NVME_PI_GUARD_16 = 0, 1488 NVME_PI_GUARD_64 = 2, 1489 }; 1490 1491 typedef union NvmeDifTuple { 1492 struct { 1493 uint16_t guard; 1494 uint16_t apptag; 1495 uint32_t reftag; 1496 } g16; 1497 1498 struct { 1499 uint64_t guard; 1500 uint16_t apptag; 1501 uint8_t sr[6]; 1502 } g64; 1503 } NvmeDifTuple; 1504 1505 enum NvmeZoneAttr { 1506 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1507 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1508 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1509 NVME_ZA_ZRWA_VALID = 1 << 3, 1510 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1511 }; 1512 1513 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1514 uint64_t nr_zones; 1515 uint8_t rsvd[56]; 1516 } NvmeZoneReportHeader; 1517 1518 enum NvmeZoneReceiveAction { 1519 NVME_ZONE_REPORT = 0, 1520 NVME_ZONE_REPORT_EXTENDED = 1, 1521 }; 1522 1523 enum NvmeZoneReportType { 1524 NVME_ZONE_REPORT_ALL = 0, 1525 NVME_ZONE_REPORT_EMPTY = 1, 1526 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1527 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1528 NVME_ZONE_REPORT_CLOSED = 4, 1529 NVME_ZONE_REPORT_FULL = 5, 1530 NVME_ZONE_REPORT_READ_ONLY = 6, 1531 NVME_ZONE_REPORT_OFFLINE = 7, 1532 }; 1533 1534 enum NvmeZoneType { 1535 NVME_ZONE_TYPE_RESERVED = 0x00, 1536 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1537 }; 1538 1539 typedef struct QEMU_PACKED NvmeZoneSendCmd { 1540 uint8_t opcode; 1541 uint8_t flags; 1542 uint16_t cid; 1543 uint32_t nsid; 1544 uint32_t rsvd8[4]; 1545 NvmeCmdDptr dptr; 1546 uint64_t slba; 1547 uint32_t rsvd48; 1548 uint8_t zsa; 1549 uint8_t zsflags; 1550 uint8_t rsvd54[2]; 1551 uint32_t rsvd56[2]; 1552 } NvmeZoneSendCmd; 1553 1554 enum NvmeZoneSendAction { 1555 NVME_ZONE_ACTION_RSD = 0x00, 1556 NVME_ZONE_ACTION_CLOSE = 0x01, 1557 NVME_ZONE_ACTION_FINISH = 0x02, 1558 NVME_ZONE_ACTION_OPEN = 0x03, 1559 NVME_ZONE_ACTION_RESET = 0x04, 1560 NVME_ZONE_ACTION_OFFLINE = 0x05, 1561 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1562 NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11, 1563 }; 1564 1565 enum { 1566 NVME_ZSFLAG_SELECT_ALL = 1 << 0, 1567 NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1, 1568 }; 1569 1570 typedef struct QEMU_PACKED NvmeZoneDescr { 1571 uint8_t zt; 1572 uint8_t zs; 1573 uint8_t za; 1574 uint8_t rsvd3[5]; 1575 uint64_t zcap; 1576 uint64_t zslba; 1577 uint64_t wp; 1578 uint8_t rsvd32[32]; 1579 } NvmeZoneDescr; 1580 1581 typedef enum NvmeZoneState { 1582 NVME_ZONE_STATE_RESERVED = 0x00, 1583 NVME_ZONE_STATE_EMPTY = 0x01, 1584 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1585 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1586 NVME_ZONE_STATE_CLOSED = 0x04, 1587 NVME_ZONE_STATE_READ_ONLY = 0x0d, 1588 NVME_ZONE_STATE_FULL = 0x0e, 1589 NVME_ZONE_STATE_OFFLINE = 0x0f, 1590 } NvmeZoneState; 1591 1592 typedef struct QEMU_PACKED NvmePriCtrlCap { 1593 uint16_t cntlid; 1594 uint16_t portid; 1595 uint8_t crt; 1596 uint8_t rsvd5[27]; 1597 uint32_t vqfrt; 1598 uint32_t vqrfa; 1599 uint16_t vqrfap; 1600 uint16_t vqprt; 1601 uint16_t vqfrsm; 1602 uint16_t vqgran; 1603 uint8_t rsvd48[16]; 1604 uint32_t vifrt; 1605 uint32_t virfa; 1606 uint16_t virfap; 1607 uint16_t viprt; 1608 uint16_t vifrsm; 1609 uint16_t vigran; 1610 uint8_t rsvd80[4016]; 1611 } NvmePriCtrlCap; 1612 1613 typedef enum NvmePriCtrlCapCrt { 1614 NVME_CRT_VQ = 1 << 0, 1615 NVME_CRT_VI = 1 << 1, 1616 } NvmePriCtrlCapCrt; 1617 1618 typedef struct QEMU_PACKED NvmeSecCtrlEntry { 1619 uint16_t scid; 1620 uint16_t pcid; 1621 uint8_t scs; 1622 uint8_t rsvd5[3]; 1623 uint16_t vfn; 1624 uint16_t nvq; 1625 uint16_t nvi; 1626 uint8_t rsvd14[18]; 1627 } NvmeSecCtrlEntry; 1628 1629 typedef struct QEMU_PACKED NvmeSecCtrlList { 1630 uint8_t numcntl; 1631 uint8_t rsvd1[31]; 1632 NvmeSecCtrlEntry sec[127]; 1633 } NvmeSecCtrlList; 1634 1635 typedef enum NvmeVirtMngmtAction { 1636 NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01, 1637 NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07, 1638 NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08, 1639 NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09, 1640 } NvmeVirtMngmtAction; 1641 1642 typedef enum NvmeVirtualResourceType { 1643 NVME_VIRT_RES_QUEUE = 0x00, 1644 NVME_VIRT_RES_INTERRUPT = 0x01, 1645 } NvmeVirtualResourceType; 1646 1647 static inline void _nvme_check_size(void) 1648 { 1649 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1650 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1651 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1652 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1653 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1654 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0) != 32); 1655 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1) != 40); 1656 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1657 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1658 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1659 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1660 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1661 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1662 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1663 QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); 1664 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1665 QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512); 1666 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1667 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1668 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1669 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1670 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1671 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1672 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); 1673 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1674 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1675 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1676 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096); 1677 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1678 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1679 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1680 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1681 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16); 1682 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096); 1683 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32); 1684 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096); 1685 QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512); 1686 } 1687 #endif 1688