1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint8_t rsvd24[4]; 11 uint32_t csts; 12 uint32_t nssr; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint32_t bpinfo; 19 uint32_t bprsel; 20 uint64_t bpmbl; 21 uint64_t cmbmsc; 22 uint32_t cmbsts; 23 uint8_t rsvd92[3492]; 24 uint32_t pmrcap; 25 uint32_t pmrctl; 26 uint32_t pmrsts; 27 uint32_t pmrebs; 28 uint32_t pmrswtp; 29 uint32_t pmrmscl; 30 uint32_t pmrmscu; 31 uint8_t css[484]; 32 } NvmeBar; 33 34 enum NvmeBarRegs { 35 NVME_REG_CAP = offsetof(NvmeBar, cap), 36 NVME_REG_VS = offsetof(NvmeBar, vs), 37 NVME_REG_INTMS = offsetof(NvmeBar, intms), 38 NVME_REG_INTMC = offsetof(NvmeBar, intmc), 39 NVME_REG_CC = offsetof(NvmeBar, cc), 40 NVME_REG_CSTS = offsetof(NvmeBar, csts), 41 NVME_REG_NSSR = offsetof(NvmeBar, nssr), 42 NVME_REG_AQA = offsetof(NvmeBar, aqa), 43 NVME_REG_ASQ = offsetof(NvmeBar, asq), 44 NVME_REG_ACQ = offsetof(NvmeBar, acq), 45 NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc), 46 NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz), 47 NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo), 48 NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel), 49 NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl), 50 NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc), 51 NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts), 52 NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap), 53 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl), 54 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts), 55 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs), 56 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp), 57 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl), 58 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu), 59 }; 60 61 typedef struct QEMU_PACKED NvmeEndGrpLog { 62 uint8_t critical_warning; 63 uint8_t rsvd[2]; 64 uint8_t avail_spare; 65 uint8_t avail_spare_thres; 66 uint8_t percet_used; 67 uint8_t rsvd1[26]; 68 uint64_t end_estimate[2]; 69 uint64_t data_units_read[2]; 70 uint64_t data_units_written[2]; 71 uint64_t media_units_written[2]; 72 uint64_t host_read_commands[2]; 73 uint64_t host_write_commands[2]; 74 uint64_t media_integrity_errors[2]; 75 uint64_t no_err_info_log_entries[2]; 76 uint8_t rsvd2[352]; 77 } NvmeEndGrpLog; 78 79 enum NvmeCapShift { 80 CAP_MQES_SHIFT = 0, 81 CAP_CQR_SHIFT = 16, 82 CAP_AMS_SHIFT = 17, 83 CAP_TO_SHIFT = 24, 84 CAP_DSTRD_SHIFT = 32, 85 CAP_NSSRS_SHIFT = 36, 86 CAP_CSS_SHIFT = 37, 87 CAP_MPSMIN_SHIFT = 48, 88 CAP_MPSMAX_SHIFT = 52, 89 CAP_PMRS_SHIFT = 56, 90 CAP_CMBS_SHIFT = 57, 91 }; 92 93 enum NvmeCapMask { 94 CAP_MQES_MASK = 0xffff, 95 CAP_CQR_MASK = 0x1, 96 CAP_AMS_MASK = 0x3, 97 CAP_TO_MASK = 0xff, 98 CAP_DSTRD_MASK = 0xf, 99 CAP_NSSRS_MASK = 0x1, 100 CAP_CSS_MASK = 0xff, 101 CAP_MPSMIN_MASK = 0xf, 102 CAP_MPSMAX_MASK = 0xf, 103 CAP_PMRS_MASK = 0x1, 104 CAP_CMBS_MASK = 0x1, 105 }; 106 107 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 108 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 109 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 110 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 111 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 112 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 113 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 114 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 115 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 116 #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 117 #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) 118 119 #define NVME_CAP_SET_MQES(cap, val) \ 120 ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT) 121 #define NVME_CAP_SET_CQR(cap, val) \ 122 ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT) 123 #define NVME_CAP_SET_AMS(cap, val) \ 124 ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT) 125 #define NVME_CAP_SET_TO(cap, val) \ 126 ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT) 127 #define NVME_CAP_SET_DSTRD(cap, val) \ 128 ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT) 129 #define NVME_CAP_SET_NSSRS(cap, val) \ 130 ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT) 131 #define NVME_CAP_SET_CSS(cap, val) \ 132 ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT) 133 #define NVME_CAP_SET_MPSMIN(cap, val) \ 134 ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT) 135 #define NVME_CAP_SET_MPSMAX(cap, val) \ 136 ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT) 137 #define NVME_CAP_SET_PMRS(cap, val) \ 138 ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT) 139 #define NVME_CAP_SET_CMBS(cap, val) \ 140 ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) 141 142 enum NvmeCapCss { 143 NVME_CAP_CSS_NVM = 1 << 0, 144 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 145 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 146 }; 147 148 enum NvmeCcShift { 149 CC_EN_SHIFT = 0, 150 CC_CSS_SHIFT = 4, 151 CC_MPS_SHIFT = 7, 152 CC_AMS_SHIFT = 11, 153 CC_SHN_SHIFT = 14, 154 CC_IOSQES_SHIFT = 16, 155 CC_IOCQES_SHIFT = 20, 156 }; 157 158 enum NvmeCcMask { 159 CC_EN_MASK = 0x1, 160 CC_CSS_MASK = 0x7, 161 CC_MPS_MASK = 0xf, 162 CC_AMS_MASK = 0x7, 163 CC_SHN_MASK = 0x3, 164 CC_IOSQES_MASK = 0xf, 165 CC_IOCQES_MASK = 0xf, 166 }; 167 168 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 169 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 170 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 171 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 172 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 173 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 174 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 175 176 enum NvmeCcCss { 177 NVME_CC_CSS_NVM = 0x0, 178 NVME_CC_CSS_CSI = 0x6, 179 NVME_CC_CSS_ADMIN_ONLY = 0x7, 180 }; 181 182 #define NVME_SET_CC_EN(cc, val) \ 183 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 184 #define NVME_SET_CC_CSS(cc, val) \ 185 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 186 #define NVME_SET_CC_MPS(cc, val) \ 187 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 188 #define NVME_SET_CC_AMS(cc, val) \ 189 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 190 #define NVME_SET_CC_SHN(cc, val) \ 191 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 192 #define NVME_SET_CC_IOSQES(cc, val) \ 193 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 194 #define NVME_SET_CC_IOCQES(cc, val) \ 195 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 196 197 enum NvmeCstsShift { 198 CSTS_RDY_SHIFT = 0, 199 CSTS_CFS_SHIFT = 1, 200 CSTS_SHST_SHIFT = 2, 201 CSTS_NSSRO_SHIFT = 4, 202 }; 203 204 enum NvmeCstsMask { 205 CSTS_RDY_MASK = 0x1, 206 CSTS_CFS_MASK = 0x1, 207 CSTS_SHST_MASK = 0x3, 208 CSTS_NSSRO_MASK = 0x1, 209 }; 210 211 enum NvmeCsts { 212 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 213 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 214 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 215 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 216 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 217 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 218 }; 219 220 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 221 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 222 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 223 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 224 225 enum NvmeAqaShift { 226 AQA_ASQS_SHIFT = 0, 227 AQA_ACQS_SHIFT = 16, 228 }; 229 230 enum NvmeAqaMask { 231 AQA_ASQS_MASK = 0xfff, 232 AQA_ACQS_MASK = 0xfff, 233 }; 234 235 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 236 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 237 238 enum NvmeCmblocShift { 239 CMBLOC_BIR_SHIFT = 0, 240 CMBLOC_CQMMS_SHIFT = 3, 241 CMBLOC_CQPDS_SHIFT = 4, 242 CMBLOC_CDPMLS_SHIFT = 5, 243 CMBLOC_CDPCILS_SHIFT = 6, 244 CMBLOC_CDMMMS_SHIFT = 7, 245 CMBLOC_CQDA_SHIFT = 8, 246 CMBLOC_OFST_SHIFT = 12, 247 }; 248 249 enum NvmeCmblocMask { 250 CMBLOC_BIR_MASK = 0x7, 251 CMBLOC_CQMMS_MASK = 0x1, 252 CMBLOC_CQPDS_MASK = 0x1, 253 CMBLOC_CDPMLS_MASK = 0x1, 254 CMBLOC_CDPCILS_MASK = 0x1, 255 CMBLOC_CDMMMS_MASK = 0x1, 256 CMBLOC_CQDA_MASK = 0x1, 257 CMBLOC_OFST_MASK = 0xfffff, 258 }; 259 260 #define NVME_CMBLOC_BIR(cmbloc) \ 261 ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) 262 #define NVME_CMBLOC_CQMMS(cmbloc) \ 263 ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) 264 #define NVME_CMBLOC_CQPDS(cmbloc) \ 265 ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) 266 #define NVME_CMBLOC_CDPMLS(cmbloc) \ 267 ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) 268 #define NVME_CMBLOC_CDPCILS(cmbloc) \ 269 ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) 270 #define NVME_CMBLOC_CDMMMS(cmbloc) \ 271 ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) 272 #define NVME_CMBLOC_CQDA(cmbloc) \ 273 ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) 274 #define NVME_CMBLOC_OFST(cmbloc) \ 275 ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) 276 277 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 278 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 279 #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ 280 (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) 281 #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ 282 (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) 283 #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ 284 (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) 285 #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ 286 (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) 287 #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ 288 (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) 289 #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ 290 (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) 291 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 292 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 293 294 #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ 295 (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) 296 297 enum NvmeCmbszShift { 298 CMBSZ_SQS_SHIFT = 0, 299 CMBSZ_CQS_SHIFT = 1, 300 CMBSZ_LISTS_SHIFT = 2, 301 CMBSZ_RDS_SHIFT = 3, 302 CMBSZ_WDS_SHIFT = 4, 303 CMBSZ_SZU_SHIFT = 8, 304 CMBSZ_SZ_SHIFT = 12, 305 }; 306 307 enum NvmeCmbszMask { 308 CMBSZ_SQS_MASK = 0x1, 309 CMBSZ_CQS_MASK = 0x1, 310 CMBSZ_LISTS_MASK = 0x1, 311 CMBSZ_RDS_MASK = 0x1, 312 CMBSZ_WDS_MASK = 0x1, 313 CMBSZ_SZU_MASK = 0xf, 314 CMBSZ_SZ_MASK = 0xfffff, 315 }; 316 317 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 318 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 319 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 320 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 321 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 322 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 323 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 324 325 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 326 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 327 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 328 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 329 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 330 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 331 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 332 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 333 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 334 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 335 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 336 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 337 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 338 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 339 340 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 341 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 342 343 enum NvmeCmbmscShift { 344 CMBMSC_CRE_SHIFT = 0, 345 CMBMSC_CMSE_SHIFT = 1, 346 CMBMSC_CBA_SHIFT = 12, 347 }; 348 349 enum NvmeCmbmscMask { 350 CMBMSC_CRE_MASK = 0x1, 351 CMBMSC_CMSE_MASK = 0x1, 352 CMBMSC_CBA_MASK = ((1ULL << 52) - 1), 353 }; 354 355 #define NVME_CMBMSC_CRE(cmbmsc) \ 356 ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) 357 #define NVME_CMBMSC_CMSE(cmbmsc) \ 358 ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) 359 #define NVME_CMBMSC_CBA(cmbmsc) \ 360 ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) 361 362 363 #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ 364 (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) 365 #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ 366 (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) 367 #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ 368 (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) 369 370 enum NvmeCmbstsShift { 371 CMBSTS_CBAI_SHIFT = 0, 372 }; 373 enum NvmeCmbstsMask { 374 CMBSTS_CBAI_MASK = 0x1, 375 }; 376 377 #define NVME_CMBSTS_CBAI(cmbsts) \ 378 ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) 379 380 #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ 381 (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) 382 383 enum NvmePmrcapShift { 384 PMRCAP_RDS_SHIFT = 3, 385 PMRCAP_WDS_SHIFT = 4, 386 PMRCAP_BIR_SHIFT = 5, 387 PMRCAP_PMRTU_SHIFT = 8, 388 PMRCAP_PMRWBM_SHIFT = 10, 389 PMRCAP_PMRTO_SHIFT = 16, 390 PMRCAP_CMSS_SHIFT = 24, 391 }; 392 393 enum NvmePmrcapMask { 394 PMRCAP_RDS_MASK = 0x1, 395 PMRCAP_WDS_MASK = 0x1, 396 PMRCAP_BIR_MASK = 0x7, 397 PMRCAP_PMRTU_MASK = 0x3, 398 PMRCAP_PMRWBM_MASK = 0xf, 399 PMRCAP_PMRTO_MASK = 0xff, 400 PMRCAP_CMSS_MASK = 0x1, 401 }; 402 403 #define NVME_PMRCAP_RDS(pmrcap) \ 404 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 405 #define NVME_PMRCAP_WDS(pmrcap) \ 406 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 407 #define NVME_PMRCAP_BIR(pmrcap) \ 408 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 409 #define NVME_PMRCAP_PMRTU(pmrcap) \ 410 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 411 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 412 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 413 #define NVME_PMRCAP_PMRTO(pmrcap) \ 414 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 415 #define NVME_PMRCAP_CMSS(pmrcap) \ 416 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 417 418 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 419 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 420 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 421 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 422 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 423 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 424 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 425 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 426 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 427 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 428 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 429 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 430 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 431 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 432 433 enum NvmePmrctlShift { 434 PMRCTL_EN_SHIFT = 0, 435 }; 436 437 enum NvmePmrctlMask { 438 PMRCTL_EN_MASK = 0x1, 439 }; 440 441 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 442 443 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 444 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 445 446 enum NvmePmrstsShift { 447 PMRSTS_ERR_SHIFT = 0, 448 PMRSTS_NRDY_SHIFT = 8, 449 PMRSTS_HSTS_SHIFT = 9, 450 PMRSTS_CBAI_SHIFT = 12, 451 }; 452 453 enum NvmePmrstsMask { 454 PMRSTS_ERR_MASK = 0xff, 455 PMRSTS_NRDY_MASK = 0x1, 456 PMRSTS_HSTS_MASK = 0x7, 457 PMRSTS_CBAI_MASK = 0x1, 458 }; 459 460 #define NVME_PMRSTS_ERR(pmrsts) \ 461 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 462 #define NVME_PMRSTS_NRDY(pmrsts) \ 463 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 464 #define NVME_PMRSTS_HSTS(pmrsts) \ 465 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 466 #define NVME_PMRSTS_CBAI(pmrsts) \ 467 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 468 469 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 470 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 471 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 472 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 473 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 474 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 475 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 476 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 477 478 enum NvmePmrebsShift { 479 PMREBS_PMRSZU_SHIFT = 0, 480 PMREBS_RBB_SHIFT = 4, 481 PMREBS_PMRWBZ_SHIFT = 8, 482 }; 483 484 enum NvmePmrebsMask { 485 PMREBS_PMRSZU_MASK = 0xf, 486 PMREBS_RBB_MASK = 0x1, 487 PMREBS_PMRWBZ_MASK = 0xffffff, 488 }; 489 490 #define NVME_PMREBS_PMRSZU(pmrebs) \ 491 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 492 #define NVME_PMREBS_RBB(pmrebs) \ 493 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 494 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 495 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 496 497 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 498 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 499 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 500 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 501 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 502 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 503 504 enum NvmePmrswtpShift { 505 PMRSWTP_PMRSWTU_SHIFT = 0, 506 PMRSWTP_PMRSWTV_SHIFT = 8, 507 }; 508 509 enum NvmePmrswtpMask { 510 PMRSWTP_PMRSWTU_MASK = 0xf, 511 PMRSWTP_PMRSWTV_MASK = 0xffffff, 512 }; 513 514 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 515 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 516 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 517 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 518 519 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 520 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 521 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 522 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 523 524 enum NvmePmrmsclShift { 525 PMRMSCL_CMSE_SHIFT = 1, 526 PMRMSCL_CBA_SHIFT = 12, 527 }; 528 529 enum NvmePmrmsclMask { 530 PMRMSCL_CMSE_MASK = 0x1, 531 PMRMSCL_CBA_MASK = 0xfffff, 532 }; 533 534 #define NVME_PMRMSCL_CMSE(pmrmscl) \ 535 ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) 536 #define NVME_PMRMSCL_CBA(pmrmscl) \ 537 ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) 538 539 #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ 540 (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) 541 #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ 542 (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) 543 544 enum NvmeSglDescriptorType { 545 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 546 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 547 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 548 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 549 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 550 551 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 552 }; 553 554 enum NvmeSglDescriptorSubtype { 555 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 556 }; 557 558 typedef struct QEMU_PACKED NvmeSglDescriptor { 559 uint64_t addr; 560 uint32_t len; 561 uint8_t rsvd[3]; 562 uint8_t type; 563 } NvmeSglDescriptor; 564 565 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 566 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 567 568 typedef union NvmeCmdDptr { 569 struct { 570 uint64_t prp1; 571 uint64_t prp2; 572 }; 573 574 NvmeSglDescriptor sgl; 575 } NvmeCmdDptr; 576 577 enum NvmePsdt { 578 NVME_PSDT_PRP = 0x0, 579 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 580 NVME_PSDT_SGL_MPTR_SGL = 0x2, 581 }; 582 583 typedef struct QEMU_PACKED NvmeCmd { 584 uint8_t opcode; 585 uint8_t flags; 586 uint16_t cid; 587 uint32_t nsid; 588 uint64_t res1; 589 uint64_t mptr; 590 NvmeCmdDptr dptr; 591 uint32_t cdw10; 592 uint32_t cdw11; 593 uint32_t cdw12; 594 uint32_t cdw13; 595 uint32_t cdw14; 596 uint32_t cdw15; 597 } NvmeCmd; 598 599 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 600 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 601 602 enum NvmeAdminCommands { 603 NVME_ADM_CMD_DELETE_SQ = 0x00, 604 NVME_ADM_CMD_CREATE_SQ = 0x01, 605 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 606 NVME_ADM_CMD_DELETE_CQ = 0x04, 607 NVME_ADM_CMD_CREATE_CQ = 0x05, 608 NVME_ADM_CMD_IDENTIFY = 0x06, 609 NVME_ADM_CMD_ABORT = 0x08, 610 NVME_ADM_CMD_SET_FEATURES = 0x09, 611 NVME_ADM_CMD_GET_FEATURES = 0x0a, 612 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 613 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 614 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 615 NVME_ADM_CMD_NS_ATTACHMENT = 0x15, 616 NVME_ADM_CMD_DIRECTIVE_SEND = 0x19, 617 NVME_ADM_CMD_VIRT_MNGMT = 0x1c, 618 NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a, 619 NVME_ADM_CMD_DBBUF_CONFIG = 0x7c, 620 NVME_ADM_CMD_FORMAT_NVM = 0x80, 621 NVME_ADM_CMD_SECURITY_SEND = 0x81, 622 NVME_ADM_CMD_SECURITY_RECV = 0x82, 623 }; 624 625 enum NvmeIoCommands { 626 NVME_CMD_FLUSH = 0x00, 627 NVME_CMD_WRITE = 0x01, 628 NVME_CMD_READ = 0x02, 629 NVME_CMD_WRITE_UNCOR = 0x04, 630 NVME_CMD_COMPARE = 0x05, 631 NVME_CMD_WRITE_ZEROES = 0x08, 632 NVME_CMD_DSM = 0x09, 633 NVME_CMD_VERIFY = 0x0c, 634 NVME_CMD_COPY = 0x19, 635 NVME_CMD_ZONE_MGMT_SEND = 0x79, 636 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 637 NVME_CMD_ZONE_APPEND = 0x7d, 638 }; 639 640 typedef struct QEMU_PACKED NvmeDeleteQ { 641 uint8_t opcode; 642 uint8_t flags; 643 uint16_t cid; 644 uint32_t rsvd1[9]; 645 uint16_t qid; 646 uint16_t rsvd10; 647 uint32_t rsvd11[5]; 648 } NvmeDeleteQ; 649 650 typedef struct QEMU_PACKED NvmeCreateCq { 651 uint8_t opcode; 652 uint8_t flags; 653 uint16_t cid; 654 uint32_t rsvd1[5]; 655 uint64_t prp1; 656 uint64_t rsvd8; 657 uint16_t cqid; 658 uint16_t qsize; 659 uint16_t cq_flags; 660 uint16_t irq_vector; 661 uint32_t rsvd12[4]; 662 } NvmeCreateCq; 663 664 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 665 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 666 667 enum NvmeFlagsCq { 668 NVME_CQ_PC = 1, 669 NVME_CQ_IEN = 2, 670 }; 671 672 typedef struct QEMU_PACKED NvmeCreateSq { 673 uint8_t opcode; 674 uint8_t flags; 675 uint16_t cid; 676 uint32_t rsvd1[5]; 677 uint64_t prp1; 678 uint64_t rsvd8; 679 uint16_t sqid; 680 uint16_t qsize; 681 uint16_t sq_flags; 682 uint16_t cqid; 683 uint32_t rsvd12[4]; 684 } NvmeCreateSq; 685 686 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 687 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 688 689 enum NvmeFlagsSq { 690 NVME_SQ_PC = 1, 691 692 NVME_SQ_PRIO_URGENT = 0, 693 NVME_SQ_PRIO_HIGH = 1, 694 NVME_SQ_PRIO_NORMAL = 2, 695 NVME_SQ_PRIO_LOW = 3, 696 }; 697 698 typedef struct QEMU_PACKED NvmeIdentify { 699 uint8_t opcode; 700 uint8_t flags; 701 uint16_t cid; 702 uint32_t nsid; 703 uint64_t rsvd2[2]; 704 uint64_t prp1; 705 uint64_t prp2; 706 uint8_t cns; 707 uint8_t rsvd10; 708 uint16_t ctrlid; 709 uint16_t nvmsetid; 710 uint8_t rsvd11; 711 uint8_t csi; 712 uint32_t rsvd12[4]; 713 } NvmeIdentify; 714 715 typedef struct QEMU_PACKED NvmeRwCmd { 716 uint8_t opcode; 717 uint8_t flags; 718 uint16_t cid; 719 uint32_t nsid; 720 uint32_t cdw2; 721 uint32_t cdw3; 722 uint64_t mptr; 723 NvmeCmdDptr dptr; 724 uint64_t slba; 725 uint16_t nlb; 726 uint16_t control; 727 uint32_t dsmgmt; 728 uint32_t reftag; 729 uint16_t apptag; 730 uint16_t appmask; 731 } NvmeRwCmd; 732 733 enum { 734 NVME_RW_LR = 1 << 15, 735 NVME_RW_FUA = 1 << 14, 736 NVME_RW_DSM_FREQ_UNSPEC = 0, 737 NVME_RW_DSM_FREQ_TYPICAL = 1, 738 NVME_RW_DSM_FREQ_RARE = 2, 739 NVME_RW_DSM_FREQ_READS = 3, 740 NVME_RW_DSM_FREQ_WRITES = 4, 741 NVME_RW_DSM_FREQ_RW = 5, 742 NVME_RW_DSM_FREQ_ONCE = 6, 743 NVME_RW_DSM_FREQ_PREFETCH = 7, 744 NVME_RW_DSM_FREQ_TEMP = 8, 745 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 746 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 747 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 748 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 749 NVME_RW_DSM_SEQ_REQ = 1 << 6, 750 NVME_RW_DSM_COMPRESSED = 1 << 7, 751 NVME_RW_PIREMAP = 1 << 9, 752 NVME_RW_PRINFO_PRACT = 1 << 13, 753 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 754 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 755 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 756 NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, 757 }; 758 759 #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) 760 761 enum { 762 NVME_PRINFO_PRACT = 1 << 3, 763 NVME_PRINFO_PRCHK_GUARD = 1 << 2, 764 NVME_PRINFO_PRCHK_APP = 1 << 1, 765 NVME_PRINFO_PRCHK_REF = 1 << 0, 766 NVME_PRINFO_PRCHK_MASK = 7 << 0, 767 }; 768 769 typedef struct QEMU_PACKED NvmeDsmCmd { 770 uint8_t opcode; 771 uint8_t flags; 772 uint16_t cid; 773 uint32_t nsid; 774 uint64_t rsvd2[2]; 775 NvmeCmdDptr dptr; 776 uint32_t nr; 777 uint32_t attributes; 778 uint32_t rsvd12[4]; 779 } NvmeDsmCmd; 780 781 enum { 782 NVME_DSMGMT_IDR = 1 << 0, 783 NVME_DSMGMT_IDW = 1 << 1, 784 NVME_DSMGMT_AD = 1 << 2, 785 }; 786 787 typedef struct QEMU_PACKED NvmeDsmRange { 788 uint32_t cattr; 789 uint32_t nlb; 790 uint64_t slba; 791 } NvmeDsmRange; 792 793 enum { 794 NVME_COPY_FORMAT_0 = 0x0, 795 NVME_COPY_FORMAT_1 = 0x1, 796 }; 797 798 typedef struct QEMU_PACKED NvmeCopyCmd { 799 uint8_t opcode; 800 uint8_t flags; 801 uint16_t cid; 802 uint32_t nsid; 803 uint32_t cdw2; 804 uint32_t cdw3; 805 uint32_t rsvd2[2]; 806 NvmeCmdDptr dptr; 807 uint64_t sdlba; 808 uint8_t nr; 809 uint8_t control[3]; 810 uint16_t rsvd13; 811 uint16_t dspec; 812 uint32_t reftag; 813 uint16_t apptag; 814 uint16_t appmask; 815 } NvmeCopyCmd; 816 817 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0 { 818 uint8_t rsvd0[8]; 819 uint64_t slba; 820 uint16_t nlb; 821 uint8_t rsvd18[6]; 822 uint32_t reftag; 823 uint16_t apptag; 824 uint16_t appmask; 825 } NvmeCopySourceRangeFormat0; 826 827 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1 { 828 uint8_t rsvd0[8]; 829 uint64_t slba; 830 uint16_t nlb; 831 uint8_t rsvd18[8]; 832 uint8_t sr[10]; 833 uint16_t apptag; 834 uint16_t appmask; 835 } NvmeCopySourceRangeFormat1; 836 837 enum NvmeAsyncEventRequest { 838 NVME_AER_TYPE_ERROR = 0, 839 NVME_AER_TYPE_SMART = 1, 840 NVME_AER_TYPE_NOTICE = 2, 841 NVME_AER_TYPE_IO_SPECIFIC = 6, 842 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 843 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 844 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 845 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 846 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 847 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 848 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 849 NVME_AER_INFO_SMART_RELIABILITY = 0, 850 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 851 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 852 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, 853 }; 854 855 typedef struct QEMU_PACKED NvmeAerResult { 856 uint8_t event_type; 857 uint8_t event_info; 858 uint8_t log_page; 859 uint8_t resv; 860 } NvmeAerResult; 861 862 typedef struct QEMU_PACKED NvmeZonedResult { 863 uint64_t slba; 864 } NvmeZonedResult; 865 866 typedef struct QEMU_PACKED NvmeCqe { 867 uint32_t result; 868 uint32_t dw1; 869 uint16_t sq_head; 870 uint16_t sq_id; 871 uint16_t cid; 872 uint16_t status; 873 } NvmeCqe; 874 875 enum NvmeStatusCodes { 876 NVME_SUCCESS = 0x0000, 877 NVME_INVALID_OPCODE = 0x0001, 878 NVME_INVALID_FIELD = 0x0002, 879 NVME_CID_CONFLICT = 0x0003, 880 NVME_DATA_TRAS_ERROR = 0x0004, 881 NVME_POWER_LOSS_ABORT = 0x0005, 882 NVME_INTERNAL_DEV_ERROR = 0x0006, 883 NVME_CMD_ABORT_REQ = 0x0007, 884 NVME_CMD_ABORT_SQ_DEL = 0x0008, 885 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 886 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 887 NVME_INVALID_NSID = 0x000b, 888 NVME_CMD_SEQ_ERROR = 0x000c, 889 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 890 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 891 NVME_DATA_SGL_LEN_INVALID = 0x000f, 892 NVME_MD_SGL_LEN_INVALID = 0x0010, 893 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 894 NVME_INVALID_USE_OF_CMB = 0x0012, 895 NVME_INVALID_PRP_OFFSET = 0x0013, 896 NVME_CMD_SET_CMB_REJECTED = 0x002b, 897 NVME_INVALID_CMD_SET = 0x002c, 898 NVME_LBA_RANGE = 0x0080, 899 NVME_CAP_EXCEEDED = 0x0081, 900 NVME_NS_NOT_READY = 0x0082, 901 NVME_NS_RESV_CONFLICT = 0x0083, 902 NVME_FORMAT_IN_PROGRESS = 0x0084, 903 NVME_INVALID_CQID = 0x0100, 904 NVME_INVALID_QID = 0x0101, 905 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 906 NVME_ACL_EXCEEDED = 0x0103, 907 NVME_RESERVED = 0x0104, 908 NVME_AER_LIMIT_EXCEEDED = 0x0105, 909 NVME_INVALID_FW_SLOT = 0x0106, 910 NVME_INVALID_FW_IMAGE = 0x0107, 911 NVME_INVALID_IRQ_VECTOR = 0x0108, 912 NVME_INVALID_LOG_ID = 0x0109, 913 NVME_INVALID_FORMAT = 0x010a, 914 NVME_FW_REQ_RESET = 0x010b, 915 NVME_INVALID_QUEUE_DEL = 0x010c, 916 NVME_FID_NOT_SAVEABLE = 0x010d, 917 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 918 NVME_FEAT_NOT_NS_SPEC = 0x010f, 919 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 920 NVME_NS_ALREADY_ATTACHED = 0x0118, 921 NVME_NS_PRIVATE = 0x0119, 922 NVME_NS_NOT_ATTACHED = 0x011a, 923 NVME_NS_CTRL_LIST_INVALID = 0x011c, 924 NVME_INVALID_CTRL_ID = 0x011f, 925 NVME_INVALID_SEC_CTRL_STATE = 0x0120, 926 NVME_INVALID_NUM_RESOURCES = 0x0121, 927 NVME_INVALID_RESOURCE_ID = 0x0122, 928 NVME_CONFLICTING_ATTRS = 0x0180, 929 NVME_INVALID_PROT_INFO = 0x0181, 930 NVME_WRITE_TO_RO = 0x0182, 931 NVME_CMD_SIZE_LIMIT = 0x0183, 932 NVME_INVALID_ZONE_OP = 0x01b6, 933 NVME_NOZRWA = 0x01b7, 934 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 935 NVME_ZONE_FULL = 0x01b9, 936 NVME_ZONE_READ_ONLY = 0x01ba, 937 NVME_ZONE_OFFLINE = 0x01bb, 938 NVME_ZONE_INVALID_WRITE = 0x01bc, 939 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 940 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 941 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 942 NVME_WRITE_FAULT = 0x0280, 943 NVME_UNRECOVERED_READ = 0x0281, 944 NVME_E2E_GUARD_ERROR = 0x0282, 945 NVME_E2E_APP_ERROR = 0x0283, 946 NVME_E2E_REF_ERROR = 0x0284, 947 NVME_CMP_FAILURE = 0x0285, 948 NVME_ACCESS_DENIED = 0x0286, 949 NVME_DULB = 0x0287, 950 NVME_E2E_STORAGE_TAG_ERROR = 0x0288, 951 NVME_MORE = 0x2000, 952 NVME_DNR = 0x4000, 953 NVME_NO_COMPLETE = 0xffff, 954 }; 955 956 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 957 uint8_t afi; 958 uint8_t reserved1[7]; 959 uint8_t frs1[8]; 960 uint8_t frs2[8]; 961 uint8_t frs3[8]; 962 uint8_t frs4[8]; 963 uint8_t frs5[8]; 964 uint8_t frs6[8]; 965 uint8_t frs7[8]; 966 uint8_t reserved2[448]; 967 } NvmeFwSlotInfoLog; 968 969 typedef struct QEMU_PACKED NvmeErrorLog { 970 uint64_t error_count; 971 uint16_t sqid; 972 uint16_t cid; 973 uint16_t status_field; 974 uint16_t param_error_location; 975 uint64_t lba; 976 uint32_t nsid; 977 uint8_t vs; 978 uint8_t resv[35]; 979 } NvmeErrorLog; 980 981 typedef struct QEMU_PACKED NvmeSmartLog { 982 uint8_t critical_warning; 983 uint16_t temperature; 984 uint8_t available_spare; 985 uint8_t available_spare_threshold; 986 uint8_t percentage_used; 987 uint8_t reserved1[26]; 988 uint64_t data_units_read[2]; 989 uint64_t data_units_written[2]; 990 uint64_t host_read_commands[2]; 991 uint64_t host_write_commands[2]; 992 uint64_t controller_busy_time[2]; 993 uint64_t power_cycles[2]; 994 uint64_t power_on_hours[2]; 995 uint64_t unsafe_shutdowns[2]; 996 uint64_t media_errors[2]; 997 uint64_t number_of_error_log_entries[2]; 998 uint8_t reserved2[320]; 999 } NvmeSmartLog; 1000 1001 #define NVME_SMART_WARN_MAX 6 1002 enum NvmeSmartWarn { 1003 NVME_SMART_SPARE = 1 << 0, 1004 NVME_SMART_TEMPERATURE = 1 << 1, 1005 NVME_SMART_RELIABILITY = 1 << 2, 1006 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 1007 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 1008 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 1009 }; 1010 1011 typedef struct NvmeEffectsLog { 1012 uint32_t acs[256]; 1013 uint32_t iocs[256]; 1014 uint8_t resv[2048]; 1015 } NvmeEffectsLog; 1016 1017 enum { 1018 NVME_CMD_EFF_CSUPP = 1 << 0, 1019 NVME_CMD_EFF_LBCC = 1 << 1, 1020 NVME_CMD_EFF_NCC = 1 << 2, 1021 NVME_CMD_EFF_NIC = 1 << 3, 1022 NVME_CMD_EFF_CCC = 1 << 4, 1023 NVME_CMD_EFF_CSE_MASK = 3 << 16, 1024 NVME_CMD_EFF_UUID_SEL = 1 << 19, 1025 }; 1026 1027 enum NvmeLogIdentifier { 1028 NVME_LOG_ERROR_INFO = 0x01, 1029 NVME_LOG_SMART_INFO = 0x02, 1030 NVME_LOG_FW_SLOT_INFO = 0x03, 1031 NVME_LOG_CHANGED_NSLIST = 0x04, 1032 NVME_LOG_CMD_EFFECTS = 0x05, 1033 NVME_LOG_ENDGRP = 0x09, 1034 }; 1035 1036 typedef struct QEMU_PACKED NvmePSD { 1037 uint16_t mp; 1038 uint16_t reserved; 1039 uint32_t enlat; 1040 uint32_t exlat; 1041 uint8_t rrt; 1042 uint8_t rrl; 1043 uint8_t rwt; 1044 uint8_t rwl; 1045 uint8_t resv[16]; 1046 } NvmePSD; 1047 1048 #define NVME_CONTROLLER_LIST_SIZE 2048 1049 #define NVME_IDENTIFY_DATA_SIZE 4096 1050 1051 enum NvmeIdCns { 1052 NVME_ID_CNS_NS = 0x00, 1053 NVME_ID_CNS_CTRL = 0x01, 1054 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 1055 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 1056 NVME_ID_CNS_CS_NS = 0x05, 1057 NVME_ID_CNS_CS_CTRL = 0x06, 1058 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 1059 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 1060 NVME_ID_CNS_NS_PRESENT = 0x11, 1061 NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, 1062 NVME_ID_CNS_CTRL_LIST = 0x13, 1063 NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, 1064 NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, 1065 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 1066 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 1067 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 1068 }; 1069 1070 typedef struct QEMU_PACKED NvmeIdCtrl { 1071 uint16_t vid; 1072 uint16_t ssvid; 1073 uint8_t sn[20]; 1074 uint8_t mn[40]; 1075 uint8_t fr[8]; 1076 uint8_t rab; 1077 uint8_t ieee[3]; 1078 uint8_t cmic; 1079 uint8_t mdts; 1080 uint16_t cntlid; 1081 uint32_t ver; 1082 uint32_t rtd3r; 1083 uint32_t rtd3e; 1084 uint32_t oaes; 1085 uint32_t ctratt; 1086 uint8_t rsvd100[11]; 1087 uint8_t cntrltype; 1088 uint8_t fguid[16]; 1089 uint8_t rsvd128[128]; 1090 uint16_t oacs; 1091 uint8_t acl; 1092 uint8_t aerl; 1093 uint8_t frmw; 1094 uint8_t lpa; 1095 uint8_t elpe; 1096 uint8_t npss; 1097 uint8_t avscc; 1098 uint8_t apsta; 1099 uint16_t wctemp; 1100 uint16_t cctemp; 1101 uint16_t mtfa; 1102 uint32_t hmpre; 1103 uint32_t hmmin; 1104 uint8_t tnvmcap[16]; 1105 uint8_t unvmcap[16]; 1106 uint32_t rpmbs; 1107 uint16_t edstt; 1108 uint8_t dsto; 1109 uint8_t fwug; 1110 uint16_t kas; 1111 uint16_t hctma; 1112 uint16_t mntmt; 1113 uint16_t mxtmt; 1114 uint32_t sanicap; 1115 uint8_t rsvd332[6]; 1116 uint16_t nsetidmax; 1117 uint16_t endgidmax; 1118 uint8_t rsvd342[170]; 1119 uint8_t sqes; 1120 uint8_t cqes; 1121 uint16_t maxcmd; 1122 uint32_t nn; 1123 uint16_t oncs; 1124 uint16_t fuses; 1125 uint8_t fna; 1126 uint8_t vwc; 1127 uint16_t awun; 1128 uint16_t awupf; 1129 uint8_t nvscc; 1130 uint8_t rsvd531; 1131 uint16_t acwu; 1132 uint16_t ocfs; 1133 uint32_t sgls; 1134 uint8_t rsvd540[228]; 1135 uint8_t subnqn[256]; 1136 uint8_t rsvd1024[1024]; 1137 NvmePSD psd[32]; 1138 uint8_t vs[1024]; 1139 } NvmeIdCtrl; 1140 1141 typedef struct NvmeIdCtrlZoned { 1142 uint8_t zasl; 1143 uint8_t rsvd1[4095]; 1144 } NvmeIdCtrlZoned; 1145 1146 typedef struct NvmeIdCtrlNvm { 1147 uint8_t vsl; 1148 uint8_t wzsl; 1149 uint8_t wusl; 1150 uint8_t dmrl; 1151 uint32_t dmrsl; 1152 uint64_t dmsl; 1153 uint8_t rsvd16[4080]; 1154 } NvmeIdCtrlNvm; 1155 1156 enum NvmeIdCtrlOaes { 1157 NVME_OAES_NS_ATTR = 1 << 8, 1158 }; 1159 1160 enum NvmeIdCtrlCtratt { 1161 NVME_CTRATT_ENDGRPS = 1 << 4, 1162 NVME_CTRATT_ELBAS = 1 << 15, 1163 }; 1164 1165 enum NvmeIdCtrlOacs { 1166 NVME_OACS_SECURITY = 1 << 0, 1167 NVME_OACS_FORMAT = 1 << 1, 1168 NVME_OACS_FW = 1 << 2, 1169 NVME_OACS_NS_MGMT = 1 << 3, 1170 NVME_OACS_DIRECTIVES = 1 << 5, 1171 NVME_OACS_DBBUF = 1 << 8, 1172 }; 1173 1174 enum NvmeIdCtrlOncs { 1175 NVME_ONCS_COMPARE = 1 << 0, 1176 NVME_ONCS_WRITE_UNCORR = 1 << 1, 1177 NVME_ONCS_DSM = 1 << 2, 1178 NVME_ONCS_WRITE_ZEROES = 1 << 3, 1179 NVME_ONCS_FEATURES = 1 << 4, 1180 NVME_ONCS_RESRVATIONS = 1 << 5, 1181 NVME_ONCS_TIMESTAMP = 1 << 6, 1182 NVME_ONCS_VERIFY = 1 << 7, 1183 NVME_ONCS_COPY = 1 << 8, 1184 }; 1185 1186 enum NvmeIdCtrlOcfs { 1187 NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0, 1188 NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1, 1189 }; 1190 1191 enum NvmeIdctrlVwc { 1192 NVME_VWC_PRESENT = 1 << 0, 1193 NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, 1194 NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, 1195 NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, 1196 NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, 1197 }; 1198 1199 enum NvmeIdCtrlFrmw { 1200 NVME_FRMW_SLOT1_RO = 1 << 0, 1201 }; 1202 1203 enum NvmeIdCtrlLpa { 1204 NVME_LPA_NS_SMART = 1 << 0, 1205 NVME_LPA_CSE = 1 << 1, 1206 NVME_LPA_EXTENDED = 1 << 2, 1207 }; 1208 1209 enum NvmeIdCtrlCmic { 1210 NVME_CMIC_MULTI_CTRL = 1 << 1, 1211 }; 1212 1213 enum NvmeNsAttachmentOperation { 1214 NVME_NS_ATTACHMENT_ATTACH = 0x0, 1215 NVME_NS_ATTACHMENT_DETACH = 0x1, 1216 }; 1217 1218 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 1219 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 1220 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 1221 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 1222 1223 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 1224 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 1225 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 1226 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 1227 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 1228 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 1229 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 1230 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 1231 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 1232 1233 #define NVME_ARB_AB(arb) (arb & 0x7) 1234 #define NVME_ARB_AB_NOLIMIT 0x7 1235 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 1236 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 1237 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 1238 1239 #define NVME_INTC_THR(intc) (intc & 0xff) 1240 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 1241 1242 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 1243 1244 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 1245 #define NVME_TEMP_THSEL_OVER 0x0 1246 #define NVME_TEMP_THSEL_UNDER 0x1 1247 1248 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 1249 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 1250 1251 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 1252 1253 #define NVME_AEC_SMART(aec) (aec & 0xff) 1254 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 1255 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 1256 #define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1) 1257 1258 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 1259 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 1260 1261 enum NvmeFeatureIds { 1262 NVME_ARBITRATION = 0x1, 1263 NVME_POWER_MANAGEMENT = 0x2, 1264 NVME_LBA_RANGE_TYPE = 0x3, 1265 NVME_TEMPERATURE_THRESHOLD = 0x4, 1266 NVME_ERROR_RECOVERY = 0x5, 1267 NVME_VOLATILE_WRITE_CACHE = 0x6, 1268 NVME_NUMBER_OF_QUEUES = 0x7, 1269 NVME_INTERRUPT_COALESCING = 0x8, 1270 NVME_INTERRUPT_VECTOR_CONF = 0x9, 1271 NVME_WRITE_ATOMICITY = 0xa, 1272 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1273 NVME_TIMESTAMP = 0xe, 1274 NVME_HOST_BEHAVIOR_SUPPORT = 0x16, 1275 NVME_COMMAND_SET_PROFILE = 0x19, 1276 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1277 NVME_FID_MAX = 0x100, 1278 }; 1279 1280 typedef enum NvmeFeatureCap { 1281 NVME_FEAT_CAP_SAVE = 1 << 0, 1282 NVME_FEAT_CAP_NS = 1 << 1, 1283 NVME_FEAT_CAP_CHANGE = 1 << 2, 1284 } NvmeFeatureCap; 1285 1286 typedef enum NvmeGetFeatureSelect { 1287 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1288 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1289 NVME_GETFEAT_SELECT_SAVED = 0x2, 1290 NVME_GETFEAT_SELECT_CAP = 0x3, 1291 } NvmeGetFeatureSelect; 1292 1293 #define NVME_GETSETFEAT_FID_MASK 0xff 1294 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1295 1296 #define NVME_GETFEAT_SELECT_SHIFT 8 1297 #define NVME_GETFEAT_SELECT_MASK 0x7 1298 #define NVME_GETFEAT_SELECT(dw10) \ 1299 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1300 1301 #define NVME_SETFEAT_SAVE_SHIFT 31 1302 #define NVME_SETFEAT_SAVE_MASK 0x1 1303 #define NVME_SETFEAT_SAVE(dw10) \ 1304 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1305 1306 typedef struct QEMU_PACKED NvmeRangeType { 1307 uint8_t type; 1308 uint8_t attributes; 1309 uint8_t rsvd2[14]; 1310 uint64_t slba; 1311 uint64_t nlb; 1312 uint8_t guid[16]; 1313 uint8_t rsvd48[16]; 1314 } NvmeRangeType; 1315 1316 typedef struct NvmeHostBehaviorSupport { 1317 uint8_t acre; 1318 uint8_t etdas; 1319 uint8_t lbafee; 1320 uint8_t rsvd3[509]; 1321 } NvmeHostBehaviorSupport; 1322 1323 typedef struct QEMU_PACKED NvmeLBAF { 1324 uint16_t ms; 1325 uint8_t ds; 1326 uint8_t rp; 1327 } NvmeLBAF; 1328 1329 typedef struct QEMU_PACKED NvmeLBAFE { 1330 uint64_t zsze; 1331 uint8_t zdes; 1332 uint8_t rsvd9[7]; 1333 } NvmeLBAFE; 1334 1335 #define NVME_NSID_BROADCAST 0xffffffff 1336 #define NVME_MAX_NLBAF 64 1337 1338 typedef struct QEMU_PACKED NvmeIdNs { 1339 uint64_t nsze; 1340 uint64_t ncap; 1341 uint64_t nuse; 1342 uint8_t nsfeat; 1343 uint8_t nlbaf; 1344 uint8_t flbas; 1345 uint8_t mc; 1346 uint8_t dpc; 1347 uint8_t dps; 1348 uint8_t nmic; 1349 uint8_t rescap; 1350 uint8_t fpi; 1351 uint8_t dlfeat; 1352 uint16_t nawun; 1353 uint16_t nawupf; 1354 uint16_t nacwu; 1355 uint16_t nabsn; 1356 uint16_t nabo; 1357 uint16_t nabspf; 1358 uint16_t noiob; 1359 uint8_t nvmcap[16]; 1360 uint16_t npwg; 1361 uint16_t npwa; 1362 uint16_t npdg; 1363 uint16_t npda; 1364 uint16_t nows; 1365 uint16_t mssrl; 1366 uint32_t mcl; 1367 uint8_t msrc; 1368 uint8_t rsvd81[18]; 1369 uint8_t nsattr; 1370 uint16_t nvmsetid; 1371 uint16_t endgid; 1372 uint8_t nguid[16]; 1373 uint64_t eui64; 1374 NvmeLBAF lbaf[NVME_MAX_NLBAF]; 1375 uint8_t vs[3712]; 1376 } NvmeIdNs; 1377 1378 #define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3) 1379 1380 typedef struct QEMU_PACKED NvmeIdNsNvm { 1381 uint64_t lbstm; 1382 uint8_t pic; 1383 uint8_t rsvd9[3]; 1384 uint32_t elbaf[NVME_MAX_NLBAF]; 1385 uint8_t rsvd268[3828]; 1386 } NvmeIdNsNvm; 1387 1388 typedef struct QEMU_PACKED NvmeIdNsDescr { 1389 uint8_t nidt; 1390 uint8_t nidl; 1391 uint8_t rsvd2[2]; 1392 } NvmeIdNsDescr; 1393 1394 enum NvmeNsIdentifierLength { 1395 NVME_NIDL_EUI64 = 8, 1396 NVME_NIDL_NGUID = 16, 1397 NVME_NIDL_UUID = 16, 1398 NVME_NIDL_CSI = 1, 1399 }; 1400 1401 enum NvmeNsIdentifierType { 1402 NVME_NIDT_EUI64 = 0x01, 1403 NVME_NIDT_NGUID = 0x02, 1404 NVME_NIDT_UUID = 0x03, 1405 NVME_NIDT_CSI = 0x04, 1406 }; 1407 1408 enum NvmeIdNsNmic { 1409 NVME_NMIC_NS_SHARED = 1 << 0, 1410 }; 1411 1412 enum NvmeCsi { 1413 NVME_CSI_NVM = 0x00, 1414 NVME_CSI_ZONED = 0x02, 1415 }; 1416 1417 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1418 1419 typedef struct QEMU_PACKED NvmeIdNsZoned { 1420 uint16_t zoc; 1421 uint16_t ozcs; 1422 uint32_t mar; 1423 uint32_t mor; 1424 uint32_t rrl; 1425 uint32_t frl; 1426 uint8_t rsvd12[24]; 1427 uint32_t numzrwa; 1428 uint16_t zrwafg; 1429 uint16_t zrwas; 1430 uint8_t zrwacap; 1431 uint8_t rsvd53[2763]; 1432 NvmeLBAFE lbafe[16]; 1433 uint8_t rsvd3072[768]; 1434 uint8_t vs[256]; 1435 } NvmeIdNsZoned; 1436 1437 enum NvmeIdNsZonedOzcs { 1438 NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0, 1439 NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1, 1440 }; 1441 1442 enum NvmeIdNsZonedZrwacap { 1443 NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0, 1444 }; 1445 1446 /*Deallocate Logical Block Features*/ 1447 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1448 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1449 1450 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1451 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1452 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1453 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1454 1455 1456 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1457 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1458 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1459 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1460 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1461 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1462 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1463 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1464 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1465 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1466 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1467 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1468 1469 enum NvmeIdNsDps { 1470 NVME_ID_NS_DPS_TYPE_NONE = 0, 1471 NVME_ID_NS_DPS_TYPE_1 = 1, 1472 NVME_ID_NS_DPS_TYPE_2 = 2, 1473 NVME_ID_NS_DPS_TYPE_3 = 3, 1474 NVME_ID_NS_DPS_TYPE_MASK = 0x7, 1475 NVME_ID_NS_DPS_FIRST_EIGHT = 8, 1476 }; 1477 1478 enum NvmeIdNsFlbas { 1479 NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, 1480 }; 1481 1482 enum NvmeIdNsMc { 1483 NVME_ID_NS_MC_EXTENDED = 1 << 0, 1484 NVME_ID_NS_MC_SEPARATE = 1 << 1, 1485 }; 1486 1487 #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) 1488 1489 enum NvmePIFormat { 1490 NVME_PI_GUARD_16 = 0, 1491 NVME_PI_GUARD_64 = 2, 1492 }; 1493 1494 typedef union NvmeDifTuple { 1495 struct { 1496 uint16_t guard; 1497 uint16_t apptag; 1498 uint32_t reftag; 1499 } g16; 1500 1501 struct { 1502 uint64_t guard; 1503 uint16_t apptag; 1504 uint8_t sr[6]; 1505 } g64; 1506 } NvmeDifTuple; 1507 1508 enum NvmeZoneAttr { 1509 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1510 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1511 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1512 NVME_ZA_ZRWA_VALID = 1 << 3, 1513 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1514 }; 1515 1516 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1517 uint64_t nr_zones; 1518 uint8_t rsvd[56]; 1519 } NvmeZoneReportHeader; 1520 1521 enum NvmeZoneReceiveAction { 1522 NVME_ZONE_REPORT = 0, 1523 NVME_ZONE_REPORT_EXTENDED = 1, 1524 }; 1525 1526 enum NvmeZoneReportType { 1527 NVME_ZONE_REPORT_ALL = 0, 1528 NVME_ZONE_REPORT_EMPTY = 1, 1529 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1530 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1531 NVME_ZONE_REPORT_CLOSED = 4, 1532 NVME_ZONE_REPORT_FULL = 5, 1533 NVME_ZONE_REPORT_READ_ONLY = 6, 1534 NVME_ZONE_REPORT_OFFLINE = 7, 1535 }; 1536 1537 enum NvmeZoneType { 1538 NVME_ZONE_TYPE_RESERVED = 0x00, 1539 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1540 }; 1541 1542 typedef struct QEMU_PACKED NvmeZoneSendCmd { 1543 uint8_t opcode; 1544 uint8_t flags; 1545 uint16_t cid; 1546 uint32_t nsid; 1547 uint32_t rsvd8[4]; 1548 NvmeCmdDptr dptr; 1549 uint64_t slba; 1550 uint32_t rsvd48; 1551 uint8_t zsa; 1552 uint8_t zsflags; 1553 uint8_t rsvd54[2]; 1554 uint32_t rsvd56[2]; 1555 } NvmeZoneSendCmd; 1556 1557 enum NvmeZoneSendAction { 1558 NVME_ZONE_ACTION_RSD = 0x00, 1559 NVME_ZONE_ACTION_CLOSE = 0x01, 1560 NVME_ZONE_ACTION_FINISH = 0x02, 1561 NVME_ZONE_ACTION_OPEN = 0x03, 1562 NVME_ZONE_ACTION_RESET = 0x04, 1563 NVME_ZONE_ACTION_OFFLINE = 0x05, 1564 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1565 NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11, 1566 }; 1567 1568 enum { 1569 NVME_ZSFLAG_SELECT_ALL = 1 << 0, 1570 NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1, 1571 }; 1572 1573 typedef struct QEMU_PACKED NvmeZoneDescr { 1574 uint8_t zt; 1575 uint8_t zs; 1576 uint8_t za; 1577 uint8_t rsvd3[5]; 1578 uint64_t zcap; 1579 uint64_t zslba; 1580 uint64_t wp; 1581 uint8_t rsvd32[32]; 1582 } NvmeZoneDescr; 1583 1584 typedef enum NvmeZoneState { 1585 NVME_ZONE_STATE_RESERVED = 0x00, 1586 NVME_ZONE_STATE_EMPTY = 0x01, 1587 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1588 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1589 NVME_ZONE_STATE_CLOSED = 0x04, 1590 NVME_ZONE_STATE_READ_ONLY = 0x0d, 1591 NVME_ZONE_STATE_FULL = 0x0e, 1592 NVME_ZONE_STATE_OFFLINE = 0x0f, 1593 } NvmeZoneState; 1594 1595 typedef struct QEMU_PACKED NvmePriCtrlCap { 1596 uint16_t cntlid; 1597 uint16_t portid; 1598 uint8_t crt; 1599 uint8_t rsvd5[27]; 1600 uint32_t vqfrt; 1601 uint32_t vqrfa; 1602 uint16_t vqrfap; 1603 uint16_t vqprt; 1604 uint16_t vqfrsm; 1605 uint16_t vqgran; 1606 uint8_t rsvd48[16]; 1607 uint32_t vifrt; 1608 uint32_t virfa; 1609 uint16_t virfap; 1610 uint16_t viprt; 1611 uint16_t vifrsm; 1612 uint16_t vigran; 1613 uint8_t rsvd80[4016]; 1614 } NvmePriCtrlCap; 1615 1616 typedef enum NvmePriCtrlCapCrt { 1617 NVME_CRT_VQ = 1 << 0, 1618 NVME_CRT_VI = 1 << 1, 1619 } NvmePriCtrlCapCrt; 1620 1621 typedef struct QEMU_PACKED NvmeSecCtrlEntry { 1622 uint16_t scid; 1623 uint16_t pcid; 1624 uint8_t scs; 1625 uint8_t rsvd5[3]; 1626 uint16_t vfn; 1627 uint16_t nvq; 1628 uint16_t nvi; 1629 uint8_t rsvd14[18]; 1630 } NvmeSecCtrlEntry; 1631 1632 typedef struct QEMU_PACKED NvmeSecCtrlList { 1633 uint8_t numcntl; 1634 uint8_t rsvd1[31]; 1635 NvmeSecCtrlEntry sec[127]; 1636 } NvmeSecCtrlList; 1637 1638 typedef enum NvmeVirtMngmtAction { 1639 NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01, 1640 NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07, 1641 NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08, 1642 NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09, 1643 } NvmeVirtMngmtAction; 1644 1645 typedef enum NvmeVirtualResourceType { 1646 NVME_VIRT_RES_QUEUE = 0x00, 1647 NVME_VIRT_RES_INTERRUPT = 0x01, 1648 } NvmeVirtualResourceType; 1649 1650 typedef struct NvmeDirectiveIdentify { 1651 uint8_t supported; 1652 uint8_t unused1[31]; 1653 uint8_t enabled; 1654 uint8_t unused33[31]; 1655 uint8_t rsvd64[4032]; 1656 } NvmeDirectiveIdentify; 1657 1658 enum NvmeDirective { 1659 NVME_DIRECTIVE_SUPPORTED = 0x0, 1660 NVME_DIRECTIVE_ENABLED = 0x1, 1661 }; 1662 1663 enum NvmeDirectiveTypes { 1664 NVME_DIRECTIVE_IDENTIFY = 0x0, 1665 }; 1666 1667 enum NvmeDirectiveOperations { 1668 NVME_DIRECTIVE_RETURN_PARAMS = 0x1, 1669 }; 1670 1671 static inline void _nvme_check_size(void) 1672 { 1673 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1674 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1675 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1676 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1677 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1678 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0) != 32); 1679 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1) != 40); 1680 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1681 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1682 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1683 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1684 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1685 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1686 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1687 QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); 1688 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1689 QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512); 1690 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1691 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1692 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1693 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1694 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1695 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1696 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); 1697 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1698 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1699 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1700 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096); 1701 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1702 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1703 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1704 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1705 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16); 1706 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096); 1707 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32); 1708 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096); 1709 QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512); 1710 QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096); 1711 } 1712 #endif 1713