1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint8_t rsvd24[4]; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint32_t bpinfo; 19 uint32_t bprsel; 20 uint64_t bpmbl; 21 uint64_t cmbmsc; 22 uint32_t cmbsts; 23 uint8_t rsvd92[3492]; 24 uint32_t pmrcap; 25 uint32_t pmrctl; 26 uint32_t pmrsts; 27 uint32_t pmrebs; 28 uint32_t pmrswtp; 29 uint32_t pmrmscl; 30 uint32_t pmrmscu; 31 uint8_t css[484]; 32 } NvmeBar; 33 34 enum NvmeCapShift { 35 CAP_MQES_SHIFT = 0, 36 CAP_CQR_SHIFT = 16, 37 CAP_AMS_SHIFT = 17, 38 CAP_TO_SHIFT = 24, 39 CAP_DSTRD_SHIFT = 32, 40 CAP_NSSRS_SHIFT = 36, 41 CAP_CSS_SHIFT = 37, 42 CAP_MPSMIN_SHIFT = 48, 43 CAP_MPSMAX_SHIFT = 52, 44 CAP_PMRS_SHIFT = 56, 45 CAP_CMBS_SHIFT = 57, 46 }; 47 48 enum NvmeCapMask { 49 CAP_MQES_MASK = 0xffff, 50 CAP_CQR_MASK = 0x1, 51 CAP_AMS_MASK = 0x3, 52 CAP_TO_MASK = 0xff, 53 CAP_DSTRD_MASK = 0xf, 54 CAP_NSSRS_MASK = 0x1, 55 CAP_CSS_MASK = 0xff, 56 CAP_MPSMIN_MASK = 0xf, 57 CAP_MPSMAX_MASK = 0xf, 58 CAP_PMRS_MASK = 0x1, 59 CAP_CMBS_MASK = 0x1, 60 }; 61 62 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 63 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 64 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 65 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 66 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 67 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 68 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 69 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 70 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 71 #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 72 #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) 73 74 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 75 << CAP_MQES_SHIFT) 76 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 77 << CAP_CQR_SHIFT) 78 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 79 << CAP_AMS_SHIFT) 80 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 81 << CAP_TO_SHIFT) 82 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 83 << CAP_DSTRD_SHIFT) 84 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 85 << CAP_NSSRS_SHIFT) 86 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 87 << CAP_CSS_SHIFT) 88 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 89 << CAP_MPSMIN_SHIFT) 90 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 91 << CAP_MPSMAX_SHIFT) 92 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMRS_MASK) \ 93 << CAP_PMRS_SHIFT) 94 #define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMBS_MASK) \ 95 << CAP_CMBS_SHIFT) 96 97 enum NvmeCapCss { 98 NVME_CAP_CSS_NVM = 1 << 0, 99 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 100 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 101 }; 102 103 enum NvmeCcShift { 104 CC_EN_SHIFT = 0, 105 CC_CSS_SHIFT = 4, 106 CC_MPS_SHIFT = 7, 107 CC_AMS_SHIFT = 11, 108 CC_SHN_SHIFT = 14, 109 CC_IOSQES_SHIFT = 16, 110 CC_IOCQES_SHIFT = 20, 111 }; 112 113 enum NvmeCcMask { 114 CC_EN_MASK = 0x1, 115 CC_CSS_MASK = 0x7, 116 CC_MPS_MASK = 0xf, 117 CC_AMS_MASK = 0x7, 118 CC_SHN_MASK = 0x3, 119 CC_IOSQES_MASK = 0xf, 120 CC_IOCQES_MASK = 0xf, 121 }; 122 123 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 124 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 125 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 126 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 127 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 128 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 129 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 130 131 enum NvmeCcCss { 132 NVME_CC_CSS_NVM = 0x0, 133 NVME_CC_CSS_CSI = 0x6, 134 NVME_CC_CSS_ADMIN_ONLY = 0x7, 135 }; 136 137 #define NVME_SET_CC_EN(cc, val) \ 138 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 139 #define NVME_SET_CC_CSS(cc, val) \ 140 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 141 #define NVME_SET_CC_MPS(cc, val) \ 142 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 143 #define NVME_SET_CC_AMS(cc, val) \ 144 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 145 #define NVME_SET_CC_SHN(cc, val) \ 146 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 147 #define NVME_SET_CC_IOSQES(cc, val) \ 148 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 149 #define NVME_SET_CC_IOCQES(cc, val) \ 150 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 151 152 enum NvmeCstsShift { 153 CSTS_RDY_SHIFT = 0, 154 CSTS_CFS_SHIFT = 1, 155 CSTS_SHST_SHIFT = 2, 156 CSTS_NSSRO_SHIFT = 4, 157 }; 158 159 enum NvmeCstsMask { 160 CSTS_RDY_MASK = 0x1, 161 CSTS_CFS_MASK = 0x1, 162 CSTS_SHST_MASK = 0x3, 163 CSTS_NSSRO_MASK = 0x1, 164 }; 165 166 enum NvmeCsts { 167 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 168 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 169 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 170 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 171 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 172 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 173 }; 174 175 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 176 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 177 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 178 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 179 180 enum NvmeAqaShift { 181 AQA_ASQS_SHIFT = 0, 182 AQA_ACQS_SHIFT = 16, 183 }; 184 185 enum NvmeAqaMask { 186 AQA_ASQS_MASK = 0xfff, 187 AQA_ACQS_MASK = 0xfff, 188 }; 189 190 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 191 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 192 193 enum NvmeCmblocShift { 194 CMBLOC_BIR_SHIFT = 0, 195 CMBLOC_CQMMS_SHIFT = 3, 196 CMBLOC_CQPDS_SHIFT = 4, 197 CMBLOC_CDPMLS_SHIFT = 5, 198 CMBLOC_CDPCILS_SHIFT = 6, 199 CMBLOC_CDMMMS_SHIFT = 7, 200 CMBLOC_CQDA_SHIFT = 8, 201 CMBLOC_OFST_SHIFT = 12, 202 }; 203 204 enum NvmeCmblocMask { 205 CMBLOC_BIR_MASK = 0x7, 206 CMBLOC_CQMMS_MASK = 0x1, 207 CMBLOC_CQPDS_MASK = 0x1, 208 CMBLOC_CDPMLS_MASK = 0x1, 209 CMBLOC_CDPCILS_MASK = 0x1, 210 CMBLOC_CDMMMS_MASK = 0x1, 211 CMBLOC_CQDA_MASK = 0x1, 212 CMBLOC_OFST_MASK = 0xfffff, 213 }; 214 215 #define NVME_CMBLOC_BIR(cmbloc) \ 216 ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) 217 #define NVME_CMBLOC_CQMMS(cmbloc) \ 218 ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) 219 #define NVME_CMBLOC_CQPDS(cmbloc) \ 220 ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) 221 #define NVME_CMBLOC_CDPMLS(cmbloc) \ 222 ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) 223 #define NVME_CMBLOC_CDPCILS(cmbloc) \ 224 ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) 225 #define NVME_CMBLOC_CDMMMS(cmbloc) \ 226 ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) 227 #define NVME_CMBLOC_CQDA(cmbloc) \ 228 ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) 229 #define NVME_CMBLOC_OFST(cmbloc) \ 230 ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) 231 232 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 233 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 234 #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ 235 (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) 236 #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ 237 (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) 238 #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ 239 (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) 240 #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ 241 (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) 242 #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ 243 (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) 244 #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ 245 (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) 246 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 247 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 248 249 #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ 250 (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) 251 252 enum NvmeCmbszShift { 253 CMBSZ_SQS_SHIFT = 0, 254 CMBSZ_CQS_SHIFT = 1, 255 CMBSZ_LISTS_SHIFT = 2, 256 CMBSZ_RDS_SHIFT = 3, 257 CMBSZ_WDS_SHIFT = 4, 258 CMBSZ_SZU_SHIFT = 8, 259 CMBSZ_SZ_SHIFT = 12, 260 }; 261 262 enum NvmeCmbszMask { 263 CMBSZ_SQS_MASK = 0x1, 264 CMBSZ_CQS_MASK = 0x1, 265 CMBSZ_LISTS_MASK = 0x1, 266 CMBSZ_RDS_MASK = 0x1, 267 CMBSZ_WDS_MASK = 0x1, 268 CMBSZ_SZU_MASK = 0xf, 269 CMBSZ_SZ_MASK = 0xfffff, 270 }; 271 272 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 273 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 274 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 275 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 276 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 277 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 278 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 279 280 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 281 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 282 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 283 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 284 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 285 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 286 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 287 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 288 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 289 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 290 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 291 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 292 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 293 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 294 295 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 296 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 297 298 enum NvmeCmbmscShift { 299 CMBMSC_CRE_SHIFT = 0, 300 CMBMSC_CMSE_SHIFT = 1, 301 CMBMSC_CBA_SHIFT = 12, 302 }; 303 304 enum NvmeCmbmscMask { 305 CMBMSC_CRE_MASK = 0x1, 306 CMBMSC_CMSE_MASK = 0x1, 307 CMBMSC_CBA_MASK = ((1ULL << 52) - 1), 308 }; 309 310 #define NVME_CMBMSC_CRE(cmbmsc) \ 311 ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) 312 #define NVME_CMBMSC_CMSE(cmbmsc) \ 313 ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) 314 #define NVME_CMBMSC_CBA(cmbmsc) \ 315 ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) 316 317 318 #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ 319 (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) 320 #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ 321 (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) 322 #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ 323 (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) 324 325 enum NvmeCmbstsShift { 326 CMBSTS_CBAI_SHIFT = 0, 327 }; 328 enum NvmeCmbstsMask { 329 CMBSTS_CBAI_MASK = 0x1, 330 }; 331 332 #define NVME_CMBSTS_CBAI(cmbsts) \ 333 ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) 334 335 #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ 336 (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) 337 338 enum NvmePmrcapShift { 339 PMRCAP_RDS_SHIFT = 3, 340 PMRCAP_WDS_SHIFT = 4, 341 PMRCAP_BIR_SHIFT = 5, 342 PMRCAP_PMRTU_SHIFT = 8, 343 PMRCAP_PMRWBM_SHIFT = 10, 344 PMRCAP_PMRTO_SHIFT = 16, 345 PMRCAP_CMSS_SHIFT = 24, 346 }; 347 348 enum NvmePmrcapMask { 349 PMRCAP_RDS_MASK = 0x1, 350 PMRCAP_WDS_MASK = 0x1, 351 PMRCAP_BIR_MASK = 0x7, 352 PMRCAP_PMRTU_MASK = 0x3, 353 PMRCAP_PMRWBM_MASK = 0xf, 354 PMRCAP_PMRTO_MASK = 0xff, 355 PMRCAP_CMSS_MASK = 0x1, 356 }; 357 358 #define NVME_PMRCAP_RDS(pmrcap) \ 359 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 360 #define NVME_PMRCAP_WDS(pmrcap) \ 361 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 362 #define NVME_PMRCAP_BIR(pmrcap) \ 363 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 364 #define NVME_PMRCAP_PMRTU(pmrcap) \ 365 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 366 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 367 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 368 #define NVME_PMRCAP_PMRTO(pmrcap) \ 369 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 370 #define NVME_PMRCAP_CMSS(pmrcap) \ 371 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 372 373 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 374 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 375 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 376 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 377 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 378 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 379 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 380 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 381 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 382 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 383 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 384 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 385 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 386 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 387 388 enum NvmePmrctlShift { 389 PMRCTL_EN_SHIFT = 0, 390 }; 391 392 enum NvmePmrctlMask { 393 PMRCTL_EN_MASK = 0x1, 394 }; 395 396 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 397 398 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 399 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 400 401 enum NvmePmrstsShift { 402 PMRSTS_ERR_SHIFT = 0, 403 PMRSTS_NRDY_SHIFT = 8, 404 PMRSTS_HSTS_SHIFT = 9, 405 PMRSTS_CBAI_SHIFT = 12, 406 }; 407 408 enum NvmePmrstsMask { 409 PMRSTS_ERR_MASK = 0xff, 410 PMRSTS_NRDY_MASK = 0x1, 411 PMRSTS_HSTS_MASK = 0x7, 412 PMRSTS_CBAI_MASK = 0x1, 413 }; 414 415 #define NVME_PMRSTS_ERR(pmrsts) \ 416 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 417 #define NVME_PMRSTS_NRDY(pmrsts) \ 418 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 419 #define NVME_PMRSTS_HSTS(pmrsts) \ 420 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 421 #define NVME_PMRSTS_CBAI(pmrsts) \ 422 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 423 424 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 425 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 426 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 427 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 428 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 429 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 430 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 431 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 432 433 enum NvmePmrebsShift { 434 PMREBS_PMRSZU_SHIFT = 0, 435 PMREBS_RBB_SHIFT = 4, 436 PMREBS_PMRWBZ_SHIFT = 8, 437 }; 438 439 enum NvmePmrebsMask { 440 PMREBS_PMRSZU_MASK = 0xf, 441 PMREBS_RBB_MASK = 0x1, 442 PMREBS_PMRWBZ_MASK = 0xffffff, 443 }; 444 445 #define NVME_PMREBS_PMRSZU(pmrebs) \ 446 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 447 #define NVME_PMREBS_RBB(pmrebs) \ 448 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 449 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 450 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 451 452 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 453 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 454 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 455 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 456 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 457 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 458 459 enum NvmePmrswtpShift { 460 PMRSWTP_PMRSWTU_SHIFT = 0, 461 PMRSWTP_PMRSWTV_SHIFT = 8, 462 }; 463 464 enum NvmePmrswtpMask { 465 PMRSWTP_PMRSWTU_MASK = 0xf, 466 PMRSWTP_PMRSWTV_MASK = 0xffffff, 467 }; 468 469 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 470 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 471 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 472 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 473 474 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 475 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 476 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 477 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 478 479 enum NvmePmrmsclShift { 480 PMRMSCL_CMSE_SHIFT = 1, 481 PMRMSCL_CBA_SHIFT = 12, 482 }; 483 484 enum NvmePmrmsclMask { 485 PMRMSCL_CMSE_MASK = 0x1, 486 PMRMSCL_CBA_MASK = 0xfffff, 487 }; 488 489 #define NVME_PMRMSCL_CMSE(pmrmscl) \ 490 ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) 491 #define NVME_PMRMSCL_CBA(pmrmscl) \ 492 ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) 493 494 #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ 495 (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) 496 #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ 497 (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) 498 499 enum NvmeSglDescriptorType { 500 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 501 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 502 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 503 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 504 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 505 506 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 507 }; 508 509 enum NvmeSglDescriptorSubtype { 510 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 511 }; 512 513 typedef struct QEMU_PACKED NvmeSglDescriptor { 514 uint64_t addr; 515 uint32_t len; 516 uint8_t rsvd[3]; 517 uint8_t type; 518 } NvmeSglDescriptor; 519 520 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 521 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 522 523 typedef union NvmeCmdDptr { 524 struct { 525 uint64_t prp1; 526 uint64_t prp2; 527 }; 528 529 NvmeSglDescriptor sgl; 530 } NvmeCmdDptr; 531 532 enum NvmePsdt { 533 NVME_PSDT_PRP = 0x0, 534 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 535 NVME_PSDT_SGL_MPTR_SGL = 0x2, 536 }; 537 538 typedef struct QEMU_PACKED NvmeCmd { 539 uint8_t opcode; 540 uint8_t flags; 541 uint16_t cid; 542 uint32_t nsid; 543 uint64_t res1; 544 uint64_t mptr; 545 NvmeCmdDptr dptr; 546 uint32_t cdw10; 547 uint32_t cdw11; 548 uint32_t cdw12; 549 uint32_t cdw13; 550 uint32_t cdw14; 551 uint32_t cdw15; 552 } NvmeCmd; 553 554 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 555 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 556 557 enum NvmeAdminCommands { 558 NVME_ADM_CMD_DELETE_SQ = 0x00, 559 NVME_ADM_CMD_CREATE_SQ = 0x01, 560 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 561 NVME_ADM_CMD_DELETE_CQ = 0x04, 562 NVME_ADM_CMD_CREATE_CQ = 0x05, 563 NVME_ADM_CMD_IDENTIFY = 0x06, 564 NVME_ADM_CMD_ABORT = 0x08, 565 NVME_ADM_CMD_SET_FEATURES = 0x09, 566 NVME_ADM_CMD_GET_FEATURES = 0x0a, 567 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 568 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 569 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 570 NVME_ADM_CMD_NS_ATTACHMENT = 0x15, 571 NVME_ADM_CMD_FORMAT_NVM = 0x80, 572 NVME_ADM_CMD_SECURITY_SEND = 0x81, 573 NVME_ADM_CMD_SECURITY_RECV = 0x82, 574 }; 575 576 enum NvmeIoCommands { 577 NVME_CMD_FLUSH = 0x00, 578 NVME_CMD_WRITE = 0x01, 579 NVME_CMD_READ = 0x02, 580 NVME_CMD_WRITE_UNCOR = 0x04, 581 NVME_CMD_COMPARE = 0x05, 582 NVME_CMD_WRITE_ZEROES = 0x08, 583 NVME_CMD_DSM = 0x09, 584 NVME_CMD_VERIFY = 0x0c, 585 NVME_CMD_COPY = 0x19, 586 NVME_CMD_ZONE_MGMT_SEND = 0x79, 587 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 588 NVME_CMD_ZONE_APPEND = 0x7d, 589 }; 590 591 typedef struct QEMU_PACKED NvmeDeleteQ { 592 uint8_t opcode; 593 uint8_t flags; 594 uint16_t cid; 595 uint32_t rsvd1[9]; 596 uint16_t qid; 597 uint16_t rsvd10; 598 uint32_t rsvd11[5]; 599 } NvmeDeleteQ; 600 601 typedef struct QEMU_PACKED NvmeCreateCq { 602 uint8_t opcode; 603 uint8_t flags; 604 uint16_t cid; 605 uint32_t rsvd1[5]; 606 uint64_t prp1; 607 uint64_t rsvd8; 608 uint16_t cqid; 609 uint16_t qsize; 610 uint16_t cq_flags; 611 uint16_t irq_vector; 612 uint32_t rsvd12[4]; 613 } NvmeCreateCq; 614 615 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 616 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 617 618 enum NvmeFlagsCq { 619 NVME_CQ_PC = 1, 620 NVME_CQ_IEN = 2, 621 }; 622 623 typedef struct QEMU_PACKED NvmeCreateSq { 624 uint8_t opcode; 625 uint8_t flags; 626 uint16_t cid; 627 uint32_t rsvd1[5]; 628 uint64_t prp1; 629 uint64_t rsvd8; 630 uint16_t sqid; 631 uint16_t qsize; 632 uint16_t sq_flags; 633 uint16_t cqid; 634 uint32_t rsvd12[4]; 635 } NvmeCreateSq; 636 637 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 638 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 639 640 enum NvmeFlagsSq { 641 NVME_SQ_PC = 1, 642 643 NVME_SQ_PRIO_URGENT = 0, 644 NVME_SQ_PRIO_HIGH = 1, 645 NVME_SQ_PRIO_NORMAL = 2, 646 NVME_SQ_PRIO_LOW = 3, 647 }; 648 649 typedef struct QEMU_PACKED NvmeIdentify { 650 uint8_t opcode; 651 uint8_t flags; 652 uint16_t cid; 653 uint32_t nsid; 654 uint64_t rsvd2[2]; 655 uint64_t prp1; 656 uint64_t prp2; 657 uint8_t cns; 658 uint8_t rsvd10; 659 uint16_t ctrlid; 660 uint16_t nvmsetid; 661 uint8_t rsvd11; 662 uint8_t csi; 663 uint32_t rsvd12[4]; 664 } NvmeIdentify; 665 666 typedef struct QEMU_PACKED NvmeRwCmd { 667 uint8_t opcode; 668 uint8_t flags; 669 uint16_t cid; 670 uint32_t nsid; 671 uint64_t rsvd2; 672 uint64_t mptr; 673 NvmeCmdDptr dptr; 674 uint64_t slba; 675 uint16_t nlb; 676 uint16_t control; 677 uint32_t dsmgmt; 678 uint32_t reftag; 679 uint16_t apptag; 680 uint16_t appmask; 681 } NvmeRwCmd; 682 683 enum { 684 NVME_RW_LR = 1 << 15, 685 NVME_RW_FUA = 1 << 14, 686 NVME_RW_DSM_FREQ_UNSPEC = 0, 687 NVME_RW_DSM_FREQ_TYPICAL = 1, 688 NVME_RW_DSM_FREQ_RARE = 2, 689 NVME_RW_DSM_FREQ_READS = 3, 690 NVME_RW_DSM_FREQ_WRITES = 4, 691 NVME_RW_DSM_FREQ_RW = 5, 692 NVME_RW_DSM_FREQ_ONCE = 6, 693 NVME_RW_DSM_FREQ_PREFETCH = 7, 694 NVME_RW_DSM_FREQ_TEMP = 8, 695 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 696 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 697 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 698 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 699 NVME_RW_DSM_SEQ_REQ = 1 << 6, 700 NVME_RW_DSM_COMPRESSED = 1 << 7, 701 NVME_RW_PIREMAP = 1 << 9, 702 NVME_RW_PRINFO_PRACT = 1 << 13, 703 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 704 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 705 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 706 NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, 707 708 }; 709 710 #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) 711 712 enum { 713 NVME_PRINFO_PRACT = 1 << 3, 714 NVME_PRINFO_PRCHK_GUARD = 1 << 2, 715 NVME_PRINFO_PRCHK_APP = 1 << 1, 716 NVME_PRINFO_PRCHK_REF = 1 << 0, 717 NVME_PRINFO_PRCHK_MASK = 7 << 0, 718 }; 719 720 typedef struct QEMU_PACKED NvmeDsmCmd { 721 uint8_t opcode; 722 uint8_t flags; 723 uint16_t cid; 724 uint32_t nsid; 725 uint64_t rsvd2[2]; 726 NvmeCmdDptr dptr; 727 uint32_t nr; 728 uint32_t attributes; 729 uint32_t rsvd12[4]; 730 } NvmeDsmCmd; 731 732 enum { 733 NVME_DSMGMT_IDR = 1 << 0, 734 NVME_DSMGMT_IDW = 1 << 1, 735 NVME_DSMGMT_AD = 1 << 2, 736 }; 737 738 typedef struct QEMU_PACKED NvmeDsmRange { 739 uint32_t cattr; 740 uint32_t nlb; 741 uint64_t slba; 742 } NvmeDsmRange; 743 744 enum { 745 NVME_COPY_FORMAT_0 = 0x0, 746 }; 747 748 typedef struct QEMU_PACKED NvmeCopyCmd { 749 uint8_t opcode; 750 uint8_t flags; 751 uint16_t cid; 752 uint32_t nsid; 753 uint32_t rsvd2[4]; 754 NvmeCmdDptr dptr; 755 uint64_t sdlba; 756 uint8_t nr; 757 uint8_t control[3]; 758 uint16_t rsvd13; 759 uint16_t dspec; 760 uint32_t reftag; 761 uint16_t apptag; 762 uint16_t appmask; 763 } NvmeCopyCmd; 764 765 typedef struct QEMU_PACKED NvmeCopySourceRange { 766 uint8_t rsvd0[8]; 767 uint64_t slba; 768 uint16_t nlb; 769 uint8_t rsvd18[6]; 770 uint32_t reftag; 771 uint16_t apptag; 772 uint16_t appmask; 773 } NvmeCopySourceRange; 774 775 enum NvmeAsyncEventRequest { 776 NVME_AER_TYPE_ERROR = 0, 777 NVME_AER_TYPE_SMART = 1, 778 NVME_AER_TYPE_NOTICE = 2, 779 NVME_AER_TYPE_IO_SPECIFIC = 6, 780 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 781 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 782 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 783 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 784 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 785 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 786 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 787 NVME_AER_INFO_SMART_RELIABILITY = 0, 788 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 789 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 790 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, 791 }; 792 793 typedef struct QEMU_PACKED NvmeAerResult { 794 uint8_t event_type; 795 uint8_t event_info; 796 uint8_t log_page; 797 uint8_t resv; 798 } NvmeAerResult; 799 800 typedef struct QEMU_PACKED NvmeZonedResult { 801 uint64_t slba; 802 } NvmeZonedResult; 803 804 typedef struct QEMU_PACKED NvmeCqe { 805 uint32_t result; 806 uint32_t dw1; 807 uint16_t sq_head; 808 uint16_t sq_id; 809 uint16_t cid; 810 uint16_t status; 811 } NvmeCqe; 812 813 enum NvmeStatusCodes { 814 NVME_SUCCESS = 0x0000, 815 NVME_INVALID_OPCODE = 0x0001, 816 NVME_INVALID_FIELD = 0x0002, 817 NVME_CID_CONFLICT = 0x0003, 818 NVME_DATA_TRAS_ERROR = 0x0004, 819 NVME_POWER_LOSS_ABORT = 0x0005, 820 NVME_INTERNAL_DEV_ERROR = 0x0006, 821 NVME_CMD_ABORT_REQ = 0x0007, 822 NVME_CMD_ABORT_SQ_DEL = 0x0008, 823 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 824 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 825 NVME_INVALID_NSID = 0x000b, 826 NVME_CMD_SEQ_ERROR = 0x000c, 827 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 828 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 829 NVME_DATA_SGL_LEN_INVALID = 0x000f, 830 NVME_MD_SGL_LEN_INVALID = 0x0010, 831 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 832 NVME_INVALID_USE_OF_CMB = 0x0012, 833 NVME_INVALID_PRP_OFFSET = 0x0013, 834 NVME_CMD_SET_CMB_REJECTED = 0x002b, 835 NVME_INVALID_CMD_SET = 0x002c, 836 NVME_LBA_RANGE = 0x0080, 837 NVME_CAP_EXCEEDED = 0x0081, 838 NVME_NS_NOT_READY = 0x0082, 839 NVME_NS_RESV_CONFLICT = 0x0083, 840 NVME_FORMAT_IN_PROGRESS = 0x0084, 841 NVME_INVALID_CQID = 0x0100, 842 NVME_INVALID_QID = 0x0101, 843 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 844 NVME_ACL_EXCEEDED = 0x0103, 845 NVME_RESERVED = 0x0104, 846 NVME_AER_LIMIT_EXCEEDED = 0x0105, 847 NVME_INVALID_FW_SLOT = 0x0106, 848 NVME_INVALID_FW_IMAGE = 0x0107, 849 NVME_INVALID_IRQ_VECTOR = 0x0108, 850 NVME_INVALID_LOG_ID = 0x0109, 851 NVME_INVALID_FORMAT = 0x010a, 852 NVME_FW_REQ_RESET = 0x010b, 853 NVME_INVALID_QUEUE_DEL = 0x010c, 854 NVME_FID_NOT_SAVEABLE = 0x010d, 855 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 856 NVME_FEAT_NOT_NS_SPEC = 0x010f, 857 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 858 NVME_NS_ALREADY_ATTACHED = 0x0118, 859 NVME_NS_PRIVATE = 0x0119, 860 NVME_NS_NOT_ATTACHED = 0x011a, 861 NVME_NS_CTRL_LIST_INVALID = 0x011c, 862 NVME_CONFLICTING_ATTRS = 0x0180, 863 NVME_INVALID_PROT_INFO = 0x0181, 864 NVME_WRITE_TO_RO = 0x0182, 865 NVME_CMD_SIZE_LIMIT = 0x0183, 866 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 867 NVME_ZONE_FULL = 0x01b9, 868 NVME_ZONE_READ_ONLY = 0x01ba, 869 NVME_ZONE_OFFLINE = 0x01bb, 870 NVME_ZONE_INVALID_WRITE = 0x01bc, 871 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 872 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 873 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 874 NVME_WRITE_FAULT = 0x0280, 875 NVME_UNRECOVERED_READ = 0x0281, 876 NVME_E2E_GUARD_ERROR = 0x0282, 877 NVME_E2E_APP_ERROR = 0x0283, 878 NVME_E2E_REF_ERROR = 0x0284, 879 NVME_CMP_FAILURE = 0x0285, 880 NVME_ACCESS_DENIED = 0x0286, 881 NVME_DULB = 0x0287, 882 NVME_MORE = 0x2000, 883 NVME_DNR = 0x4000, 884 NVME_NO_COMPLETE = 0xffff, 885 }; 886 887 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 888 uint8_t afi; 889 uint8_t reserved1[7]; 890 uint8_t frs1[8]; 891 uint8_t frs2[8]; 892 uint8_t frs3[8]; 893 uint8_t frs4[8]; 894 uint8_t frs5[8]; 895 uint8_t frs6[8]; 896 uint8_t frs7[8]; 897 uint8_t reserved2[448]; 898 } NvmeFwSlotInfoLog; 899 900 typedef struct QEMU_PACKED NvmeErrorLog { 901 uint64_t error_count; 902 uint16_t sqid; 903 uint16_t cid; 904 uint16_t status_field; 905 uint16_t param_error_location; 906 uint64_t lba; 907 uint32_t nsid; 908 uint8_t vs; 909 uint8_t resv[35]; 910 } NvmeErrorLog; 911 912 typedef struct QEMU_PACKED NvmeSmartLog { 913 uint8_t critical_warning; 914 uint16_t temperature; 915 uint8_t available_spare; 916 uint8_t available_spare_threshold; 917 uint8_t percentage_used; 918 uint8_t reserved1[26]; 919 uint64_t data_units_read[2]; 920 uint64_t data_units_written[2]; 921 uint64_t host_read_commands[2]; 922 uint64_t host_write_commands[2]; 923 uint64_t controller_busy_time[2]; 924 uint64_t power_cycles[2]; 925 uint64_t power_on_hours[2]; 926 uint64_t unsafe_shutdowns[2]; 927 uint64_t media_errors[2]; 928 uint64_t number_of_error_log_entries[2]; 929 uint8_t reserved2[320]; 930 } NvmeSmartLog; 931 932 #define NVME_SMART_WARN_MAX 6 933 enum NvmeSmartWarn { 934 NVME_SMART_SPARE = 1 << 0, 935 NVME_SMART_TEMPERATURE = 1 << 1, 936 NVME_SMART_RELIABILITY = 1 << 2, 937 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 938 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 939 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 940 }; 941 942 typedef struct NvmeEffectsLog { 943 uint32_t acs[256]; 944 uint32_t iocs[256]; 945 uint8_t resv[2048]; 946 } NvmeEffectsLog; 947 948 enum { 949 NVME_CMD_EFF_CSUPP = 1 << 0, 950 NVME_CMD_EFF_LBCC = 1 << 1, 951 NVME_CMD_EFF_NCC = 1 << 2, 952 NVME_CMD_EFF_NIC = 1 << 3, 953 NVME_CMD_EFF_CCC = 1 << 4, 954 NVME_CMD_EFF_CSE_MASK = 3 << 16, 955 NVME_CMD_EFF_UUID_SEL = 1 << 19, 956 }; 957 958 enum NvmeLogIdentifier { 959 NVME_LOG_ERROR_INFO = 0x01, 960 NVME_LOG_SMART_INFO = 0x02, 961 NVME_LOG_FW_SLOT_INFO = 0x03, 962 NVME_LOG_CHANGED_NSLIST = 0x04, 963 NVME_LOG_CMD_EFFECTS = 0x05, 964 }; 965 966 typedef struct QEMU_PACKED NvmePSD { 967 uint16_t mp; 968 uint16_t reserved; 969 uint32_t enlat; 970 uint32_t exlat; 971 uint8_t rrt; 972 uint8_t rrl; 973 uint8_t rwt; 974 uint8_t rwl; 975 uint8_t resv[16]; 976 } NvmePSD; 977 978 #define NVME_CONTROLLER_LIST_SIZE 2048 979 #define NVME_IDENTIFY_DATA_SIZE 4096 980 981 enum NvmeIdCns { 982 NVME_ID_CNS_NS = 0x00, 983 NVME_ID_CNS_CTRL = 0x01, 984 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 985 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 986 NVME_ID_CNS_CS_NS = 0x05, 987 NVME_ID_CNS_CS_CTRL = 0x06, 988 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 989 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 990 NVME_ID_CNS_NS_PRESENT = 0x11, 991 NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, 992 NVME_ID_CNS_CTRL_LIST = 0x13, 993 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 994 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 995 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 996 }; 997 998 typedef struct QEMU_PACKED NvmeIdCtrl { 999 uint16_t vid; 1000 uint16_t ssvid; 1001 uint8_t sn[20]; 1002 uint8_t mn[40]; 1003 uint8_t fr[8]; 1004 uint8_t rab; 1005 uint8_t ieee[3]; 1006 uint8_t cmic; 1007 uint8_t mdts; 1008 uint16_t cntlid; 1009 uint32_t ver; 1010 uint32_t rtd3r; 1011 uint32_t rtd3e; 1012 uint32_t oaes; 1013 uint32_t ctratt; 1014 uint8_t rsvd100[11]; 1015 uint8_t cntrltype; 1016 uint8_t fguid[16]; 1017 uint8_t rsvd128[128]; 1018 uint16_t oacs; 1019 uint8_t acl; 1020 uint8_t aerl; 1021 uint8_t frmw; 1022 uint8_t lpa; 1023 uint8_t elpe; 1024 uint8_t npss; 1025 uint8_t avscc; 1026 uint8_t apsta; 1027 uint16_t wctemp; 1028 uint16_t cctemp; 1029 uint16_t mtfa; 1030 uint32_t hmpre; 1031 uint32_t hmmin; 1032 uint8_t tnvmcap[16]; 1033 uint8_t unvmcap[16]; 1034 uint32_t rpmbs; 1035 uint16_t edstt; 1036 uint8_t dsto; 1037 uint8_t fwug; 1038 uint16_t kas; 1039 uint16_t hctma; 1040 uint16_t mntmt; 1041 uint16_t mxtmt; 1042 uint32_t sanicap; 1043 uint8_t rsvd332[180]; 1044 uint8_t sqes; 1045 uint8_t cqes; 1046 uint16_t maxcmd; 1047 uint32_t nn; 1048 uint16_t oncs; 1049 uint16_t fuses; 1050 uint8_t fna; 1051 uint8_t vwc; 1052 uint16_t awun; 1053 uint16_t awupf; 1054 uint8_t nvscc; 1055 uint8_t rsvd531; 1056 uint16_t acwu; 1057 uint16_t ocfs; 1058 uint32_t sgls; 1059 uint8_t rsvd540[228]; 1060 uint8_t subnqn[256]; 1061 uint8_t rsvd1024[1024]; 1062 NvmePSD psd[32]; 1063 uint8_t vs[1024]; 1064 } NvmeIdCtrl; 1065 1066 typedef struct NvmeIdCtrlZoned { 1067 uint8_t zasl; 1068 uint8_t rsvd1[4095]; 1069 } NvmeIdCtrlZoned; 1070 1071 typedef struct NvmeIdCtrlNvm { 1072 uint8_t vsl; 1073 uint8_t wzsl; 1074 uint8_t wusl; 1075 uint8_t dmrl; 1076 uint32_t dmrsl; 1077 uint64_t dmsl; 1078 uint8_t rsvd16[4080]; 1079 } NvmeIdCtrlNvm; 1080 1081 enum NvmeIdCtrlOaes { 1082 NVME_OAES_NS_ATTR = 1 << 8, 1083 }; 1084 1085 enum NvmeIdCtrlOacs { 1086 NVME_OACS_SECURITY = 1 << 0, 1087 NVME_OACS_FORMAT = 1 << 1, 1088 NVME_OACS_FW = 1 << 2, 1089 NVME_OACS_NS_MGMT = 1 << 3, 1090 }; 1091 1092 enum NvmeIdCtrlOncs { 1093 NVME_ONCS_COMPARE = 1 << 0, 1094 NVME_ONCS_WRITE_UNCORR = 1 << 1, 1095 NVME_ONCS_DSM = 1 << 2, 1096 NVME_ONCS_WRITE_ZEROES = 1 << 3, 1097 NVME_ONCS_FEATURES = 1 << 4, 1098 NVME_ONCS_RESRVATIONS = 1 << 5, 1099 NVME_ONCS_TIMESTAMP = 1 << 6, 1100 NVME_ONCS_VERIFY = 1 << 7, 1101 NVME_ONCS_COPY = 1 << 8, 1102 }; 1103 1104 enum NvmeIdCtrlOcfs { 1105 NVME_OCFS_COPY_FORMAT_0 = 1 << 0, 1106 }; 1107 1108 enum NvmeIdctrlVwc { 1109 NVME_VWC_PRESENT = 1 << 0, 1110 NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, 1111 NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, 1112 NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, 1113 NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, 1114 }; 1115 1116 enum NvmeIdCtrlFrmw { 1117 NVME_FRMW_SLOT1_RO = 1 << 0, 1118 }; 1119 1120 enum NvmeIdCtrlLpa { 1121 NVME_LPA_NS_SMART = 1 << 0, 1122 NVME_LPA_CSE = 1 << 1, 1123 NVME_LPA_EXTENDED = 1 << 2, 1124 }; 1125 1126 enum NvmeIdCtrlCmic { 1127 NVME_CMIC_MULTI_CTRL = 1 << 1, 1128 }; 1129 1130 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 1131 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 1132 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 1133 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 1134 1135 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 1136 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 1137 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 1138 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 1139 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 1140 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 1141 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 1142 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 1143 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 1144 1145 #define NVME_ARB_AB(arb) (arb & 0x7) 1146 #define NVME_ARB_AB_NOLIMIT 0x7 1147 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 1148 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 1149 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 1150 1151 #define NVME_INTC_THR(intc) (intc & 0xff) 1152 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 1153 1154 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 1155 1156 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 1157 #define NVME_TEMP_THSEL_OVER 0x0 1158 #define NVME_TEMP_THSEL_UNDER 0x1 1159 1160 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 1161 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 1162 1163 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 1164 1165 #define NVME_AEC_SMART(aec) (aec & 0xff) 1166 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 1167 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 1168 1169 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 1170 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 1171 1172 enum NvmeFeatureIds { 1173 NVME_ARBITRATION = 0x1, 1174 NVME_POWER_MANAGEMENT = 0x2, 1175 NVME_LBA_RANGE_TYPE = 0x3, 1176 NVME_TEMPERATURE_THRESHOLD = 0x4, 1177 NVME_ERROR_RECOVERY = 0x5, 1178 NVME_VOLATILE_WRITE_CACHE = 0x6, 1179 NVME_NUMBER_OF_QUEUES = 0x7, 1180 NVME_INTERRUPT_COALESCING = 0x8, 1181 NVME_INTERRUPT_VECTOR_CONF = 0x9, 1182 NVME_WRITE_ATOMICITY = 0xa, 1183 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1184 NVME_TIMESTAMP = 0xe, 1185 NVME_COMMAND_SET_PROFILE = 0x19, 1186 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1187 NVME_FID_MAX = 0x100, 1188 }; 1189 1190 typedef enum NvmeFeatureCap { 1191 NVME_FEAT_CAP_SAVE = 1 << 0, 1192 NVME_FEAT_CAP_NS = 1 << 1, 1193 NVME_FEAT_CAP_CHANGE = 1 << 2, 1194 } NvmeFeatureCap; 1195 1196 typedef enum NvmeGetFeatureSelect { 1197 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1198 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1199 NVME_GETFEAT_SELECT_SAVED = 0x2, 1200 NVME_GETFEAT_SELECT_CAP = 0x3, 1201 } NvmeGetFeatureSelect; 1202 1203 #define NVME_GETSETFEAT_FID_MASK 0xff 1204 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1205 1206 #define NVME_GETFEAT_SELECT_SHIFT 8 1207 #define NVME_GETFEAT_SELECT_MASK 0x7 1208 #define NVME_GETFEAT_SELECT(dw10) \ 1209 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1210 1211 #define NVME_SETFEAT_SAVE_SHIFT 31 1212 #define NVME_SETFEAT_SAVE_MASK 0x1 1213 #define NVME_SETFEAT_SAVE(dw10) \ 1214 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1215 1216 typedef struct QEMU_PACKED NvmeRangeType { 1217 uint8_t type; 1218 uint8_t attributes; 1219 uint8_t rsvd2[14]; 1220 uint64_t slba; 1221 uint64_t nlb; 1222 uint8_t guid[16]; 1223 uint8_t rsvd48[16]; 1224 } NvmeRangeType; 1225 1226 typedef struct QEMU_PACKED NvmeLBAF { 1227 uint16_t ms; 1228 uint8_t ds; 1229 uint8_t rp; 1230 } NvmeLBAF; 1231 1232 typedef struct QEMU_PACKED NvmeLBAFE { 1233 uint64_t zsze; 1234 uint8_t zdes; 1235 uint8_t rsvd9[7]; 1236 } NvmeLBAFE; 1237 1238 #define NVME_NSID_BROADCAST 0xffffffff 1239 1240 typedef struct QEMU_PACKED NvmeIdNs { 1241 uint64_t nsze; 1242 uint64_t ncap; 1243 uint64_t nuse; 1244 uint8_t nsfeat; 1245 uint8_t nlbaf; 1246 uint8_t flbas; 1247 uint8_t mc; 1248 uint8_t dpc; 1249 uint8_t dps; 1250 uint8_t nmic; 1251 uint8_t rescap; 1252 uint8_t fpi; 1253 uint8_t dlfeat; 1254 uint16_t nawun; 1255 uint16_t nawupf; 1256 uint16_t nacwu; 1257 uint16_t nabsn; 1258 uint16_t nabo; 1259 uint16_t nabspf; 1260 uint16_t noiob; 1261 uint8_t nvmcap[16]; 1262 uint16_t npwg; 1263 uint16_t npwa; 1264 uint16_t npdg; 1265 uint16_t npda; 1266 uint16_t nows; 1267 uint16_t mssrl; 1268 uint32_t mcl; 1269 uint8_t msrc; 1270 uint8_t rsvd81[23]; 1271 uint8_t nguid[16]; 1272 uint64_t eui64; 1273 NvmeLBAF lbaf[16]; 1274 uint8_t rsvd192[192]; 1275 uint8_t vs[3712]; 1276 } NvmeIdNs; 1277 1278 typedef struct QEMU_PACKED NvmeIdNsDescr { 1279 uint8_t nidt; 1280 uint8_t nidl; 1281 uint8_t rsvd2[2]; 1282 } NvmeIdNsDescr; 1283 1284 enum NvmeNsIdentifierLength { 1285 NVME_NIDL_EUI64 = 8, 1286 NVME_NIDL_NGUID = 16, 1287 NVME_NIDL_UUID = 16, 1288 NVME_NIDL_CSI = 1, 1289 }; 1290 1291 enum NvmeNsIdentifierType { 1292 NVME_NIDT_EUI64 = 0x01, 1293 NVME_NIDT_NGUID = 0x02, 1294 NVME_NIDT_UUID = 0x03, 1295 NVME_NIDT_CSI = 0x04, 1296 }; 1297 1298 enum NvmeIdNsNmic { 1299 NVME_NMIC_NS_SHARED = 1 << 0, 1300 }; 1301 1302 enum NvmeCsi { 1303 NVME_CSI_NVM = 0x00, 1304 NVME_CSI_ZONED = 0x02, 1305 }; 1306 1307 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1308 1309 typedef struct QEMU_PACKED NvmeIdNsZoned { 1310 uint16_t zoc; 1311 uint16_t ozcs; 1312 uint32_t mar; 1313 uint32_t mor; 1314 uint32_t rrl; 1315 uint32_t frl; 1316 uint8_t rsvd20[2796]; 1317 NvmeLBAFE lbafe[16]; 1318 uint8_t rsvd3072[768]; 1319 uint8_t vs[256]; 1320 } NvmeIdNsZoned; 1321 1322 /*Deallocate Logical Block Features*/ 1323 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1324 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1325 1326 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1327 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1328 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1329 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1330 1331 1332 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1333 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1334 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1335 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1336 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1337 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1338 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1339 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1340 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1341 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1342 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1343 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1344 1345 enum NvmeIdNsDps { 1346 NVME_ID_NS_DPS_TYPE_NONE = 0, 1347 NVME_ID_NS_DPS_TYPE_1 = 1, 1348 NVME_ID_NS_DPS_TYPE_2 = 2, 1349 NVME_ID_NS_DPS_TYPE_3 = 3, 1350 NVME_ID_NS_DPS_TYPE_MASK = 0x7, 1351 NVME_ID_NS_DPS_FIRST_EIGHT = 8, 1352 }; 1353 1354 enum NvmeIdNsFlbas { 1355 NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, 1356 }; 1357 1358 enum NvmeIdNsMc { 1359 NVME_ID_NS_MC_EXTENDED = 1 << 0, 1360 NVME_ID_NS_MC_SEPARATE = 1 << 1, 1361 }; 1362 1363 #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) 1364 1365 typedef struct NvmeDifTuple { 1366 uint16_t guard; 1367 uint16_t apptag; 1368 uint32_t reftag; 1369 } NvmeDifTuple; 1370 1371 enum NvmeZoneAttr { 1372 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1373 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1374 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1375 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1376 }; 1377 1378 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1379 uint64_t nr_zones; 1380 uint8_t rsvd[56]; 1381 } NvmeZoneReportHeader; 1382 1383 enum NvmeZoneReceiveAction { 1384 NVME_ZONE_REPORT = 0, 1385 NVME_ZONE_REPORT_EXTENDED = 1, 1386 }; 1387 1388 enum NvmeZoneReportType { 1389 NVME_ZONE_REPORT_ALL = 0, 1390 NVME_ZONE_REPORT_EMPTY = 1, 1391 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1392 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1393 NVME_ZONE_REPORT_CLOSED = 4, 1394 NVME_ZONE_REPORT_FULL = 5, 1395 NVME_ZONE_REPORT_READ_ONLY = 6, 1396 NVME_ZONE_REPORT_OFFLINE = 7, 1397 }; 1398 1399 enum NvmeZoneType { 1400 NVME_ZONE_TYPE_RESERVED = 0x00, 1401 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1402 }; 1403 1404 enum NvmeZoneSendAction { 1405 NVME_ZONE_ACTION_RSD = 0x00, 1406 NVME_ZONE_ACTION_CLOSE = 0x01, 1407 NVME_ZONE_ACTION_FINISH = 0x02, 1408 NVME_ZONE_ACTION_OPEN = 0x03, 1409 NVME_ZONE_ACTION_RESET = 0x04, 1410 NVME_ZONE_ACTION_OFFLINE = 0x05, 1411 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1412 }; 1413 1414 typedef struct QEMU_PACKED NvmeZoneDescr { 1415 uint8_t zt; 1416 uint8_t zs; 1417 uint8_t za; 1418 uint8_t rsvd3[5]; 1419 uint64_t zcap; 1420 uint64_t zslba; 1421 uint64_t wp; 1422 uint8_t rsvd32[32]; 1423 } NvmeZoneDescr; 1424 1425 typedef enum NvmeZoneState { 1426 NVME_ZONE_STATE_RESERVED = 0x00, 1427 NVME_ZONE_STATE_EMPTY = 0x01, 1428 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1429 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1430 NVME_ZONE_STATE_CLOSED = 0x04, 1431 NVME_ZONE_STATE_READ_ONLY = 0x0d, 1432 NVME_ZONE_STATE_FULL = 0x0e, 1433 NVME_ZONE_STATE_OFFLINE = 0x0f, 1434 } NvmeZoneState; 1435 1436 static inline void _nvme_check_size(void) 1437 { 1438 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1439 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1440 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1441 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1442 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1443 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRange) != 32); 1444 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1445 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1446 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1447 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1448 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1449 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1450 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1451 QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); 1452 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1453 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1454 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1455 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1456 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1457 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1458 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1459 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); 1460 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1461 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1462 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1463 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1464 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1465 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1466 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1467 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 8); 1468 } 1469 #endif 1470