| af1c7f0c | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c: Add hotplug support
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibil
hw/i3c: Add hotplug support
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibility to go through the hot-join and
DAA process so it can participate on the bus.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-20-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| f6e20a54 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c: Add Mock target
Adds a simple i3c device to be used for testing in lieu of a real
device.
The mock target supports the following features:
- A buffer that users can read and write to.
- CCC
hw/i3c: Add Mock target
Adds a simple i3c device to be used for testing in lieu of a real
device.
The mock target supports the following features:
- A buffer that users can read and write to.
- CCC support for commonly used CCCs when probing devices on an I3C bus.
- IBI sending upon receiving a user-defined byte.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-18-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| d9f18868 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/aspeed: Add I3C bus get function
To retrieve the I3C bus object normally, the order is Aspeed I3C -> DW
I3C[n] -> bus object, so make a nice wrapper for people to use.
Signed-off-by: Joe Kom
hw/i3c/aspeed: Add I3C bus get function
To retrieve the I3C bus object normally, the order is Aspeed I3C -> DW
I3C[n] -> bus object, so make a nice wrapper for people to use.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-17-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| e0f10495 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add controller resets
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Step
hw/i3c/dw-i3c: Add controller resets
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-16-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 27258cb0 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add ctrl MMIO handling
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick
hw/i3c/dw-i3c: Add ctrl MMIO handling
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-15-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 3b9e79ae | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add IBI handling
Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bu
hw/i3c/dw-i3c: Add IBI handling
Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bus requesting to be the
primary bus controller
- Handling an interrupt request from a target.
When receiving an IBI, the controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-14-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 59c33d79 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add data TX and RX
This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.
The I3C controller transmits data
hw/i3c/dw-i3c: Add data TX and RX
This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.
The I3C controller transmits data by the user writing into a command
queue. When the queue has a command and an argument in it, the
controller starts executing the command.
The controller can execute 1 of 3 ways:
1. A larger data transfer that involves using the TX and RX queues. This
is the most common way the controller does transactions.
2. A small data transfer that involves sending a couple bytes passed
into the command queue argument.
3. An address assignment command. This is how the controller does
ENTDAA. When ENTDAA succeeds in assigning an address to a target, it
updates the controller's char table with the target's PID, BCR, and
DCR.
The controller determines what addresses to send by looking at the index
in the device address table specified by the argument in the command
queue. ENTDAA also uses these addresses to assign to targets on the bus.
When the controller is done executing a command, it puts a response in
the response queue indicating how command execution went.
In order for the user to send and receive data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-13-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 3ecc1c95 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add IRQ MMIO behavior
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Link: https://lore.k
hw/i3c/dw-i3c: Add IRQ MMIO behavior
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-12-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| fafbebaf | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Use 32 bits on MMIO writes
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi <komlodi@google.com>
hw/i3c/dw-i3c: Use 32 bits on MMIO writes
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-11-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 4a632d68 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Treat more registers as read-as-zero
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link
hw/i3c/dw-i3c: Treat more registers as read-as-zero
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-10-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 97528073 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add register RO field masks
Adds read-only register masks for the DwC I3C controller.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.co
hw/i3c/dw-i3c: Add register RO field masks
Adds read-only register masks for the DwC I3C controller.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-9-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 6d0efcbf | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/aspeed_i3c: Add register RO field masks
Adds read-only register masks for the Aspeed I3C controller registers.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <
hw/i3c/aspeed_i3c: Add register RO field masks
Adds read-only register masks for the Aspeed I3C controller registers.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-8-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 45d91032 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add more reset values
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://
hw/i3c/dw-i3c: Add more reset values
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-7-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| e5b7dca6 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/aspeed_i3c: Add more register fields
Adds the rest of the Aspeed I3C controller register fields.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google
hw/i3c/aspeed_i3c: Add more register fields
Adds the rest of the Aspeed I3C controller register fields.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-6-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 35682b56 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c/dw-i3c: Add more register fields
Adds the rest of the Designware register fields.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: htt
hw/i3c/dw-i3c: Add more register fields
Adds the rest of the Designware register fields.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-5-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 3df01d89 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c: Split DesignWare I3C out of Aspeed I3C
The Aspeed I3C IP block is technically an Aspeed IP block that manages
6 DW I3C controllers.
To help reflect this better and to make it easier for oth
hw/i3c: Split DesignWare I3C out of Aspeed I3C
The Aspeed I3C IP block is technically an Aspeed IP block that manages
6 DW I3C controllers.
To help reflect this better and to make it easier for other SoCs to use
the DW I3C model, we'll split out the DW portion from the Aspeed
portion.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-4-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|
| 98ef6434 | 12-Jun-2025 |
Joe Komlodi <komlodi@google.com> |
hw/i3c: Add bus support
Adds an I3C bus and a target class.
The bus supports:
- I3C data transmission and reception
- CCCs (including ENTDAA)
- IBIs
- legacy I2C transactions
General usage of the b
hw/i3c: Add bus support
Adds an I3C bus and a target class.
The bus supports:
- I3C data transmission and reception
- CCCs (including ENTDAA)
- IBIs
- legacy I2C transactions
General usage of the bus is similar to I2C. Users are expected to
initialize a bus via i3c_init_bus, and use the bus returned from the
init function to do transactions on the bus.
In order to handle IBIs, the controller provides callbacks to handle
receiving an IBI from a target, receiving (optional) additional IBI
bytes from a target, and handling when a target is done with its IBI.
Similarly, target creation is done via i3c_target_create_simple and
users use the provided I3CTarget to handle transactions.
The target has functions provided that it can use to invoke an IBI and
send additional bytes.
Along with the send, recv, and event callbacks that are expected of an
I3C target, which are similar to I2C, there is a separate callback for
CCC handling.
This is to help encapsulate CCC handling and keep it separate from
target-specific read/write functionality.
To avoid repition for required CCCs among I3C targets, there is some
class-level CCC handling added. The CCC is then passed to the target in
case it needs to handle it in some way.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-3-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
|