1 /* 2 * DesignWare I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2025 Google, LLC 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/error-report.h" 13 #include "hw/i3c/i3c.h" 14 #include "hw/i3c/dw-i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 REG32(DEVICE_CTRL, 0x00) 22 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 23 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 24 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 25 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 26 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 27 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 28 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 29 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 30 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 31 REG32(DEVICE_ADDR, 0x04) 32 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 33 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 34 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 35 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 36 REG32(HW_CAPABILITY, 0x08) 37 FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 2) 38 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 39 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 40 REG32(COMMAND_QUEUE_PORT, 0x0c) 41 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 42 /* Transfer command structure */ 43 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 44 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 45 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 46 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 47 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 48 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 49 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 50 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 51 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 52 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 53 /* Transfer argument data structure */ 54 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 55 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 56 /* Short data argument data structure */ 57 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 58 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 59 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 60 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 61 /* Address assignment command structure */ 62 /* 63 * bits 3..21 and 26..31 are the same as the transfer command structure, or 64 * marked as reserved. 65 */ 66 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 67 REG32(RESPONSE_QUEUE_PORT, 0x10) 68 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 69 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 70 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 71 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 72 REG32(RX_TX_DATA_PORT, 0x14) 73 REG32(IBI_QUEUE_STATUS, 0x18) 74 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 75 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 76 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 77 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 78 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 79 REG32(IBI_QUEUE_DATA, 0x18) 80 REG32(QUEUE_THLD_CTRL, 0x1c) 81 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 82 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 83 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 84 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 85 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 86 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 87 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 88 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 89 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 90 REG32(IBI_QUEUE_CTRL, 0x24) 91 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 92 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 93 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 94 REG32(IBI_MR_REQ_REJECT, 0x2c) 95 REG32(IBI_SIR_REQ_REJECT, 0x30) 96 REG32(RESET_CTRL, 0x34) 97 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 98 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 99 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 100 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 101 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 102 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 103 REG32(SLV_EVENT_CTRL, 0x38) 104 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 105 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 106 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 107 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 108 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 109 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 110 REG32(INTR_STATUS, 0x3c) 111 FIELD(INTR_STATUS, TX_THLD, 0, 1) 112 FIELD(INTR_STATUS, RX_THLD, 1, 1) 113 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 114 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 115 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 116 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 117 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 118 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 119 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 120 FIELD(INTR_STATUS, DEFSLV, 10, 1) 121 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 122 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 123 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 124 REG32(INTR_STATUS_EN, 0x40) 125 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 126 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 127 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 128 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 129 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 130 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 131 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 132 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 133 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 134 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 135 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 136 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 137 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 138 REG32(INTR_SIGNAL_EN, 0x44) 139 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 140 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 141 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 142 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 143 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 144 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 145 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 146 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 147 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 148 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 149 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 150 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 151 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 152 REG32(INTR_FORCE, 0x48) 153 FIELD(INTR_FORCE, TX_THLD, 0, 1) 154 FIELD(INTR_FORCE, RX_THLD, 1, 1) 155 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 156 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 157 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 158 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 159 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 160 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 161 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 162 FIELD(INTR_FORCE, DEFSLV, 10, 1) 163 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 164 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 165 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 166 REG32(QUEUE_STATUS_LEVEL, 0x4c) 167 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 168 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 169 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 170 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 171 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 172 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 173 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 174 REG32(PRESENT_STATE, 0x54) 175 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 176 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 177 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 178 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 179 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 180 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 181 REG32(CCC_DEVICE_STATUS, 0x58) 182 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 183 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 184 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 185 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 186 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 187 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 188 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 189 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 190 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 191 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 192 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 193 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 194 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 195 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 196 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 197 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 198 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 199 REG32(SLV_MIPI_PID_VALUE, 0x70) 200 REG32(SLV_PID_VALUE, 0x74) 201 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 202 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 203 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 204 REG32(SLV_CHAR_CTRL, 0x78) 205 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 206 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 207 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 208 REG32(SLV_MAX_LEN, 0x7c) 209 FIELD(SLV_MAX_LEN, MWL, 0, 16) 210 FIELD(SLV_MAX_LEN, MRL, 16, 16) 211 REG32(MAX_READ_TURNAROUND, 0x80) 212 REG32(MAX_DATA_SPEED, 0x84) 213 REG32(SLV_DEBUG_STATUS, 0x88) 214 REG32(SLV_INTR_REQ, 0x8c) 215 FIELD(SLV_INTR_REQ, SIR, 0, 1) 216 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 217 FIELD(SLV_INTR_REQ, MIR, 3, 1) 218 FIELD(SLV_INTR_REQ, TS, 4, 1) 219 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 220 FIELD(SLV_INTR_REQ, MDB, 8, 8) 221 FIELD(SLV_INTR_REQ, SIR_DATA_LEN, 16, 8) 222 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 223 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 224 REG32(SLV_SIR_DATA, 0x94) 225 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE0, 0, 8) 226 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE1, 8, 8) 227 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE2, 16, 8) 228 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE3, 24, 8) 229 REG32(SLV_IBI_RESP, 0x98) 230 FIELD(SLV_IBI_RESP, IBI_STS, 0, 2) 231 FIELD(SLV_IBI_RESP, SIR_RESP_DATA_LEN, 8, 16) 232 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 233 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 234 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 235 REG32(SCL_I3C_OD_TIMING, 0xb4) 236 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 237 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 238 REG32(SCL_I3C_PP_TIMING, 0xb8) 239 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 240 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 241 REG32(SCL_I2C_FM_TIMING, 0xbc) 242 REG32(SCL_I2C_FMP_TIMING, 0xc0) 243 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 244 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 245 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 246 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 247 REG32(BUS_FREE_TIMING, 0xd4) 248 REG32(BUS_IDLE_TIMING, 0xd8) 249 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 250 REG32(I3C_VER_ID, 0xe0) 251 REG32(I3C_VER_TYPE, 0xe4) 252 REG32(EXTENDED_CAPABILITY, 0xe8) 253 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 254 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 255 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 256 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 257 REG32(SLAVE_CONFIG, 0xec) 258 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 259 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 260 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 261 /* Device characteristic table fields */ 262 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 263 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 264 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 265 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 266 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 267 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 268 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 269 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 270 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 271 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 272 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 273 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 274 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 275 /* Dev addr table fields */ 276 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 277 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 278 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 279 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 280 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 281 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 282 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 283 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 284 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 285 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 286 287 static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { 288 /* Target mode is not supported, don't advertise it for now. */ 289 [R_HW_CAPABILITY] = 0x000e00b9, 290 [R_QUEUE_THLD_CTRL] = 0x01000101, 291 [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, 292 [R_SLV_EVENT_CTRL] = 0x0000000b, 293 [R_QUEUE_STATUS_LEVEL] = 0x00000002, 294 [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, 295 [R_PRESENT_STATE] = 0x00000003, 296 [R_I3C_VER_ID] = 0x3130302a, 297 [R_I3C_VER_TYPE] = 0x6c633033, 298 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 299 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 300 [R_SLV_CHAR_CTRL] = 0x00010000, 301 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 302 [R_SLV_MAX_LEN] = 0x00ff00ff, 303 [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, 304 [R_SCL_I3C_OD_TIMING] = 0x000a0010, 305 [R_SCL_I3C_PP_TIMING] = 0x000a000a, 306 [R_SCL_I2C_FM_TIMING] = 0x00100010, 307 [R_SCL_I2C_FMP_TIMING] = 0x00100010, 308 [R_SCL_EXT_LCNT_TIMING] = 0x20202020, 309 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, 310 [R_BUS_FREE_TIMING] = 0x00200020, 311 [R_BUS_IDLE_TIMING] = 0x00000020, 312 [R_EXTENDED_CAPABILITY] = 0x00000239, 313 [R_SLAVE_CONFIG] = 0x00000023, 314 }; 315 316 static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { 317 [R_DEVICE_CTRL] = 0x04fffe00, 318 [R_DEVICE_ADDR] = 0x7f807f80, 319 [R_HW_CAPABILITY] = 0xffffffff, 320 [R_IBI_QUEUE_STATUS] = 0xffffffff, 321 [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, 322 [R_IBI_QUEUE_CTRL] = 0xfffffff0, 323 [R_RESET_CTRL] = 0xffffffc0, 324 [R_SLV_EVENT_CTRL] = 0xffffff3f, 325 [R_INTR_STATUS] = 0xffff809f, 326 [R_INTR_STATUS_EN] = 0xffff8080, 327 [R_INTR_SIGNAL_EN] = 0xffff8080, 328 [R_INTR_FORCE] = 0xffff8000, 329 [R_QUEUE_STATUS_LEVEL] = 0xffffffff, 330 [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, 331 [R_PRESENT_STATE] = 0xffffffff, 332 [R_CCC_DEVICE_STATUS] = 0xffffffff, 333 [R_I3C_VER_ID] = 0xffffffff, 334 [R_I3C_VER_TYPE] = 0xffffffff, 335 [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, 336 [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, 337 [R_SLV_PID_VALUE] = 0xffff0fff, 338 [R_SLV_CHAR_CTRL] = 0xffffffff, 339 [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, 340 [R_SLV_MAX_LEN] = 0xffffffff, 341 [R_MAX_READ_TURNAROUND] = 0xffffffff, 342 [R_MAX_DATA_SPEED] = 0xffffffff, 343 [R_SLV_INTR_REQ] = 0xfffffff0, 344 [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, 345 [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, 346 [R_SCL_I3C_OD_TIMING] = 0xff00ff00, 347 [R_SCL_I3C_PP_TIMING] = 0xff00ff00, 348 [R_SCL_I2C_FMP_TIMING] = 0xff000000, 349 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, 350 [R_BUS_IDLE_TIMING] = 0xfff00000, 351 [R_EXTENDED_CAPABILITY] = 0xffffffff, 352 [R_SLAVE_CONFIG] = 0xffffffff, 353 }; 354 355 static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) 356 { 357 DWI3C *s = DW_I3C(opaque); 358 uint32_t addr = offset >> 2; 359 uint64_t value; 360 361 switch (addr) { 362 /* RAZ */ 363 case R_COMMAND_QUEUE_PORT: 364 case R_RESET_CTRL: 365 case R_INTR_FORCE: 366 value = 0; 367 break; 368 default: 369 value = s->regs[addr]; 370 break; 371 } 372 373 trace_dw_i3c_read(s->id, offset, value); 374 375 return value; 376 } 377 378 static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, 379 unsigned size) 380 { 381 DWI3C *s = DW_I3C(opaque); 382 uint32_t addr = offset >> 2; 383 uint32_t val32 = (uint32_t)value; 384 385 trace_dw_i3c_write(s->id, offset, value); 386 387 val32 &= ~dw_i3c_ro[addr]; 388 switch (addr) { 389 case R_HW_CAPABILITY: 390 case R_RESPONSE_QUEUE_PORT: 391 case R_IBI_QUEUE_DATA: 392 case R_QUEUE_STATUS_LEVEL: 393 case R_PRESENT_STATE: 394 case R_CCC_DEVICE_STATUS: 395 case R_DEVICE_ADDR_TABLE_POINTER: 396 case R_VENDOR_SPECIFIC_REG_POINTER: 397 case R_SLV_CHAR_CTRL: 398 case R_SLV_MAX_LEN: 399 case R_MAX_READ_TURNAROUND: 400 case R_I3C_VER_ID: 401 case R_I3C_VER_TYPE: 402 case R_EXTENDED_CAPABILITY: 403 qemu_log_mask(LOG_GUEST_ERROR, 404 "%s: write to readonly register[0x%02" HWADDR_PRIx 405 "] = 0x%08" PRIx64 "\n", 406 __func__, offset, value); 407 break; 408 case R_RX_TX_DATA_PORT: 409 break; 410 case R_RESET_CTRL: 411 break; 412 default: 413 s->regs[addr] = val32; 414 break; 415 } 416 } 417 418 const VMStateDescription vmstate_dw_i3c = { 419 .name = TYPE_DW_I3C, 420 .version_id = 1, 421 .minimum_version_id = 1, 422 .fields = (VMStateField[]){ 423 VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS), 424 VMSTATE_END_OF_LIST(), 425 } 426 }; 427 428 static const MemoryRegionOps dw_i3c_ops = { 429 .read = dw_i3c_read, 430 .write = dw_i3c_write, 431 .endianness = DEVICE_LITTLE_ENDIAN, 432 }; 433 434 static void dw_i3c_reset_enter(Object *obj, ResetType type) 435 { 436 DWI3C *s = DW_I3C(obj); 437 438 memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); 439 } 440 441 static void dw_i3c_realize(DeviceState *dev, Error **errp) 442 { 443 DWI3C *s = DW_I3C(dev); 444 g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->id); 445 446 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 447 448 memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, 449 DW_I3C_NR_REGS << 2); 450 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 451 } 452 453 static const Property dw_i3c_properties[] = { 454 DEFINE_PROP_UINT8("device-id", DWI3C, id, 0), 455 }; 456 457 static void dw_i3c_class_init(ObjectClass *klass, const void *data) 458 { 459 DeviceClass *dc = DEVICE_CLASS(klass); 460 ResettableClass *rc = RESETTABLE_CLASS(klass); 461 462 rc->phases.enter = dw_i3c_reset_enter; 463 464 dc->desc = "DesignWare I3C Controller"; 465 dc->realize = dw_i3c_realize; 466 dc->vmsd = &vmstate_dw_i3c; 467 device_class_set_props(dc, dw_i3c_properties); 468 } 469 470 static const TypeInfo dw_i3c_info = { 471 .name = TYPE_DW_I3C, 472 .parent = TYPE_SYS_BUS_DEVICE, 473 .instance_size = sizeof(DWI3C), 474 .class_init = dw_i3c_class_init, 475 }; 476 477 static void dw_i3c_register_types(void) 478 { 479 type_register_static(&dw_i3c_info); 480 } 481 482 type_init(dw_i3c_register_types); 483