1 /* 2 * DesignWare I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2025 Google, LLC 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/error-report.h" 13 #include "hw/i3c/i3c.h" 14 #include "hw/i3c/dw-i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 #include "hw/irq.h" 21 22 REG32(DEVICE_CTRL, 0x00) 23 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 24 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 25 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 26 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 27 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 28 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 29 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 30 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 31 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 32 REG32(DEVICE_ADDR, 0x04) 33 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 34 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 35 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 36 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 37 REG32(HW_CAPABILITY, 0x08) 38 FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 2) 39 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 40 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 41 REG32(COMMAND_QUEUE_PORT, 0x0c) 42 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 43 /* Transfer command structure */ 44 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 45 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 46 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 47 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 48 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 49 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 50 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 51 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 52 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 53 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 54 /* Transfer argument data structure */ 55 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 56 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 57 /* Short data argument data structure */ 58 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 59 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 60 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 61 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 62 /* Address assignment command structure */ 63 /* 64 * bits 3..21 and 26..31 are the same as the transfer command structure, or 65 * marked as reserved. 66 */ 67 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 68 REG32(RESPONSE_QUEUE_PORT, 0x10) 69 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 70 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 71 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 72 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 73 REG32(RX_TX_DATA_PORT, 0x14) 74 REG32(IBI_QUEUE_STATUS, 0x18) 75 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 76 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 77 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 78 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 79 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 80 REG32(IBI_QUEUE_DATA, 0x18) 81 REG32(QUEUE_THLD_CTRL, 0x1c) 82 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 83 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 84 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 85 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 86 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 87 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 88 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 89 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 90 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 91 REG32(IBI_QUEUE_CTRL, 0x24) 92 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 93 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 94 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 95 REG32(IBI_MR_REQ_REJECT, 0x2c) 96 REG32(IBI_SIR_REQ_REJECT, 0x30) 97 REG32(RESET_CTRL, 0x34) 98 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 99 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 100 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 101 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 102 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 103 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 104 REG32(SLV_EVENT_CTRL, 0x38) 105 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 106 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 107 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 108 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 109 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 110 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 111 REG32(INTR_STATUS, 0x3c) 112 FIELD(INTR_STATUS, TX_THLD, 0, 1) 113 FIELD(INTR_STATUS, RX_THLD, 1, 1) 114 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 115 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 116 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 117 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 118 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 119 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 120 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 121 FIELD(INTR_STATUS, DEFSLV, 10, 1) 122 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 123 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 124 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 125 REG32(INTR_STATUS_EN, 0x40) 126 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 127 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 128 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 129 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 130 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 131 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 132 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 133 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 134 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 135 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 136 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 137 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 138 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 139 REG32(INTR_SIGNAL_EN, 0x44) 140 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 141 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 142 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 143 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 144 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 145 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 146 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 147 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 148 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 149 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 150 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 151 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 152 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 153 REG32(INTR_FORCE, 0x48) 154 FIELD(INTR_FORCE, TX_THLD, 0, 1) 155 FIELD(INTR_FORCE, RX_THLD, 1, 1) 156 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 157 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 158 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 159 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 160 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 161 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 162 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 163 FIELD(INTR_FORCE, DEFSLV, 10, 1) 164 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 165 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 166 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 167 REG32(QUEUE_STATUS_LEVEL, 0x4c) 168 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 169 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 170 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 171 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 172 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 173 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 174 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 175 REG32(PRESENT_STATE, 0x54) 176 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 177 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 178 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 179 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 180 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 181 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 182 REG32(CCC_DEVICE_STATUS, 0x58) 183 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 184 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 185 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 186 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 187 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 188 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 189 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 190 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 191 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 192 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 193 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 194 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 195 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 196 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 197 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 198 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 199 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 200 REG32(SLV_MIPI_PID_VALUE, 0x70) 201 REG32(SLV_PID_VALUE, 0x74) 202 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 203 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 204 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 205 REG32(SLV_CHAR_CTRL, 0x78) 206 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 207 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 208 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 209 REG32(SLV_MAX_LEN, 0x7c) 210 FIELD(SLV_MAX_LEN, MWL, 0, 16) 211 FIELD(SLV_MAX_LEN, MRL, 16, 16) 212 REG32(MAX_READ_TURNAROUND, 0x80) 213 REG32(MAX_DATA_SPEED, 0x84) 214 REG32(SLV_DEBUG_STATUS, 0x88) 215 REG32(SLV_INTR_REQ, 0x8c) 216 FIELD(SLV_INTR_REQ, SIR, 0, 1) 217 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 218 FIELD(SLV_INTR_REQ, MIR, 3, 1) 219 FIELD(SLV_INTR_REQ, TS, 4, 1) 220 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 221 FIELD(SLV_INTR_REQ, MDB, 8, 8) 222 FIELD(SLV_INTR_REQ, SIR_DATA_LEN, 16, 8) 223 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 224 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 225 REG32(SLV_SIR_DATA, 0x94) 226 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE0, 0, 8) 227 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE1, 8, 8) 228 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE2, 16, 8) 229 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE3, 24, 8) 230 REG32(SLV_IBI_RESP, 0x98) 231 FIELD(SLV_IBI_RESP, IBI_STS, 0, 2) 232 FIELD(SLV_IBI_RESP, SIR_RESP_DATA_LEN, 8, 16) 233 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 234 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 235 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 236 REG32(SCL_I3C_OD_TIMING, 0xb4) 237 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 238 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 239 REG32(SCL_I3C_PP_TIMING, 0xb8) 240 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 241 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 242 REG32(SCL_I2C_FM_TIMING, 0xbc) 243 REG32(SCL_I2C_FMP_TIMING, 0xc0) 244 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 245 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 246 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 247 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 248 REG32(BUS_FREE_TIMING, 0xd4) 249 REG32(BUS_IDLE_TIMING, 0xd8) 250 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 251 REG32(I3C_VER_ID, 0xe0) 252 REG32(I3C_VER_TYPE, 0xe4) 253 REG32(EXTENDED_CAPABILITY, 0xe8) 254 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 255 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 256 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 257 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 258 REG32(SLAVE_CONFIG, 0xec) 259 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 260 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 261 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 262 /* Device characteristic table fields */ 263 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 264 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 265 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 266 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 267 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 268 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 269 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 270 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 271 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 272 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 273 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 274 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 275 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 276 /* Dev addr table fields */ 277 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 278 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 279 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 280 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 281 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 282 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 283 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 284 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 285 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 286 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 287 288 static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { 289 /* Target mode is not supported, don't advertise it for now. */ 290 [R_HW_CAPABILITY] = 0x000e00b9, 291 [R_QUEUE_THLD_CTRL] = 0x01000101, 292 [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, 293 [R_SLV_EVENT_CTRL] = 0x0000000b, 294 [R_QUEUE_STATUS_LEVEL] = 0x00000002, 295 [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, 296 [R_PRESENT_STATE] = 0x00000003, 297 [R_I3C_VER_ID] = 0x3130302a, 298 [R_I3C_VER_TYPE] = 0x6c633033, 299 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 300 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 301 [R_SLV_CHAR_CTRL] = 0x00010000, 302 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 303 [R_SLV_MAX_LEN] = 0x00ff00ff, 304 [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, 305 [R_SCL_I3C_OD_TIMING] = 0x000a0010, 306 [R_SCL_I3C_PP_TIMING] = 0x000a000a, 307 [R_SCL_I2C_FM_TIMING] = 0x00100010, 308 [R_SCL_I2C_FMP_TIMING] = 0x00100010, 309 [R_SCL_EXT_LCNT_TIMING] = 0x20202020, 310 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, 311 [R_BUS_FREE_TIMING] = 0x00200020, 312 [R_BUS_IDLE_TIMING] = 0x00000020, 313 [R_EXTENDED_CAPABILITY] = 0x00000239, 314 [R_SLAVE_CONFIG] = 0x00000023, 315 }; 316 317 static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { 318 [R_DEVICE_CTRL] = 0x04fffe00, 319 [R_DEVICE_ADDR] = 0x7f807f80, 320 [R_HW_CAPABILITY] = 0xffffffff, 321 [R_IBI_QUEUE_STATUS] = 0xffffffff, 322 [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, 323 [R_IBI_QUEUE_CTRL] = 0xfffffff0, 324 [R_RESET_CTRL] = 0xffffffc0, 325 [R_SLV_EVENT_CTRL] = 0xffffff3f, 326 [R_INTR_STATUS] = 0xffff809f, 327 [R_INTR_STATUS_EN] = 0xffff8080, 328 [R_INTR_SIGNAL_EN] = 0xffff8080, 329 [R_INTR_FORCE] = 0xffff8000, 330 [R_QUEUE_STATUS_LEVEL] = 0xffffffff, 331 [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, 332 [R_PRESENT_STATE] = 0xffffffff, 333 [R_CCC_DEVICE_STATUS] = 0xffffffff, 334 [R_I3C_VER_ID] = 0xffffffff, 335 [R_I3C_VER_TYPE] = 0xffffffff, 336 [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, 337 [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, 338 [R_SLV_PID_VALUE] = 0xffff0fff, 339 [R_SLV_CHAR_CTRL] = 0xffffffff, 340 [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, 341 [R_SLV_MAX_LEN] = 0xffffffff, 342 [R_MAX_READ_TURNAROUND] = 0xffffffff, 343 [R_MAX_DATA_SPEED] = 0xffffffff, 344 [R_SLV_INTR_REQ] = 0xfffffff0, 345 [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, 346 [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, 347 [R_SCL_I3C_OD_TIMING] = 0xff00ff00, 348 [R_SCL_I3C_PP_TIMING] = 0xff00ff00, 349 [R_SCL_I2C_FMP_TIMING] = 0xff000000, 350 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, 351 [R_BUS_IDLE_TIMING] = 0xfff00000, 352 [R_EXTENDED_CAPABILITY] = 0xffffffff, 353 [R_SLAVE_CONFIG] = 0xffffffff, 354 }; 355 356 static void dw_i3c_update_irq(DWI3C *s) 357 { 358 bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); 359 qemu_set_irq(s->irq, level); 360 } 361 362 static uint32_t dw_i3c_intr_status_r(DWI3C *s) 363 { 364 /* Only return the status whose corresponding EN bits are set. */ 365 return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; 366 } 367 368 static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) 369 { 370 /* INTR_STATUS[13:5] is w1c, other bits are RO. */ 371 val &= 0x3fe0; 372 s->regs[R_INTR_STATUS] &= ~val; 373 374 dw_i3c_update_irq(s); 375 } 376 377 static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) 378 { 379 s->regs[R_INTR_STATUS_EN] = val; 380 dw_i3c_update_irq(s); 381 } 382 383 static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) 384 { 385 s->regs[R_INTR_SIGNAL_EN] = val; 386 dw_i3c_update_irq(s); 387 } 388 389 static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) 390 { 391 /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ 392 s->regs[R_INTR_STATUS] = val; 393 dw_i3c_update_irq(s); 394 } 395 396 static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) 397 { 398 DWI3C *s = DW_I3C(opaque); 399 uint32_t addr = offset >> 2; 400 uint64_t value; 401 402 switch (addr) { 403 /* RAZ */ 404 case R_COMMAND_QUEUE_PORT: 405 case R_RESET_CTRL: 406 case R_INTR_FORCE: 407 value = 0; 408 break; 409 case R_INTR_STATUS: 410 value = dw_i3c_intr_status_r(s); 411 break; 412 default: 413 value = s->regs[addr]; 414 break; 415 } 416 417 trace_dw_i3c_read(s->id, offset, value); 418 419 return value; 420 } 421 422 static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, 423 unsigned size) 424 { 425 DWI3C *s = DW_I3C(opaque); 426 uint32_t addr = offset >> 2; 427 uint32_t val32 = (uint32_t)value; 428 429 trace_dw_i3c_write(s->id, offset, value); 430 431 val32 &= ~dw_i3c_ro[addr]; 432 switch (addr) { 433 case R_HW_CAPABILITY: 434 case R_RESPONSE_QUEUE_PORT: 435 case R_IBI_QUEUE_DATA: 436 case R_QUEUE_STATUS_LEVEL: 437 case R_PRESENT_STATE: 438 case R_CCC_DEVICE_STATUS: 439 case R_DEVICE_ADDR_TABLE_POINTER: 440 case R_VENDOR_SPECIFIC_REG_POINTER: 441 case R_SLV_CHAR_CTRL: 442 case R_SLV_MAX_LEN: 443 case R_MAX_READ_TURNAROUND: 444 case R_I3C_VER_ID: 445 case R_I3C_VER_TYPE: 446 case R_EXTENDED_CAPABILITY: 447 qemu_log_mask(LOG_GUEST_ERROR, 448 "%s: write to readonly register[0x%02" HWADDR_PRIx 449 "] = 0x%08" PRIx64 "\n", 450 __func__, offset, value); 451 break; 452 case R_RX_TX_DATA_PORT: 453 break; 454 case R_RESET_CTRL: 455 break; 456 case R_INTR_STATUS: 457 dw_i3c_intr_status_w(s, val32); 458 break; 459 case R_INTR_STATUS_EN: 460 dw_i3c_intr_status_en_w(s, val32); 461 break; 462 case R_INTR_SIGNAL_EN: 463 dw_i3c_intr_signal_en_w(s, val32); 464 break; 465 case R_INTR_FORCE: 466 dw_i3c_intr_force_w(s, val32); 467 break; 468 default: 469 s->regs[addr] = val32; 470 break; 471 } 472 } 473 474 const VMStateDescription vmstate_dw_i3c = { 475 .name = TYPE_DW_I3C, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .fields = (VMStateField[]){ 479 VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS), 480 VMSTATE_END_OF_LIST(), 481 } 482 }; 483 484 static const MemoryRegionOps dw_i3c_ops = { 485 .read = dw_i3c_read, 486 .write = dw_i3c_write, 487 .endianness = DEVICE_LITTLE_ENDIAN, 488 }; 489 490 static void dw_i3c_reset_enter(Object *obj, ResetType type) 491 { 492 DWI3C *s = DW_I3C(obj); 493 494 memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); 495 } 496 497 static void dw_i3c_realize(DeviceState *dev, Error **errp) 498 { 499 DWI3C *s = DW_I3C(dev); 500 g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->id); 501 502 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 503 504 memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, 505 DW_I3C_NR_REGS << 2); 506 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 507 } 508 509 static const Property dw_i3c_properties[] = { 510 DEFINE_PROP_UINT8("device-id", DWI3C, id, 0), 511 }; 512 513 static void dw_i3c_class_init(ObjectClass *klass, const void *data) 514 { 515 DeviceClass *dc = DEVICE_CLASS(klass); 516 ResettableClass *rc = RESETTABLE_CLASS(klass); 517 518 rc->phases.enter = dw_i3c_reset_enter; 519 520 dc->desc = "DesignWare I3C Controller"; 521 dc->realize = dw_i3c_realize; 522 dc->vmsd = &vmstate_dw_i3c; 523 device_class_set_props(dc, dw_i3c_properties); 524 } 525 526 static const TypeInfo dw_i3c_info = { 527 .name = TYPE_DW_I3C, 528 .parent = TYPE_SYS_BUS_DEVICE, 529 .instance_size = sizeof(DWI3C), 530 .class_init = dw_i3c_class_init, 531 }; 532 533 static void dw_i3c_register_types(void) 534 { 535 type_register_static(&dw_i3c_info); 536 } 537 538 type_init(dw_i3c_register_types); 539