xref: /openbmc/qemu/target/riscv/insn_trans/trans_rvzicfiss.c.inc (revision 1bbbe7cf2df11a1bc334489a3b87ee23e13c3c29)
1/*
2 * RISC-V translation routines for the Control-Flow Integrity Extension
3 *
4 * Copyright (c) 2024 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#define REQUIRE_ZICFISS(ctx) do {        \
20    if (!ctx->cfg_ptr->ext_zicfiss) {    \
21        return false;                    \
22    }                                    \
23} while (0)
24
25static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
26{
27    if (!ctx->bcfi_enabled) {
28        return false;
29    }
30
31    TCGv addr = tcg_temp_new();
32    TCGLabel *skip = gen_new_label();
33    uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
34    TCGv data = tcg_temp_new();
35    tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
36    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
37    tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx),
38                       mxl_memop(ctx) | MO_ALIGN);
39    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
40    tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);
41    tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL),
42                  tcg_env, offsetof(CPURISCVState, sw_check_code));
43    gen_update_pc(ctx, 0);
44    gen_helper_raise_exception(tcg_env,
45                  tcg_constant_i32(RISCV_EXCP_SW_CHECK));
46    gen_set_label(skip);
47    tcg_gen_addi_tl(addr, addr, tmp);
48    tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
49
50    return true;
51}
52
53static bool trans_sspush(DisasContext *ctx, arg_sspush *a)
54{
55    if (!ctx->bcfi_enabled) {
56        return false;
57    }
58
59    TCGv addr = tcg_temp_new();
60    int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
61    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
62    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
63    tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
64    tcg_gen_addi_tl(addr, addr, tmp);
65    tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx),
66                       mxl_memop(ctx) | MO_ALIGN);
67    tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
68
69    return true;
70}
71
72static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
73{
74    if (!ctx->bcfi_enabled || a->rd == 0) {
75        return false;
76    }
77
78    TCGv dest = dest_gpr(ctx, a->rd);
79    tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp));
80    gen_set_gpr(ctx, a->rd, dest);
81
82    return true;
83}
84
85static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)
86{
87    REQUIRE_A_OR_ZAAMO(ctx);
88    REQUIRE_ZICFISS(ctx);
89    if (ctx->priv == PRV_M) {
90        generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT);
91    }
92
93    if (!ctx->bcfi_enabled) {
94#ifndef CONFIG_USER_ONLY
95        gen_helper_ssamoswap_disabled(tcg_env);
96#else
97        return false;
98#endif
99    }
100
101    TCGv dest = dest_gpr(ctx, a->rd);
102    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
103
104    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
105    src1 = get_address(ctx, a->rs1, 0);
106
107    tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx),
108                           (MO_ALIGN | MO_TESL));
109    gen_set_gpr(ctx, a->rd, dest);
110    return true;
111}
112
113static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)
114{
115    REQUIRE_64BIT(ctx);
116    REQUIRE_A_OR_ZAAMO(ctx);
117    REQUIRE_ZICFISS(ctx);
118    if (ctx->priv == PRV_M) {
119        generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT);
120    }
121
122    if (!ctx->bcfi_enabled) {
123#ifndef CONFIG_USER_ONLY
124        gen_helper_ssamoswap_disabled(tcg_env);
125#else
126        return false;
127#endif
128    }
129
130    TCGv dest = dest_gpr(ctx, a->rd);
131    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
132
133    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
134    src1 = get_address(ctx, a->rs1, 0);
135
136    tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx),
137                           (MO_ALIGN | MO_TESQ));
138    gen_set_gpr(ctx, a->rd, dest);
139    return true;
140}
141