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6886fee4 |
| 24-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: remove obsolete -M, -m, -C, -c options The new --add option has replaced the -M, -m, -C, -c options Eg. -M 0x10 is now --add msr0x10,raw -m 0x10 is no
tools/power turbostat: remove obsolete -M, -m, -C, -c options The new --add option has replaced the -M, -m, -C, -c options Eg. -M 0x10 is now --add msr0x10,raw -m 0x10 is now --add msr0x10,raw,u32 -C 0x10 is now --add msr0x10,delta -c 0x10 is now --add msr0x10,delta,u32 The --add option can be repeated to add any number of counters, while the previous options were limited to adding one of each type. In addition, the --add option can accept a column label, and can also display a counter as a percentage of elapsed cycles. Eg. --add msr0x3fe,core,percent,MY_CC3 Signed-off-by: Len Brown <len.brown@intel.com>
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#
388e9c81 |
| 22-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Make extensible via the --add parameter Create the "--add" parameter. This can be used to teach an existing turbostat binary about any number of any type of count
tools/power turbostat: Make extensible via the --add parameter Create the "--add" parameter. This can be used to teach an existing turbostat binary about any number of any type of counter. turbostat(8) details the syntax for --add. Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: v4.9 |
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#
7268d407 |
| 01-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Denverton uses a 25 MHz crystal, not 19.2 MHz This changes only the TSC frequency decoding line seen with --debug old: TSC: 1382 MHz (19200000 Hz * 216 / 3 /
tools/power turbostat: Denverton uses a 25 MHz crystal, not 19.2 MHz This changes only the TSC frequency decoding line seen with --debug old: TSC: 1382 MHz (19200000 Hz * 216 / 3 / 1000000) new: TSC: 1800 MHz (25000000 Hz * 216 / 3 / 1000000) Signed-off-by: Len Brown <len.brown@intel.com>
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#
5cc6323c |
| 01-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: line up headers when -M is used The -M option adds an 18-column item, and the header needs to be wide enough to keep the header aligned with the columns.
tools/power turbostat: line up headers when -M is used The -M option adds an 18-column item, and the header needs to be wide enough to keep the header aligned with the columns. Signed-off-by: Len Brown <len.brown@intel.com>
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#
d8ebb442 |
| 01-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: fix SKX PKG_CSTATE_LIMIT decoding SKX has fewer package C-states than previous generations, and so the decoding of PKG_CSTATE_LIMIT has changed. This chan
tools/power turbostat: fix SKX PKG_CSTATE_LIMIT decoding SKX has fewer package C-states than previous generations, and so the decoding of PKG_CSTATE_LIMIT has changed. This changes the line ending with pkg-cstate-limit=XXX: pcYYY Signed-off-by: Len Brown <len.brown@intel.com>
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#
005c82d6 |
| 01-Dec-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Support Knights Mill (KNM) Original-author: Piotr Luc <piotr.luc@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: openbmc-4.4-20161121-1, v4.4.33, v4.4.32 |
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#
ddadb8ad |
| 11-Nov-2016 |
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
tools/power turbostat: Display HWP OOB status Display if the HWP is enabled in OOB (Out of band) mode. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> S
tools/power turbostat: Display HWP OOB status Display if the HWP is enabled in OOB (Out of band) mode. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8 |
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#
5bbac26e |
| 30-Sep-2016 |
Xiaolong Wang <xiaolong.wang@linux.intel.com> |
tools/power turbostat: fix Denverton BCLK Add Denverton to the group of SandyBridge and later processors, to let the bclk be recognized as 100MHz rather than 133MHz, then avoid the w
tools/power turbostat: fix Denverton BCLK Add Denverton to the group of SandyBridge and later processors, to let the bclk be recognized as 100MHz rather than 133MHz, then avoid the wrong value of the frequencies based on it, including Bzy_MHz, max efficiency freuency, base frequency, and turbo mode frequencies. Signed-off-by: Xiaolong Wang <xiaolong.wang@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14 |
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#
869ce69e |
| 16-Jun-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: use intel-family.h model strings All except for model 1F, a Nehalem, which is currently incorrectly indentified as a Westmere in that new header. Signed-o
tools/power turbostat: use intel-family.h model strings All except for model 1F, a Nehalem, which is currently incorrectly indentified as a Westmere in that new header. Signed-off-by: Len Brown <len.brown@intel.com>
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#
0f644909 |
| 16-Jun-2016 |
Jacob Pan <jacob.jun.pan@linux.intel.com> |
tools/power/turbostat: Add Denverton RAPL support The Denverton CPU RAPL supports package, core, and DRAM domains. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signe
tools/power/turbostat: Add Denverton RAPL support The Denverton CPU RAPL supports package, core, and DRAM domains. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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#
2c48c990 |
| 16-Jun-2016 |
Jacob Pan <jacob.jun.pan@linux.intel.com> |
tools/power/turbostat: Add Denverton support Denverton is an Atom based micro server which shares the same Goldmont architecture as Broxton. The available C-states on Denverton is a
tools/power/turbostat: Add Denverton support Denverton is an Atom based micro server which shares the same Goldmont architecture as Broxton. The available C-states on Denverton is a subset of Broxton with only C1, C1e, and C6. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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#
9148494c |
| 16-Jun-2016 |
Jacob Pan <jacob.jun.pan@linux.intel.com> |
tools/power/turbostat: split core MSR support into status + limit Some CPUs may not have PP0/Core domain power limit MSRs. We should still allow its domain energy status to be used. This
tools/power/turbostat: split core MSR support into status + limit Some CPUs may not have PP0/Core domain power limit MSRs. We should still allow its domain energy status to be used. This patch splits PP0/Core RAPL into two separate flags for power limit and energy status such that energy status can continue to be reported without power limit. Without this patch, turbostat will not be able to use the remaining RAPL features if some PL MSRs are not present. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9 |
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#
0a91e551 |
| 25-Apr-2016 |
Colin Ian King <colin.king@canonical.com> |
tools/power turbostat: fix error case overflow read of slm_freq_table[] When i >= SLM_BCLK_FREQS, the frequency read from the slm_freq_table is off the end of the array because msr is se
tools/power turbostat: fix error case overflow read of slm_freq_table[] When i >= SLM_BCLK_FREQS, the frequency read from the slm_freq_table is off the end of the array because msr is set to 3 rather than the actual array index i. Set i to 3 rather than msr to fix this. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Len Brown <len.brown@intel.com>
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#
01a67adf |
| 22-Apr-2016 |
Mika Westerberg <mika.westerberg@linux.intel.com> |
tools/power turbostat: Allocate correct amount of fd and irq entries The tool uses topo.max_cpu_num to determine number of entries needed for fd_percpu[] and irqs_per_cpu[]. For example
tools/power turbostat: Allocate correct amount of fd and irq entries The tool uses topo.max_cpu_num to determine number of entries needed for fd_percpu[] and irqs_per_cpu[]. For example on a system with 4 CPUs topo.max_cpu_num is 3 so we get too small array for holding per-CPU items. Fix this to use right number of entries, which is topo.max_cpu_num + 1. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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3d109de2 |
| 22-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: switch to tab delimited output Switch to tab-delimited output from fixed-width columns to make it simpler to import into spreadsheets. As the fixed width
tools/power turbostat: switch to tab delimited output Switch to tab-delimited output from fixed-width columns to make it simpler to import into spreadsheets. As the fixed width columnns were 8-spaces wide, the output on the screen should not change. Signed-off-by: Len Brown <len.brown@intel.com>
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#
ba3dec99 |
| 22-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Gracefully handle ACPI S3 turbostat gives valid results across suspend to idle, aka freeze, whether invoked in interval mode, or in command mode. Indeed, this
tools/power turbostat: Gracefully handle ACPI S3 turbostat gives valid results across suspend to idle, aka freeze, whether invoked in interval mode, or in command mode. Indeed, this can be used to measure suspend to idle: turbostat echo freeze > /sys/power/state But this does not work across suspend to ACPI S3, because the processor counters, including the TSC, are reset on resume. Further, when turbostat detects a problem, it does't forgive the hardware, and interval mode will print *'s from there on out. Instead, upon detecting counters going backwards, simply reset and start over. Interval mode across ACPI S3: (observe TSC going backwards) root@sharkbay:/home/lenb/turbostat-src# ./turbostat -M 0x10 CPU Avg_MHz Busy% Bzy_MHz TSC_MHz MSR 0x010 - 1 0.06 858 2294 0x0000000000000000 0 0 0.06 847 2294 0x0000002a254b98ac 1 1 0.06 878 2294 0x0000002a254efa3a 2 1 0.07 843 2294 0x0000002a2551df65 3 0 0.05 863 2294 0x0000002a2553fea2 turbostat: re-initialized with num_cpus 4 CPU Avg_MHz Busy% Bzy_MHz TSC_MHz MSR 0x010 - 2 0.20 849 2294 0x0000000000000000 0 2 0.26 856 2294 0x0000000449abb60d 1 2 0.20 844 2294 0x0000000449b087ec 2 2 0.21 850 2294 0x0000000449b35d5d 3 1 0.12 839 2294 0x0000000449b5fd5a ^C Command mode across ACPI S3: root@sharkbay:/home/lenb/turbostat-src# ./turbostat -M 0x10 sleep 10 ./turbostat: Counter reset detected 14.196299 sec Signed-off-by: Len Brown <len.brown@intel.com>
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Revision tags: v4.4.8, v4.4.7 |
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#
e975db5d |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: tidy up output on Joule counter overflow The RAPL Joules counter is limited in capacity. Turbostat estimates how soon it can roll-over based on the max TDP of
tools/power turbostat: tidy up output on Joule counter overflow The RAPL Joules counter is limited in capacity. Turbostat estimates how soon it can roll-over based on the max TDP of the processor -- which tells us the maximum increment rate. eg. RAPL: 2759 sec. Joule Counter Range, at 95 Watts So if a sample duration is longer than 2759 seconds on this system, '**' replace the decimal place in the display to indicate that the results may be suspect. But the display had an extra ' ' in this case, throwing off the columns. Also, the -J "Joules" option appended an extra "time" column to the display. While this may be useful, it printed the interval time, which may not be the accurate time per processor. Remove this column, which appeared only when using '-J', as we plan to add accurate per-cpu interval times in a future commit. Signed-off-by: Len Brown <len.brown@intel.com>
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#
ebf5926a |
| 06-Jul-2016 |
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
tools/power turbostat: Replace MSR_NHM_TURBO_RATIO_LIMIT Replace MSR_NHM_TURBO_RATIO_LIMIT with MSR_TURBO_RATIO_LIMIT. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.
tools/power turbostat: Replace MSR_NHM_TURBO_RATIO_LIMIT Replace MSR_NHM_TURBO_RATIO_LIMIT with MSR_TURBO_RATIO_LIMIT. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
73659be7 |
| 08-Apr-2016 |
Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
Merge branches 'pm-core', 'powercap' and 'pm-tools' * pm-core: PM / wakeirq: fix wakeirq setting after wakup re-configuration from sysfs PM / runtime: Document steps for device r
Merge branches 'pm-core', 'powercap' and 'pm-tools' * pm-core: PM / wakeirq: fix wakeirq setting after wakup re-configuration from sysfs PM / runtime: Document steps for device removal * powercap: powercap: intel_rapl: Add missing Haswell model * pm-tools: tools/power turbostat: work around RC6 counter wrap tools/power turbostat: initial KBL support tools/power turbostat: initial SKX support tools/power turbostat: decode BXT TSC frequency via CPUID tools/power turbostat: initial BXT support tools/power turbostat: print IRTL MSRs tools/power turbostat: SGX state should print only if --debug
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#
9185e988 |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: work around RC6 counter wrap Sometimes the rc6 sysfs counter spontaneously resets, causing turbostat prints a very large number as it tries to calcuate % = 100
tools/power turbostat: work around RC6 counter wrap Sometimes the rc6 sysfs counter spontaneously resets, causing turbostat prints a very large number as it tries to calcuate % = 100 * (old - new) / interval When we see (old > new), print ***.**% instead of a bogus huge number. Note that this detection is not fool-proof, as the counter could reset several times and still result in new > old. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
cdc57272 |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: initial KBL support KBL is similar to SKL Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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ec53e594 |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: initial SKX support SKX has a lot in common with HSX Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@int
tools/power turbostat: initial SKX support SKX has a lot in common with HSX Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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#
e8efbc80 |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: decode BXT TSC frequency via CPUID Hard-code BXT ART to 19200MHz, so turbostat --debug can fully enumerate TSC: CPUID(0x15): eax_crystal: 3 ebx_tsc: 186 e
tools/power turbostat: decode BXT TSC frequency via CPUID Hard-code BXT ART to 19200MHz, so turbostat --debug can fully enumerate TSC: CPUID(0x15): eax_crystal: 3 ebx_tsc: 186 ecx_crystal_hz: 0 TSC: 1190 MHz (19200000 Hz * 186 / 3 / 1000000) Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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e4085d54 |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: initial BXT support Broxton has a lot in common with SKL Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki
tools/power turbostat: initial BXT support Broxton has a lot in common with SKL Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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5a63426e |
| 06-Apr-2016 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: print IRTL MSRs Some processors use the Interrupt Response Time Limit (IRTL) MSR value to describe the maximum IRQ response time latency for deep package C-sta
tools/power turbostat: print IRTL MSRs Some processors use the Interrupt Response Time Limit (IRTL) MSR value to describe the maximum IRQ response time latency for deep package C-states. (Though others have the register, but do not use it) Lets print it out to give insight into the cases where it is used. IRTL begain in SNB, with PC3/PC6/PC7, and HSW added PC8/PC9/PC10. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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