1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include <stdarg.h> 25 #include <stdio.h> 26 #include <err.h> 27 #include <unistd.h> 28 #include <sys/types.h> 29 #include <sys/wait.h> 30 #include <sys/stat.h> 31 #include <sys/resource.h> 32 #include <fcntl.h> 33 #include <signal.h> 34 #include <sys/time.h> 35 #include <stdlib.h> 36 #include <getopt.h> 37 #include <dirent.h> 38 #include <string.h> 39 #include <ctype.h> 40 #include <sched.h> 41 #include <time.h> 42 #include <cpuid.h> 43 #include <linux/capability.h> 44 #include <errno.h> 45 46 char *proc_stat = "/proc/stat"; 47 FILE *outf; 48 int *fd_percpu; 49 struct timespec interval_ts = {5, 0}; 50 unsigned int debug; 51 unsigned int rapl_joules; 52 unsigned int summary_only; 53 unsigned int dump_only; 54 unsigned int skip_c0; 55 unsigned int skip_c1; 56 unsigned int do_nhm_cstates; 57 unsigned int do_snb_cstates; 58 unsigned int do_knl_cstates; 59 unsigned int do_pc2; 60 unsigned int do_pc3; 61 unsigned int do_pc6; 62 unsigned int do_pc7; 63 unsigned int do_c8_c9_c10; 64 unsigned int do_skl_residency; 65 unsigned int do_slm_cstates; 66 unsigned int use_c1_residency_msr; 67 unsigned int has_aperf; 68 unsigned int has_epb; 69 unsigned int do_irtl_snb; 70 unsigned int do_irtl_hsw; 71 unsigned int units = 1000000; /* MHz etc */ 72 unsigned int genuine_intel; 73 unsigned int has_invariant_tsc; 74 unsigned int do_nhm_platform_info; 75 unsigned int extra_msr_offset32; 76 unsigned int extra_msr_offset64; 77 unsigned int extra_delta_offset32; 78 unsigned int extra_delta_offset64; 79 unsigned int aperf_mperf_multiplier = 1; 80 int do_irq = 1; 81 int do_smi; 82 double bclk; 83 double base_hz; 84 unsigned int has_base_hz; 85 double tsc_tweak = 1.0; 86 unsigned int show_pkg; 87 unsigned int show_core; 88 unsigned int show_cpu; 89 unsigned int show_pkg_only; 90 unsigned int show_core_only; 91 char *output_buffer, *outp; 92 unsigned int do_rapl; 93 unsigned int do_dts; 94 unsigned int do_ptm; 95 unsigned int do_gfx_rc6_ms; 96 unsigned long long gfx_cur_rc6_ms; 97 unsigned int do_gfx_mhz; 98 unsigned int gfx_cur_mhz; 99 unsigned int tcc_activation_temp; 100 unsigned int tcc_activation_temp_override; 101 double rapl_power_units, rapl_time_units; 102 double rapl_dram_energy_units, rapl_energy_units; 103 double rapl_joule_counter_range; 104 unsigned int do_core_perf_limit_reasons; 105 unsigned int do_gfx_perf_limit_reasons; 106 unsigned int do_ring_perf_limit_reasons; 107 unsigned int crystal_hz; 108 unsigned long long tsc_hz; 109 int base_cpu; 110 double discover_bclk(unsigned int family, unsigned int model); 111 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 112 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 113 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 114 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 115 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 116 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 117 118 #define RAPL_PKG (1 << 0) 119 /* 0x610 MSR_PKG_POWER_LIMIT */ 120 /* 0x611 MSR_PKG_ENERGY_STATUS */ 121 #define RAPL_PKG_PERF_STATUS (1 << 1) 122 /* 0x613 MSR_PKG_PERF_STATUS */ 123 #define RAPL_PKG_POWER_INFO (1 << 2) 124 /* 0x614 MSR_PKG_POWER_INFO */ 125 126 #define RAPL_DRAM (1 << 3) 127 /* 0x618 MSR_DRAM_POWER_LIMIT */ 128 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 129 #define RAPL_DRAM_PERF_STATUS (1 << 4) 130 /* 0x61b MSR_DRAM_PERF_STATUS */ 131 #define RAPL_DRAM_POWER_INFO (1 << 5) 132 /* 0x61c MSR_DRAM_POWER_INFO */ 133 134 #define RAPL_CORES (1 << 6) 135 /* 0x638 MSR_PP0_POWER_LIMIT */ 136 /* 0x639 MSR_PP0_ENERGY_STATUS */ 137 #define RAPL_CORE_POLICY (1 << 7) 138 /* 0x63a MSR_PP0_POLICY */ 139 140 #define RAPL_GFX (1 << 8) 141 /* 0x640 MSR_PP1_POWER_LIMIT */ 142 /* 0x641 MSR_PP1_ENERGY_STATUS */ 143 /* 0x642 MSR_PP1_POLICY */ 144 #define TJMAX_DEFAULT 100 145 146 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 147 148 int aperf_mperf_unstable; 149 int backwards_count; 150 char *progname; 151 152 cpu_set_t *cpu_present_set, *cpu_affinity_set; 153 size_t cpu_present_setsize, cpu_affinity_setsize; 154 155 struct thread_data { 156 unsigned long long tsc; 157 unsigned long long aperf; 158 unsigned long long mperf; 159 unsigned long long c1; 160 unsigned long long extra_msr64; 161 unsigned long long extra_delta64; 162 unsigned long long extra_msr32; 163 unsigned long long extra_delta32; 164 unsigned int irq_count; 165 unsigned int smi_count; 166 unsigned int cpu_id; 167 unsigned int flags; 168 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 169 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 170 } *thread_even, *thread_odd; 171 172 struct core_data { 173 unsigned long long c3; 174 unsigned long long c6; 175 unsigned long long c7; 176 unsigned int core_temp_c; 177 unsigned int core_id; 178 } *core_even, *core_odd; 179 180 struct pkg_data { 181 unsigned long long pc2; 182 unsigned long long pc3; 183 unsigned long long pc6; 184 unsigned long long pc7; 185 unsigned long long pc8; 186 unsigned long long pc9; 187 unsigned long long pc10; 188 unsigned long long pkg_wtd_core_c0; 189 unsigned long long pkg_any_core_c0; 190 unsigned long long pkg_any_gfxe_c0; 191 unsigned long long pkg_both_core_gfxe_c0; 192 unsigned long long gfx_rc6_ms; 193 unsigned int gfx_mhz; 194 unsigned int package_id; 195 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 196 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 197 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 198 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 199 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 200 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 201 unsigned int pkg_temp_c; 202 203 } *package_even, *package_odd; 204 205 #define ODD_COUNTERS thread_odd, core_odd, package_odd 206 #define EVEN_COUNTERS thread_even, core_even, package_even 207 208 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 209 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 210 topo.num_threads_per_core + \ 211 (core_no) * topo.num_threads_per_core + (thread_no)) 212 #define GET_CORE(core_base, core_no, pkg_no) \ 213 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 214 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 215 216 struct system_summary { 217 struct thread_data threads; 218 struct core_data cores; 219 struct pkg_data packages; 220 } sum, average; 221 222 223 struct topo_params { 224 int num_packages; 225 int num_cpus; 226 int num_cores; 227 int max_cpu_num; 228 int num_cores_per_pkg; 229 int num_threads_per_core; 230 } topo; 231 232 struct timeval tv_even, tv_odd, tv_delta; 233 234 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 235 int *irqs_per_cpu; /* indexed by cpu_num */ 236 237 void setup_all_buffers(void); 238 239 int cpu_is_not_present(int cpu) 240 { 241 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 242 } 243 /* 244 * run func(thread, core, package) in topology order 245 * skip non-present cpus 246 */ 247 248 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 249 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 250 { 251 int retval, pkg_no, core_no, thread_no; 252 253 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 254 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 255 for (thread_no = 0; thread_no < 256 topo.num_threads_per_core; ++thread_no) { 257 struct thread_data *t; 258 struct core_data *c; 259 struct pkg_data *p; 260 261 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 262 263 if (cpu_is_not_present(t->cpu_id)) 264 continue; 265 266 c = GET_CORE(core_base, core_no, pkg_no); 267 p = GET_PKG(pkg_base, pkg_no); 268 269 retval = func(t, c, p); 270 if (retval) 271 return retval; 272 } 273 } 274 } 275 return 0; 276 } 277 278 int cpu_migrate(int cpu) 279 { 280 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 281 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 282 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 283 return -1; 284 else 285 return 0; 286 } 287 int get_msr_fd(int cpu) 288 { 289 char pathname[32]; 290 int fd; 291 292 fd = fd_percpu[cpu]; 293 294 if (fd) 295 return fd; 296 297 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 298 fd = open(pathname, O_RDONLY); 299 if (fd < 0) 300 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 301 302 fd_percpu[cpu] = fd; 303 304 return fd; 305 } 306 307 int get_msr(int cpu, off_t offset, unsigned long long *msr) 308 { 309 ssize_t retval; 310 311 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 312 313 if (retval != sizeof *msr) 314 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset); 315 316 return 0; 317 } 318 319 /* 320 * Example Format w/ field column widths: 321 * 322 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt 323 * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 324 */ 325 326 void print_header(void) 327 { 328 if (show_pkg) 329 outp += sprintf(outp, " Package"); 330 if (show_core) 331 outp += sprintf(outp, " Core"); 332 if (show_cpu) 333 outp += sprintf(outp, " CPU"); 334 if (has_aperf) 335 outp += sprintf(outp, " Avg_MHz"); 336 if (has_aperf) 337 outp += sprintf(outp, " Busy%%"); 338 if (has_aperf) 339 outp += sprintf(outp, " Bzy_MHz"); 340 outp += sprintf(outp, " TSC_MHz"); 341 342 if (extra_delta_offset32) 343 outp += sprintf(outp, " count 0x%03X", extra_delta_offset32); 344 if (extra_delta_offset64) 345 outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64); 346 if (extra_msr_offset32) 347 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32); 348 if (extra_msr_offset64) 349 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64); 350 351 if (!debug) 352 goto done; 353 354 if (do_irq) 355 outp += sprintf(outp, " IRQ"); 356 if (do_smi) 357 outp += sprintf(outp, " SMI"); 358 359 if (do_nhm_cstates) 360 outp += sprintf(outp, " CPU%%c1"); 361 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 362 outp += sprintf(outp, " CPU%%c3"); 363 if (do_nhm_cstates) 364 outp += sprintf(outp, " CPU%%c6"); 365 if (do_snb_cstates) 366 outp += sprintf(outp, " CPU%%c7"); 367 368 if (do_dts) 369 outp += sprintf(outp, " CoreTmp"); 370 if (do_ptm) 371 outp += sprintf(outp, " PkgTmp"); 372 373 if (do_gfx_rc6_ms) 374 outp += sprintf(outp, " GFX%%rc6"); 375 376 if (do_gfx_mhz) 377 outp += sprintf(outp, " GFXMHz"); 378 379 if (do_skl_residency) { 380 outp += sprintf(outp, " Totl%%C0"); 381 outp += sprintf(outp, " Any%%C0"); 382 outp += sprintf(outp, " GFX%%C0"); 383 outp += sprintf(outp, " CPUGFX%%"); 384 } 385 386 if (do_pc2) 387 outp += sprintf(outp, " Pkg%%pc2"); 388 if (do_pc3) 389 outp += sprintf(outp, " Pkg%%pc3"); 390 if (do_pc6) 391 outp += sprintf(outp, " Pkg%%pc6"); 392 if (do_pc7) 393 outp += sprintf(outp, " Pkg%%pc7"); 394 if (do_c8_c9_c10) { 395 outp += sprintf(outp, " Pkg%%pc8"); 396 outp += sprintf(outp, " Pkg%%pc9"); 397 outp += sprintf(outp, " Pk%%pc10"); 398 } 399 400 if (do_rapl && !rapl_joules) { 401 if (do_rapl & RAPL_PKG) 402 outp += sprintf(outp, " PkgWatt"); 403 if (do_rapl & RAPL_CORES) 404 outp += sprintf(outp, " CorWatt"); 405 if (do_rapl & RAPL_GFX) 406 outp += sprintf(outp, " GFXWatt"); 407 if (do_rapl & RAPL_DRAM) 408 outp += sprintf(outp, " RAMWatt"); 409 if (do_rapl & RAPL_PKG_PERF_STATUS) 410 outp += sprintf(outp, " PKG_%%"); 411 if (do_rapl & RAPL_DRAM_PERF_STATUS) 412 outp += sprintf(outp, " RAM_%%"); 413 } else if (do_rapl && rapl_joules) { 414 if (do_rapl & RAPL_PKG) 415 outp += sprintf(outp, " Pkg_J"); 416 if (do_rapl & RAPL_CORES) 417 outp += sprintf(outp, " Cor_J"); 418 if (do_rapl & RAPL_GFX) 419 outp += sprintf(outp, " GFX_J"); 420 if (do_rapl & RAPL_DRAM) 421 outp += sprintf(outp, " RAM_J"); 422 if (do_rapl & RAPL_PKG_PERF_STATUS) 423 outp += sprintf(outp, " PKG_%%"); 424 if (do_rapl & RAPL_DRAM_PERF_STATUS) 425 outp += sprintf(outp, " RAM_%%"); 426 outp += sprintf(outp, " time"); 427 428 } 429 done: 430 outp += sprintf(outp, "\n"); 431 } 432 433 int dump_counters(struct thread_data *t, struct core_data *c, 434 struct pkg_data *p) 435 { 436 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 437 438 if (t) { 439 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 440 t->cpu_id, t->flags); 441 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 442 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 443 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 444 outp += sprintf(outp, "c1: %016llX\n", t->c1); 445 outp += sprintf(outp, "msr0x%x: %08llX\n", 446 extra_delta_offset32, t->extra_delta32); 447 outp += sprintf(outp, "msr0x%x: %016llX\n", 448 extra_delta_offset64, t->extra_delta64); 449 outp += sprintf(outp, "msr0x%x: %08llX\n", 450 extra_msr_offset32, t->extra_msr32); 451 outp += sprintf(outp, "msr0x%x: %016llX\n", 452 extra_msr_offset64, t->extra_msr64); 453 if (do_irq) 454 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 455 if (do_smi) 456 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 457 } 458 459 if (c) { 460 outp += sprintf(outp, "core: %d\n", c->core_id); 461 outp += sprintf(outp, "c3: %016llX\n", c->c3); 462 outp += sprintf(outp, "c6: %016llX\n", c->c6); 463 outp += sprintf(outp, "c7: %016llX\n", c->c7); 464 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 465 } 466 467 if (p) { 468 outp += sprintf(outp, "package: %d\n", p->package_id); 469 470 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 471 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 472 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 473 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 474 475 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 476 if (do_pc3) 477 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 478 if (do_pc6) 479 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 480 if (do_pc7) 481 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 482 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 483 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 484 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 485 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 486 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 487 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 488 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 489 outp += sprintf(outp, "Throttle PKG: %0X\n", 490 p->rapl_pkg_perf_status); 491 outp += sprintf(outp, "Throttle RAM: %0X\n", 492 p->rapl_dram_perf_status); 493 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 494 } 495 496 outp += sprintf(outp, "\n"); 497 498 return 0; 499 } 500 501 /* 502 * column formatting convention & formats 503 */ 504 int format_counters(struct thread_data *t, struct core_data *c, 505 struct pkg_data *p) 506 { 507 double interval_float; 508 char *fmt8; 509 510 /* if showing only 1st thread in core and this isn't one, bail out */ 511 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 512 return 0; 513 514 /* if showing only 1st thread in pkg and this isn't one, bail out */ 515 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 516 return 0; 517 518 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 519 520 /* topo columns, print blanks on 1st (average) line */ 521 if (t == &average.threads) { 522 if (show_pkg) 523 outp += sprintf(outp, " -"); 524 if (show_core) 525 outp += sprintf(outp, " -"); 526 if (show_cpu) 527 outp += sprintf(outp, " -"); 528 } else { 529 if (show_pkg) { 530 if (p) 531 outp += sprintf(outp, "%8d", p->package_id); 532 else 533 outp += sprintf(outp, " -"); 534 } 535 if (show_core) { 536 if (c) 537 outp += sprintf(outp, "%8d", c->core_id); 538 else 539 outp += sprintf(outp, " -"); 540 } 541 if (show_cpu) 542 outp += sprintf(outp, "%8d", t->cpu_id); 543 } 544 545 /* Avg_MHz */ 546 if (has_aperf) 547 outp += sprintf(outp, "%8.0f", 548 1.0 / units * t->aperf / interval_float); 549 550 /* Busy% */ 551 if (has_aperf) { 552 if (!skip_c0) 553 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); 554 else 555 outp += sprintf(outp, "********"); 556 } 557 558 /* Bzy_MHz */ 559 if (has_aperf) { 560 if (has_base_hz) 561 outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf); 562 else 563 outp += sprintf(outp, "%8.0f", 564 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); 565 } 566 567 /* TSC_MHz */ 568 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float); 569 570 /* delta */ 571 if (extra_delta_offset32) 572 outp += sprintf(outp, " %11llu", t->extra_delta32); 573 574 /* DELTA */ 575 if (extra_delta_offset64) 576 outp += sprintf(outp, " %11llu", t->extra_delta64); 577 /* msr */ 578 if (extra_msr_offset32) 579 outp += sprintf(outp, " 0x%08llx", t->extra_msr32); 580 581 /* MSR */ 582 if (extra_msr_offset64) 583 outp += sprintf(outp, " 0x%016llx", t->extra_msr64); 584 585 if (!debug) 586 goto done; 587 588 /* IRQ */ 589 if (do_irq) 590 outp += sprintf(outp, "%8d", t->irq_count); 591 592 /* SMI */ 593 if (do_smi) 594 outp += sprintf(outp, "%8d", t->smi_count); 595 596 if (do_nhm_cstates) { 597 if (!skip_c1) 598 outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc); 599 else 600 outp += sprintf(outp, "********"); 601 } 602 603 /* print per-core data only for 1st thread in core */ 604 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 605 goto done; 606 607 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 608 outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc); 609 if (do_nhm_cstates) 610 outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc); 611 if (do_snb_cstates) 612 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc); 613 614 if (do_dts) 615 outp += sprintf(outp, "%8d", c->core_temp_c); 616 617 /* print per-package data only for 1st core in package */ 618 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 619 goto done; 620 621 /* PkgTmp */ 622 if (do_ptm) 623 outp += sprintf(outp, "%8d", p->pkg_temp_c); 624 625 /* GFXrc6 */ 626 if (do_gfx_rc6_ms) 627 outp += sprintf(outp, "%8.2f", 100.0 * p->gfx_rc6_ms / 1000.0 / interval_float); 628 629 /* GFXMHz */ 630 if (do_gfx_mhz) 631 outp += sprintf(outp, "%8d", p->gfx_mhz); 632 633 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 634 if (do_skl_residency) { 635 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); 636 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_core_c0/t->tsc); 637 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); 638 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); 639 } 640 641 if (do_pc2) 642 outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc); 643 if (do_pc3) 644 outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc); 645 if (do_pc6) 646 outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc); 647 if (do_pc7) 648 outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc); 649 if (do_c8_c9_c10) { 650 outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc); 651 outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc); 652 outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc); 653 } 654 655 /* 656 * If measurement interval exceeds minimum RAPL Joule Counter range, 657 * indicate that results are suspect by printing "**" in fraction place. 658 */ 659 if (interval_float < rapl_joule_counter_range) 660 fmt8 = "%8.2f"; 661 else 662 fmt8 = " %6.0f**"; 663 664 if (do_rapl && !rapl_joules) { 665 if (do_rapl & RAPL_PKG) 666 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 667 if (do_rapl & RAPL_CORES) 668 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 669 if (do_rapl & RAPL_GFX) 670 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 671 if (do_rapl & RAPL_DRAM) 672 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 673 if (do_rapl & RAPL_PKG_PERF_STATUS) 674 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 675 if (do_rapl & RAPL_DRAM_PERF_STATUS) 676 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 677 } else if (do_rapl && rapl_joules) { 678 if (do_rapl & RAPL_PKG) 679 outp += sprintf(outp, fmt8, 680 p->energy_pkg * rapl_energy_units); 681 if (do_rapl & RAPL_CORES) 682 outp += sprintf(outp, fmt8, 683 p->energy_cores * rapl_energy_units); 684 if (do_rapl & RAPL_GFX) 685 outp += sprintf(outp, fmt8, 686 p->energy_gfx * rapl_energy_units); 687 if (do_rapl & RAPL_DRAM) 688 outp += sprintf(outp, fmt8, 689 p->energy_dram * rapl_dram_energy_units); 690 if (do_rapl & RAPL_PKG_PERF_STATUS) 691 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 692 if (do_rapl & RAPL_DRAM_PERF_STATUS) 693 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 694 695 outp += sprintf(outp, fmt8, interval_float); 696 } 697 done: 698 outp += sprintf(outp, "\n"); 699 700 return 0; 701 } 702 703 void flush_output_stdout(void) 704 { 705 FILE *filep; 706 707 if (outf == stderr) 708 filep = stdout; 709 else 710 filep = outf; 711 712 fputs(output_buffer, filep); 713 fflush(filep); 714 715 outp = output_buffer; 716 } 717 void flush_output_stderr(void) 718 { 719 fputs(output_buffer, outf); 720 fflush(outf); 721 outp = output_buffer; 722 } 723 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 724 { 725 static int printed; 726 727 if (!printed || !summary_only) 728 print_header(); 729 730 if (topo.num_cpus > 1) 731 format_counters(&average.threads, &average.cores, 732 &average.packages); 733 734 printed = 1; 735 736 if (summary_only) 737 return; 738 739 for_all_cpus(format_counters, t, c, p); 740 } 741 742 #define DELTA_WRAP32(new, old) \ 743 if (new > old) { \ 744 old = new - old; \ 745 } else { \ 746 old = 0x100000000 + new - old; \ 747 } 748 749 void 750 delta_package(struct pkg_data *new, struct pkg_data *old) 751 { 752 753 if (do_skl_residency) { 754 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 755 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 756 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 757 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 758 } 759 old->pc2 = new->pc2 - old->pc2; 760 if (do_pc3) 761 old->pc3 = new->pc3 - old->pc3; 762 if (do_pc6) 763 old->pc6 = new->pc6 - old->pc6; 764 if (do_pc7) 765 old->pc7 = new->pc7 - old->pc7; 766 old->pc8 = new->pc8 - old->pc8; 767 old->pc9 = new->pc9 - old->pc9; 768 old->pc10 = new->pc10 - old->pc10; 769 old->pkg_temp_c = new->pkg_temp_c; 770 771 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 772 old->gfx_mhz = new->gfx_mhz; 773 774 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 775 DELTA_WRAP32(new->energy_cores, old->energy_cores); 776 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 777 DELTA_WRAP32(new->energy_dram, old->energy_dram); 778 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 779 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 780 } 781 782 void 783 delta_core(struct core_data *new, struct core_data *old) 784 { 785 old->c3 = new->c3 - old->c3; 786 old->c6 = new->c6 - old->c6; 787 old->c7 = new->c7 - old->c7; 788 old->core_temp_c = new->core_temp_c; 789 } 790 791 /* 792 * old = new - old 793 */ 794 void 795 delta_thread(struct thread_data *new, struct thread_data *old, 796 struct core_data *core_delta) 797 { 798 old->tsc = new->tsc - old->tsc; 799 800 /* check for TSC < 1 Mcycles over interval */ 801 if (old->tsc < (1000 * 1000)) 802 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 803 "You can disable all c-states by booting with \"idle=poll\"\n" 804 "or just the deep ones with \"processor.max_cstate=1\""); 805 806 old->c1 = new->c1 - old->c1; 807 808 if (has_aperf) { 809 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 810 old->aperf = new->aperf - old->aperf; 811 old->mperf = new->mperf - old->mperf; 812 } else { 813 814 if (!aperf_mperf_unstable) { 815 fprintf(outf, "%s: APERF or MPERF went backwards *\n", progname); 816 fprintf(outf, "* Frequency results do not cover entire interval *\n"); 817 fprintf(outf, "* fix this by running Linux-2.6.30 or later *\n"); 818 819 aperf_mperf_unstable = 1; 820 } 821 /* 822 * mperf delta is likely a huge "positive" number 823 * can not use it for calculating c0 time 824 */ 825 skip_c0 = 1; 826 skip_c1 = 1; 827 } 828 } 829 830 831 if (use_c1_residency_msr) { 832 /* 833 * Some models have a dedicated C1 residency MSR, 834 * which should be more accurate than the derivation below. 835 */ 836 } else { 837 /* 838 * As counter collection is not atomic, 839 * it is possible for mperf's non-halted cycles + idle states 840 * to exceed TSC's all cycles: show c1 = 0% in that case. 841 */ 842 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 843 old->c1 = 0; 844 else { 845 /* normal case, derive c1 */ 846 old->c1 = old->tsc - old->mperf - core_delta->c3 847 - core_delta->c6 - core_delta->c7; 848 } 849 } 850 851 if (old->mperf == 0) { 852 if (debug > 1) 853 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 854 old->mperf = 1; /* divide by 0 protection */ 855 } 856 857 old->extra_delta32 = new->extra_delta32 - old->extra_delta32; 858 old->extra_delta32 &= 0xFFFFFFFF; 859 860 old->extra_delta64 = new->extra_delta64 - old->extra_delta64; 861 862 /* 863 * Extra MSR is just a snapshot, simply copy latest w/o subtracting 864 */ 865 old->extra_msr32 = new->extra_msr32; 866 old->extra_msr64 = new->extra_msr64; 867 868 if (do_irq) 869 old->irq_count = new->irq_count - old->irq_count; 870 871 if (do_smi) 872 old->smi_count = new->smi_count - old->smi_count; 873 } 874 875 int delta_cpu(struct thread_data *t, struct core_data *c, 876 struct pkg_data *p, struct thread_data *t2, 877 struct core_data *c2, struct pkg_data *p2) 878 { 879 /* calculate core delta only for 1st thread in core */ 880 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 881 delta_core(c, c2); 882 883 /* always calculate thread delta */ 884 delta_thread(t, t2, c2); /* c2 is core delta */ 885 886 /* calculate package delta only for 1st core in package */ 887 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 888 delta_package(p, p2); 889 890 return 0; 891 } 892 893 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 894 { 895 t->tsc = 0; 896 t->aperf = 0; 897 t->mperf = 0; 898 t->c1 = 0; 899 900 t->extra_delta32 = 0; 901 t->extra_delta64 = 0; 902 903 t->irq_count = 0; 904 t->smi_count = 0; 905 906 /* tells format_counters to dump all fields from this set */ 907 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 908 909 c->c3 = 0; 910 c->c6 = 0; 911 c->c7 = 0; 912 c->core_temp_c = 0; 913 914 p->pkg_wtd_core_c0 = 0; 915 p->pkg_any_core_c0 = 0; 916 p->pkg_any_gfxe_c0 = 0; 917 p->pkg_both_core_gfxe_c0 = 0; 918 919 p->pc2 = 0; 920 if (do_pc3) 921 p->pc3 = 0; 922 if (do_pc6) 923 p->pc6 = 0; 924 if (do_pc7) 925 p->pc7 = 0; 926 p->pc8 = 0; 927 p->pc9 = 0; 928 p->pc10 = 0; 929 930 p->energy_pkg = 0; 931 p->energy_dram = 0; 932 p->energy_cores = 0; 933 p->energy_gfx = 0; 934 p->rapl_pkg_perf_status = 0; 935 p->rapl_dram_perf_status = 0; 936 p->pkg_temp_c = 0; 937 938 p->gfx_rc6_ms = 0; 939 p->gfx_mhz = 0; 940 } 941 int sum_counters(struct thread_data *t, struct core_data *c, 942 struct pkg_data *p) 943 { 944 average.threads.tsc += t->tsc; 945 average.threads.aperf += t->aperf; 946 average.threads.mperf += t->mperf; 947 average.threads.c1 += t->c1; 948 949 average.threads.extra_delta32 += t->extra_delta32; 950 average.threads.extra_delta64 += t->extra_delta64; 951 952 average.threads.irq_count += t->irq_count; 953 average.threads.smi_count += t->smi_count; 954 955 /* sum per-core values only for 1st thread in core */ 956 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 957 return 0; 958 959 average.cores.c3 += c->c3; 960 average.cores.c6 += c->c6; 961 average.cores.c7 += c->c7; 962 963 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 964 965 /* sum per-pkg values only for 1st core in pkg */ 966 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 967 return 0; 968 969 if (do_skl_residency) { 970 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 971 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 972 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 973 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 974 } 975 976 average.packages.pc2 += p->pc2; 977 if (do_pc3) 978 average.packages.pc3 += p->pc3; 979 if (do_pc6) 980 average.packages.pc6 += p->pc6; 981 if (do_pc7) 982 average.packages.pc7 += p->pc7; 983 average.packages.pc8 += p->pc8; 984 average.packages.pc9 += p->pc9; 985 average.packages.pc10 += p->pc10; 986 987 average.packages.energy_pkg += p->energy_pkg; 988 average.packages.energy_dram += p->energy_dram; 989 average.packages.energy_cores += p->energy_cores; 990 average.packages.energy_gfx += p->energy_gfx; 991 992 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 993 average.packages.gfx_mhz = p->gfx_mhz; 994 995 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 996 997 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 998 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 999 return 0; 1000 } 1001 /* 1002 * sum the counters for all cpus in the system 1003 * compute the weighted average 1004 */ 1005 void compute_average(struct thread_data *t, struct core_data *c, 1006 struct pkg_data *p) 1007 { 1008 clear_counters(&average.threads, &average.cores, &average.packages); 1009 1010 for_all_cpus(sum_counters, t, c, p); 1011 1012 average.threads.tsc /= topo.num_cpus; 1013 average.threads.aperf /= topo.num_cpus; 1014 average.threads.mperf /= topo.num_cpus; 1015 average.threads.c1 /= topo.num_cpus; 1016 1017 average.threads.extra_delta32 /= topo.num_cpus; 1018 average.threads.extra_delta32 &= 0xFFFFFFFF; 1019 1020 average.threads.extra_delta64 /= topo.num_cpus; 1021 1022 average.cores.c3 /= topo.num_cores; 1023 average.cores.c6 /= topo.num_cores; 1024 average.cores.c7 /= topo.num_cores; 1025 1026 if (do_skl_residency) { 1027 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1028 average.packages.pkg_any_core_c0 /= topo.num_packages; 1029 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1030 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1031 } 1032 1033 average.packages.pc2 /= topo.num_packages; 1034 if (do_pc3) 1035 average.packages.pc3 /= topo.num_packages; 1036 if (do_pc6) 1037 average.packages.pc6 /= topo.num_packages; 1038 if (do_pc7) 1039 average.packages.pc7 /= topo.num_packages; 1040 1041 average.packages.pc8 /= topo.num_packages; 1042 average.packages.pc9 /= topo.num_packages; 1043 average.packages.pc10 /= topo.num_packages; 1044 } 1045 1046 static unsigned long long rdtsc(void) 1047 { 1048 unsigned int low, high; 1049 1050 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1051 1052 return low | ((unsigned long long)high) << 32; 1053 } 1054 1055 /* 1056 * get_counters(...) 1057 * migrate to cpu 1058 * acquire and record local counters for that cpu 1059 */ 1060 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1061 { 1062 int cpu = t->cpu_id; 1063 unsigned long long msr; 1064 int aperf_mperf_retry_count = 0; 1065 1066 if (cpu_migrate(cpu)) { 1067 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1068 return -1; 1069 } 1070 1071 retry: 1072 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1073 1074 if (has_aperf) { 1075 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1076 1077 /* 1078 * The TSC, APERF and MPERF must be read together for 1079 * APERF/MPERF and MPERF/TSC to give accurate results. 1080 * 1081 * Unfortunately, APERF and MPERF are read by 1082 * individual system call, so delays may occur 1083 * between them. If the time to read them 1084 * varies by a large amount, we re-read them. 1085 */ 1086 1087 /* 1088 * This initial dummy APERF read has been seen to 1089 * reduce jitter in the subsequent reads. 1090 */ 1091 1092 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1093 return -3; 1094 1095 t->tsc = rdtsc(); /* re-read close to APERF */ 1096 1097 tsc_before = t->tsc; 1098 1099 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1100 return -3; 1101 1102 tsc_between = rdtsc(); 1103 1104 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1105 return -4; 1106 1107 tsc_after = rdtsc(); 1108 1109 aperf_time = tsc_between - tsc_before; 1110 mperf_time = tsc_after - tsc_between; 1111 1112 /* 1113 * If the system call latency to read APERF and MPERF 1114 * differ by more than 2x, then try again. 1115 */ 1116 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1117 aperf_mperf_retry_count++; 1118 if (aperf_mperf_retry_count < 5) 1119 goto retry; 1120 else 1121 warnx("cpu%d jitter %lld %lld", 1122 cpu, aperf_time, mperf_time); 1123 } 1124 aperf_mperf_retry_count = 0; 1125 1126 t->aperf = t->aperf * aperf_mperf_multiplier; 1127 t->mperf = t->mperf * aperf_mperf_multiplier; 1128 } 1129 1130 if (do_irq) 1131 t->irq_count = irqs_per_cpu[cpu]; 1132 if (do_smi) { 1133 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1134 return -5; 1135 t->smi_count = msr & 0xFFFFFFFF; 1136 } 1137 if (extra_delta_offset32) { 1138 if (get_msr(cpu, extra_delta_offset32, &msr)) 1139 return -5; 1140 t->extra_delta32 = msr & 0xFFFFFFFF; 1141 } 1142 1143 if (extra_delta_offset64) 1144 if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64)) 1145 return -5; 1146 1147 if (extra_msr_offset32) { 1148 if (get_msr(cpu, extra_msr_offset32, &msr)) 1149 return -5; 1150 t->extra_msr32 = msr & 0xFFFFFFFF; 1151 } 1152 1153 if (extra_msr_offset64) 1154 if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64)) 1155 return -5; 1156 1157 if (use_c1_residency_msr) { 1158 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1159 return -6; 1160 } 1161 1162 /* collect core counters only for 1st thread in core */ 1163 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1164 return 0; 1165 1166 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) { 1167 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1168 return -6; 1169 } 1170 1171 if (do_nhm_cstates && !do_knl_cstates) { 1172 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1173 return -7; 1174 } else if (do_knl_cstates) { 1175 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1176 return -7; 1177 } 1178 1179 if (do_snb_cstates) 1180 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1181 return -8; 1182 1183 if (do_dts) { 1184 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1185 return -9; 1186 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1187 } 1188 1189 1190 /* collect package counters only for 1st core in package */ 1191 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1192 return 0; 1193 1194 if (do_skl_residency) { 1195 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1196 return -10; 1197 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1198 return -11; 1199 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1200 return -12; 1201 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1202 return -13; 1203 } 1204 if (do_pc3) 1205 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1206 return -9; 1207 if (do_pc6) 1208 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1209 return -10; 1210 if (do_pc2) 1211 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1212 return -11; 1213 if (do_pc7) 1214 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1215 return -12; 1216 if (do_c8_c9_c10) { 1217 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1218 return -13; 1219 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1220 return -13; 1221 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1222 return -13; 1223 } 1224 if (do_rapl & RAPL_PKG) { 1225 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1226 return -13; 1227 p->energy_pkg = msr & 0xFFFFFFFF; 1228 } 1229 if (do_rapl & RAPL_CORES) { 1230 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1231 return -14; 1232 p->energy_cores = msr & 0xFFFFFFFF; 1233 } 1234 if (do_rapl & RAPL_DRAM) { 1235 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1236 return -15; 1237 p->energy_dram = msr & 0xFFFFFFFF; 1238 } 1239 if (do_rapl & RAPL_GFX) { 1240 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1241 return -16; 1242 p->energy_gfx = msr & 0xFFFFFFFF; 1243 } 1244 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1245 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1246 return -16; 1247 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1248 } 1249 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1250 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1251 return -16; 1252 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1253 } 1254 if (do_ptm) { 1255 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1256 return -17; 1257 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1258 } 1259 1260 if (do_gfx_rc6_ms) 1261 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1262 1263 if (do_gfx_mhz) 1264 p->gfx_mhz = gfx_cur_mhz; 1265 1266 return 0; 1267 } 1268 1269 /* 1270 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1271 * If you change the values, note they are used both in comparisons 1272 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1273 */ 1274 1275 #define PCLUKN 0 /* Unknown */ 1276 #define PCLRSV 1 /* Reserved */ 1277 #define PCL__0 2 /* PC0 */ 1278 #define PCL__1 3 /* PC1 */ 1279 #define PCL__2 4 /* PC2 */ 1280 #define PCL__3 5 /* PC3 */ 1281 #define PCL__4 6 /* PC4 */ 1282 #define PCL__6 7 /* PC6 */ 1283 #define PCL_6N 8 /* PC6 No Retention */ 1284 #define PCL_6R 9 /* PC6 Retention */ 1285 #define PCL__7 10 /* PC7 */ 1286 #define PCL_7S 11 /* PC7 Shrink */ 1287 #define PCL__8 12 /* PC8 */ 1288 #define PCL__9 13 /* PC9 */ 1289 #define PCLUNL 14 /* Unlimited */ 1290 1291 int pkg_cstate_limit = PCLUKN; 1292 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1293 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1294 1295 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1296 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1297 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1298 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1299 int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1300 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1301 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1302 1303 1304 static void 1305 calculate_tsc_tweak() 1306 { 1307 tsc_tweak = base_hz / tsc_hz; 1308 } 1309 1310 static void 1311 dump_nhm_platform_info(void) 1312 { 1313 unsigned long long msr; 1314 unsigned int ratio; 1315 1316 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1317 1318 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1319 1320 ratio = (msr >> 40) & 0xFF; 1321 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", 1322 ratio, bclk, ratio * bclk); 1323 1324 ratio = (msr >> 8) & 0xFF; 1325 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", 1326 ratio, bclk, ratio * bclk); 1327 1328 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1329 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1330 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1331 1332 return; 1333 } 1334 1335 static void 1336 dump_hsw_turbo_ratio_limits(void) 1337 { 1338 unsigned long long msr; 1339 unsigned int ratio; 1340 1341 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1342 1343 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1344 1345 ratio = (msr >> 8) & 0xFF; 1346 if (ratio) 1347 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", 1348 ratio, bclk, ratio * bclk); 1349 1350 ratio = (msr >> 0) & 0xFF; 1351 if (ratio) 1352 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", 1353 ratio, bclk, ratio * bclk); 1354 return; 1355 } 1356 1357 static void 1358 dump_ivt_turbo_ratio_limits(void) 1359 { 1360 unsigned long long msr; 1361 unsigned int ratio; 1362 1363 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1364 1365 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1366 1367 ratio = (msr >> 56) & 0xFF; 1368 if (ratio) 1369 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", 1370 ratio, bclk, ratio * bclk); 1371 1372 ratio = (msr >> 48) & 0xFF; 1373 if (ratio) 1374 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", 1375 ratio, bclk, ratio * bclk); 1376 1377 ratio = (msr >> 40) & 0xFF; 1378 if (ratio) 1379 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", 1380 ratio, bclk, ratio * bclk); 1381 1382 ratio = (msr >> 32) & 0xFF; 1383 if (ratio) 1384 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", 1385 ratio, bclk, ratio * bclk); 1386 1387 ratio = (msr >> 24) & 0xFF; 1388 if (ratio) 1389 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", 1390 ratio, bclk, ratio * bclk); 1391 1392 ratio = (msr >> 16) & 0xFF; 1393 if (ratio) 1394 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", 1395 ratio, bclk, ratio * bclk); 1396 1397 ratio = (msr >> 8) & 0xFF; 1398 if (ratio) 1399 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", 1400 ratio, bclk, ratio * bclk); 1401 1402 ratio = (msr >> 0) & 0xFF; 1403 if (ratio) 1404 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", 1405 ratio, bclk, ratio * bclk); 1406 return; 1407 } 1408 1409 static void 1410 dump_nhm_turbo_ratio_limits(void) 1411 { 1412 unsigned long long msr; 1413 unsigned int ratio; 1414 1415 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1416 1417 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1418 1419 ratio = (msr >> 56) & 0xFF; 1420 if (ratio) 1421 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", 1422 ratio, bclk, ratio * bclk); 1423 1424 ratio = (msr >> 48) & 0xFF; 1425 if (ratio) 1426 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", 1427 ratio, bclk, ratio * bclk); 1428 1429 ratio = (msr >> 40) & 0xFF; 1430 if (ratio) 1431 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", 1432 ratio, bclk, ratio * bclk); 1433 1434 ratio = (msr >> 32) & 0xFF; 1435 if (ratio) 1436 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", 1437 ratio, bclk, ratio * bclk); 1438 1439 ratio = (msr >> 24) & 0xFF; 1440 if (ratio) 1441 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", 1442 ratio, bclk, ratio * bclk); 1443 1444 ratio = (msr >> 16) & 0xFF; 1445 if (ratio) 1446 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", 1447 ratio, bclk, ratio * bclk); 1448 1449 ratio = (msr >> 8) & 0xFF; 1450 if (ratio) 1451 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", 1452 ratio, bclk, ratio * bclk); 1453 1454 ratio = (msr >> 0) & 0xFF; 1455 if (ratio) 1456 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", 1457 ratio, bclk, ratio * bclk); 1458 return; 1459 } 1460 1461 static void 1462 dump_knl_turbo_ratio_limits(void) 1463 { 1464 const unsigned int buckets_no = 7; 1465 1466 unsigned long long msr; 1467 int delta_cores, delta_ratio; 1468 int i, b_nr; 1469 unsigned int cores[buckets_no]; 1470 unsigned int ratio[buckets_no]; 1471 1472 get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr); 1473 1474 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1475 base_cpu, msr); 1476 1477 /** 1478 * Turbo encoding in KNL is as follows: 1479 * [0] -- Reserved 1480 * [7:1] -- Base value of number of active cores of bucket 1. 1481 * [15:8] -- Base value of freq ratio of bucket 1. 1482 * [20:16] -- +ve delta of number of active cores of bucket 2. 1483 * i.e. active cores of bucket 2 = 1484 * active cores of bucket 1 + delta 1485 * [23:21] -- Negative delta of freq ratio of bucket 2. 1486 * i.e. freq ratio of bucket 2 = 1487 * freq ratio of bucket 1 - delta 1488 * [28:24]-- +ve delta of number of active cores of bucket 3. 1489 * [31:29]-- -ve delta of freq ratio of bucket 3. 1490 * [36:32]-- +ve delta of number of active cores of bucket 4. 1491 * [39:37]-- -ve delta of freq ratio of bucket 4. 1492 * [44:40]-- +ve delta of number of active cores of bucket 5. 1493 * [47:45]-- -ve delta of freq ratio of bucket 5. 1494 * [52:48]-- +ve delta of number of active cores of bucket 6. 1495 * [55:53]-- -ve delta of freq ratio of bucket 6. 1496 * [60:56]-- +ve delta of number of active cores of bucket 7. 1497 * [63:61]-- -ve delta of freq ratio of bucket 7. 1498 */ 1499 1500 b_nr = 0; 1501 cores[b_nr] = (msr & 0xFF) >> 1; 1502 ratio[b_nr] = (msr >> 8) & 0xFF; 1503 1504 for (i = 16; i < 64; i += 8) { 1505 delta_cores = (msr >> i) & 0x1F; 1506 delta_ratio = (msr >> (i + 5)) & 0x7; 1507 1508 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1509 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1510 b_nr++; 1511 } 1512 1513 for (i = buckets_no - 1; i >= 0; i--) 1514 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1515 fprintf(outf, 1516 "%d * %.0f = %.0f MHz max turbo %d active cores\n", 1517 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1518 } 1519 1520 static void 1521 dump_nhm_cst_cfg(void) 1522 { 1523 unsigned long long msr; 1524 1525 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 1526 1527 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1528 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1529 1530 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr); 1531 1532 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1533 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1534 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1535 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1536 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1537 (msr & (1 << 15)) ? "" : "UN", 1538 (unsigned int)msr & 0xF, 1539 pkg_cstate_limit_strings[pkg_cstate_limit]); 1540 return; 1541 } 1542 1543 static void 1544 dump_config_tdp(void) 1545 { 1546 unsigned long long msr; 1547 1548 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1549 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1550 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1551 1552 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1553 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1554 if (msr) { 1555 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1556 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1557 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1558 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1559 } 1560 fprintf(outf, ")\n"); 1561 1562 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1563 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1564 if (msr) { 1565 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1566 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1567 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1568 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1569 } 1570 fprintf(outf, ")\n"); 1571 1572 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1573 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1574 if ((msr) & 0x3) 1575 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1576 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1577 fprintf(outf, ")\n"); 1578 1579 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1580 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1581 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1582 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1583 fprintf(outf, ")\n"); 1584 } 1585 1586 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1587 1588 void print_irtl(void) 1589 { 1590 unsigned long long msr; 1591 1592 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1593 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1594 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1595 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1596 1597 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1598 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1599 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1600 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1601 1602 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1603 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1604 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1605 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1606 1607 if (!do_irtl_hsw) 1608 return; 1609 1610 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1611 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1612 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1613 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1614 1615 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1616 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1617 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1618 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1619 1620 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1621 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1622 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1623 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1624 1625 } 1626 void free_fd_percpu(void) 1627 { 1628 int i; 1629 1630 for (i = 0; i < topo.max_cpu_num; ++i) { 1631 if (fd_percpu[i] != 0) 1632 close(fd_percpu[i]); 1633 } 1634 1635 free(fd_percpu); 1636 } 1637 1638 void free_all_buffers(void) 1639 { 1640 CPU_FREE(cpu_present_set); 1641 cpu_present_set = NULL; 1642 cpu_present_setsize = 0; 1643 1644 CPU_FREE(cpu_affinity_set); 1645 cpu_affinity_set = NULL; 1646 cpu_affinity_setsize = 0; 1647 1648 free(thread_even); 1649 free(core_even); 1650 free(package_even); 1651 1652 thread_even = NULL; 1653 core_even = NULL; 1654 package_even = NULL; 1655 1656 free(thread_odd); 1657 free(core_odd); 1658 free(package_odd); 1659 1660 thread_odd = NULL; 1661 core_odd = NULL; 1662 package_odd = NULL; 1663 1664 free(output_buffer); 1665 output_buffer = NULL; 1666 outp = NULL; 1667 1668 free_fd_percpu(); 1669 1670 free(irq_column_2_cpu); 1671 free(irqs_per_cpu); 1672 } 1673 1674 /* 1675 * Open a file, and exit on failure 1676 */ 1677 FILE *fopen_or_die(const char *path, const char *mode) 1678 { 1679 FILE *filep = fopen(path, mode); 1680 if (!filep) 1681 err(1, "%s: open failed", path); 1682 return filep; 1683 } 1684 1685 /* 1686 * Parse a file containing a single int. 1687 */ 1688 int parse_int_file(const char *fmt, ...) 1689 { 1690 va_list args; 1691 char path[PATH_MAX]; 1692 FILE *filep; 1693 int value; 1694 1695 va_start(args, fmt); 1696 vsnprintf(path, sizeof(path), fmt, args); 1697 va_end(args); 1698 filep = fopen_or_die(path, "r"); 1699 if (fscanf(filep, "%d", &value) != 1) 1700 err(1, "%s: failed to parse number from file", path); 1701 fclose(filep); 1702 return value; 1703 } 1704 1705 /* 1706 * get_cpu_position_in_core(cpu) 1707 * return the position of the CPU among its HT siblings in the core 1708 * return -1 if the sibling is not in list 1709 */ 1710 int get_cpu_position_in_core(int cpu) 1711 { 1712 char path[64]; 1713 FILE *filep; 1714 int this_cpu; 1715 char character; 1716 int i; 1717 1718 sprintf(path, 1719 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 1720 cpu); 1721 filep = fopen(path, "r"); 1722 if (filep == NULL) { 1723 perror(path); 1724 exit(1); 1725 } 1726 1727 for (i = 0; i < topo.num_threads_per_core; i++) { 1728 fscanf(filep, "%d", &this_cpu); 1729 if (this_cpu == cpu) { 1730 fclose(filep); 1731 return i; 1732 } 1733 1734 /* Account for no separator after last thread*/ 1735 if (i != (topo.num_threads_per_core - 1)) 1736 fscanf(filep, "%c", &character); 1737 } 1738 1739 fclose(filep); 1740 return -1; 1741 } 1742 1743 /* 1744 * cpu_is_first_core_in_package(cpu) 1745 * return 1 if given CPU is 1st core in package 1746 */ 1747 int cpu_is_first_core_in_package(int cpu) 1748 { 1749 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 1750 } 1751 1752 int get_physical_package_id(int cpu) 1753 { 1754 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 1755 } 1756 1757 int get_core_id(int cpu) 1758 { 1759 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 1760 } 1761 1762 int get_num_ht_siblings(int cpu) 1763 { 1764 char path[80]; 1765 FILE *filep; 1766 int sib1; 1767 int matches = 0; 1768 char character; 1769 char str[100]; 1770 char *ch; 1771 1772 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 1773 filep = fopen_or_die(path, "r"); 1774 1775 /* 1776 * file format: 1777 * A ',' separated or '-' separated set of numbers 1778 * (eg 1-2 or 1,3,4,5) 1779 */ 1780 fscanf(filep, "%d%c\n", &sib1, &character); 1781 fseek(filep, 0, SEEK_SET); 1782 fgets(str, 100, filep); 1783 ch = strchr(str, character); 1784 while (ch != NULL) { 1785 matches++; 1786 ch = strchr(ch+1, character); 1787 } 1788 1789 fclose(filep); 1790 return matches+1; 1791 } 1792 1793 /* 1794 * run func(thread, core, package) in topology order 1795 * skip non-present cpus 1796 */ 1797 1798 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 1799 struct pkg_data *, struct thread_data *, struct core_data *, 1800 struct pkg_data *), struct thread_data *thread_base, 1801 struct core_data *core_base, struct pkg_data *pkg_base, 1802 struct thread_data *thread_base2, struct core_data *core_base2, 1803 struct pkg_data *pkg_base2) 1804 { 1805 int retval, pkg_no, core_no, thread_no; 1806 1807 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 1808 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 1809 for (thread_no = 0; thread_no < 1810 topo.num_threads_per_core; ++thread_no) { 1811 struct thread_data *t, *t2; 1812 struct core_data *c, *c2; 1813 struct pkg_data *p, *p2; 1814 1815 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 1816 1817 if (cpu_is_not_present(t->cpu_id)) 1818 continue; 1819 1820 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 1821 1822 c = GET_CORE(core_base, core_no, pkg_no); 1823 c2 = GET_CORE(core_base2, core_no, pkg_no); 1824 1825 p = GET_PKG(pkg_base, pkg_no); 1826 p2 = GET_PKG(pkg_base2, pkg_no); 1827 1828 retval = func(t, c, p, t2, c2, p2); 1829 if (retval) 1830 return retval; 1831 } 1832 } 1833 } 1834 return 0; 1835 } 1836 1837 /* 1838 * run func(cpu) on every cpu in /proc/stat 1839 * return max_cpu number 1840 */ 1841 int for_all_proc_cpus(int (func)(int)) 1842 { 1843 FILE *fp; 1844 int cpu_num; 1845 int retval; 1846 1847 fp = fopen_or_die(proc_stat, "r"); 1848 1849 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 1850 if (retval != 0) 1851 err(1, "%s: failed to parse format", proc_stat); 1852 1853 while (1) { 1854 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 1855 if (retval != 1) 1856 break; 1857 1858 retval = func(cpu_num); 1859 if (retval) { 1860 fclose(fp); 1861 return(retval); 1862 } 1863 } 1864 fclose(fp); 1865 return 0; 1866 } 1867 1868 void re_initialize(void) 1869 { 1870 free_all_buffers(); 1871 setup_all_buffers(); 1872 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 1873 } 1874 1875 1876 /* 1877 * count_cpus() 1878 * remember the last one seen, it will be the max 1879 */ 1880 int count_cpus(int cpu) 1881 { 1882 if (topo.max_cpu_num < cpu) 1883 topo.max_cpu_num = cpu; 1884 1885 topo.num_cpus += 1; 1886 return 0; 1887 } 1888 int mark_cpu_present(int cpu) 1889 { 1890 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 1891 return 0; 1892 } 1893 1894 /* 1895 * snapshot_proc_interrupts() 1896 * 1897 * read and record summary of /proc/interrupts 1898 * 1899 * return 1 if config change requires a restart, else return 0 1900 */ 1901 int snapshot_proc_interrupts(void) 1902 { 1903 static FILE *fp; 1904 int column, retval; 1905 1906 if (fp == NULL) 1907 fp = fopen_or_die("/proc/interrupts", "r"); 1908 else 1909 rewind(fp); 1910 1911 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 1912 for (column = 0; column < topo.num_cpus; ++column) { 1913 int cpu_number; 1914 1915 retval = fscanf(fp, " CPU%d", &cpu_number); 1916 if (retval != 1) 1917 break; 1918 1919 if (cpu_number > topo.max_cpu_num) { 1920 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 1921 return 1; 1922 } 1923 1924 irq_column_2_cpu[column] = cpu_number; 1925 irqs_per_cpu[cpu_number] = 0; 1926 } 1927 1928 /* read /proc/interrupt count lines and sum up irqs per cpu */ 1929 while (1) { 1930 int column; 1931 char buf[64]; 1932 1933 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 1934 if (retval != 1) 1935 break; 1936 1937 /* read the count per cpu */ 1938 for (column = 0; column < topo.num_cpus; ++column) { 1939 1940 int cpu_number, irq_count; 1941 1942 retval = fscanf(fp, " %d", &irq_count); 1943 if (retval != 1) 1944 break; 1945 1946 cpu_number = irq_column_2_cpu[column]; 1947 irqs_per_cpu[cpu_number] += irq_count; 1948 1949 } 1950 1951 while (getc(fp) != '\n') 1952 ; /* flush interrupt description */ 1953 1954 } 1955 return 0; 1956 } 1957 /* 1958 * snapshot_gfx_rc6_ms() 1959 * 1960 * record snapshot of 1961 * /sys/class/drm/card0/power/rc6_residency_ms 1962 * 1963 * return 1 if config change requires a restart, else return 0 1964 */ 1965 int snapshot_gfx_rc6_ms(void) 1966 { 1967 FILE *fp; 1968 int retval; 1969 1970 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 1971 1972 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 1973 if (retval != 1) 1974 err(1, "GFX rc6"); 1975 1976 fclose(fp); 1977 1978 return 0; 1979 } 1980 /* 1981 * snapshot_gfx_mhz() 1982 * 1983 * record snapshot of 1984 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 1985 * 1986 * return 1 if config change requires a restart, else return 0 1987 */ 1988 int snapshot_gfx_mhz(void) 1989 { 1990 static FILE *fp; 1991 int retval; 1992 1993 if (fp == NULL) 1994 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 1995 else 1996 rewind(fp); 1997 1998 retval = fscanf(fp, "%d", &gfx_cur_mhz); 1999 if (retval != 1) 2000 err(1, "GFX MHz"); 2001 2002 return 0; 2003 } 2004 2005 /* 2006 * snapshot /proc and /sys files 2007 * 2008 * return 1 if configuration restart needed, else return 0 2009 */ 2010 int snapshot_proc_sysfs_files(void) 2011 { 2012 if (snapshot_proc_interrupts()) 2013 return 1; 2014 2015 if (do_gfx_rc6_ms) 2016 snapshot_gfx_rc6_ms(); 2017 2018 if (do_gfx_mhz) 2019 snapshot_gfx_mhz(); 2020 2021 return 0; 2022 } 2023 2024 void turbostat_loop() 2025 { 2026 int retval; 2027 int restarted = 0; 2028 2029 restart: 2030 restarted++; 2031 2032 snapshot_proc_sysfs_files(); 2033 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2034 if (retval < -1) { 2035 exit(retval); 2036 } else if (retval == -1) { 2037 if (restarted > 1) { 2038 exit(retval); 2039 } 2040 re_initialize(); 2041 goto restart; 2042 } 2043 restarted = 0; 2044 gettimeofday(&tv_even, (struct timezone *)NULL); 2045 2046 while (1) { 2047 if (for_all_proc_cpus(cpu_is_not_present)) { 2048 re_initialize(); 2049 goto restart; 2050 } 2051 nanosleep(&interval_ts, NULL); 2052 if (snapshot_proc_sysfs_files()) 2053 goto restart; 2054 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2055 if (retval < -1) { 2056 exit(retval); 2057 } else if (retval == -1) { 2058 re_initialize(); 2059 goto restart; 2060 } 2061 gettimeofday(&tv_odd, (struct timezone *)NULL); 2062 timersub(&tv_odd, &tv_even, &tv_delta); 2063 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); 2064 compute_average(EVEN_COUNTERS); 2065 format_all_counters(EVEN_COUNTERS); 2066 flush_output_stdout(); 2067 nanosleep(&interval_ts, NULL); 2068 if (snapshot_proc_sysfs_files()) 2069 goto restart; 2070 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2071 if (retval < -1) { 2072 exit(retval); 2073 } else if (retval == -1) { 2074 re_initialize(); 2075 goto restart; 2076 } 2077 gettimeofday(&tv_even, (struct timezone *)NULL); 2078 timersub(&tv_even, &tv_odd, &tv_delta); 2079 for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS); 2080 compute_average(ODD_COUNTERS); 2081 format_all_counters(ODD_COUNTERS); 2082 flush_output_stdout(); 2083 } 2084 } 2085 2086 void check_dev_msr() 2087 { 2088 struct stat sb; 2089 char pathname[32]; 2090 2091 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2092 if (stat(pathname, &sb)) 2093 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2094 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2095 } 2096 2097 void check_permissions() 2098 { 2099 struct __user_cap_header_struct cap_header_data; 2100 cap_user_header_t cap_header = &cap_header_data; 2101 struct __user_cap_data_struct cap_data_data; 2102 cap_user_data_t cap_data = &cap_data_data; 2103 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2104 int do_exit = 0; 2105 char pathname[32]; 2106 2107 /* check for CAP_SYS_RAWIO */ 2108 cap_header->pid = getpid(); 2109 cap_header->version = _LINUX_CAPABILITY_VERSION; 2110 if (capget(cap_header, cap_data) < 0) 2111 err(-6, "capget(2) failed"); 2112 2113 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2114 do_exit++; 2115 warnx("capget(CAP_SYS_RAWIO) failed," 2116 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2117 } 2118 2119 /* test file permissions */ 2120 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2121 if (euidaccess(pathname, R_OK)) { 2122 do_exit++; 2123 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2124 } 2125 2126 /* if all else fails, thell them to be root */ 2127 if (do_exit) 2128 if (getuid() != 0) 2129 warnx("... or simply run as root"); 2130 2131 if (do_exit) 2132 exit(-6); 2133 } 2134 2135 /* 2136 * NHM adds support for additional MSRs: 2137 * 2138 * MSR_SMI_COUNT 0x00000034 2139 * 2140 * MSR_PLATFORM_INFO 0x000000ce 2141 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 2142 * 2143 * MSR_PKG_C3_RESIDENCY 0x000003f8 2144 * MSR_PKG_C6_RESIDENCY 0x000003f9 2145 * MSR_CORE_C3_RESIDENCY 0x000003fc 2146 * MSR_CORE_C6_RESIDENCY 0x000003fd 2147 * 2148 * Side effect: 2149 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL 2150 */ 2151 int probe_nhm_msrs(unsigned int family, unsigned int model) 2152 { 2153 unsigned long long msr; 2154 unsigned int base_ratio; 2155 int *pkg_cstate_limits; 2156 2157 if (!genuine_intel) 2158 return 0; 2159 2160 if (family != 6) 2161 return 0; 2162 2163 bclk = discover_bclk(family, model); 2164 2165 switch (model) { 2166 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2167 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2168 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2169 case 0x25: /* Westmere Client - Clarkdale, Arrandale */ 2170 case 0x2C: /* Westmere EP - Gulftown */ 2171 case 0x2E: /* Nehalem-EX Xeon - Beckton */ 2172 case 0x2F: /* Westmere-EX Xeon - Eagleton */ 2173 pkg_cstate_limits = nhm_pkg_cstate_limits; 2174 break; 2175 case 0x2A: /* SNB */ 2176 case 0x2D: /* SNB Xeon */ 2177 case 0x3A: /* IVB */ 2178 case 0x3E: /* IVB Xeon */ 2179 pkg_cstate_limits = snb_pkg_cstate_limits; 2180 break; 2181 case 0x3C: /* HSW */ 2182 case 0x3F: /* HSX */ 2183 case 0x45: /* HSW */ 2184 case 0x46: /* HSW */ 2185 case 0x3D: /* BDW */ 2186 case 0x47: /* BDW */ 2187 case 0x4F: /* BDX */ 2188 case 0x56: /* BDX-DE */ 2189 case 0x4E: /* SKL */ 2190 case 0x5E: /* SKL */ 2191 case 0x55: /* SKX */ 2192 pkg_cstate_limits = hsw_pkg_cstate_limits; 2193 break; 2194 case 0x37: /* BYT */ 2195 case 0x4D: /* AVN */ 2196 pkg_cstate_limits = slv_pkg_cstate_limits; 2197 break; 2198 case 0x4C: /* AMT */ 2199 pkg_cstate_limits = amt_pkg_cstate_limits; 2200 break; 2201 case 0x57: /* PHI */ 2202 pkg_cstate_limits = phi_pkg_cstate_limits; 2203 break; 2204 case 0x5C: /* BXT */ 2205 pkg_cstate_limits = bxt_pkg_cstate_limits; 2206 break; 2207 default: 2208 return 0; 2209 } 2210 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 2211 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2212 2213 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2214 base_ratio = (msr >> 8) & 0xFF; 2215 2216 base_hz = base_ratio * bclk * 1000000; 2217 has_base_hz = 1; 2218 return 1; 2219 } 2220 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2221 { 2222 switch (model) { 2223 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2224 case 0x2E: /* Nehalem-EX Xeon - Beckton */ 2225 case 0x2F: /* Westmere-EX Xeon - Eagleton */ 2226 case 0x57: /* PHI - Knights Landing (different MSR definition) */ 2227 return 0; 2228 default: 2229 return 1; 2230 } 2231 } 2232 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2233 { 2234 if (!genuine_intel) 2235 return 0; 2236 2237 if (family != 6) 2238 return 0; 2239 2240 switch (model) { 2241 case 0x3E: /* IVB Xeon */ 2242 case 0x3F: /* HSW Xeon */ 2243 return 1; 2244 default: 2245 return 0; 2246 } 2247 } 2248 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2249 { 2250 if (!genuine_intel) 2251 return 0; 2252 2253 if (family != 6) 2254 return 0; 2255 2256 switch (model) { 2257 case 0x3F: /* HSW Xeon */ 2258 return 1; 2259 default: 2260 return 0; 2261 } 2262 } 2263 2264 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2265 { 2266 if (!genuine_intel) 2267 return 0; 2268 2269 if (family != 6) 2270 return 0; 2271 2272 switch (model) { 2273 case 0x57: /* Knights Landing */ 2274 return 1; 2275 default: 2276 return 0; 2277 } 2278 } 2279 int has_config_tdp(unsigned int family, unsigned int model) 2280 { 2281 if (!genuine_intel) 2282 return 0; 2283 2284 if (family != 6) 2285 return 0; 2286 2287 switch (model) { 2288 case 0x3A: /* IVB */ 2289 case 0x3C: /* HSW */ 2290 case 0x3F: /* HSX */ 2291 case 0x45: /* HSW */ 2292 case 0x46: /* HSW */ 2293 case 0x3D: /* BDW */ 2294 case 0x47: /* BDW */ 2295 case 0x4F: /* BDX */ 2296 case 0x56: /* BDX-DE */ 2297 case 0x4E: /* SKL */ 2298 case 0x5E: /* SKL */ 2299 case 0x55: /* SKX */ 2300 2301 case 0x57: /* Knights Landing */ 2302 return 1; 2303 default: 2304 return 0; 2305 } 2306 } 2307 2308 static void 2309 dump_cstate_pstate_config_info(int family, int model) 2310 { 2311 if (!do_nhm_platform_info) 2312 return; 2313 2314 dump_nhm_platform_info(); 2315 2316 if (has_hsw_turbo_ratio_limit(family, model)) 2317 dump_hsw_turbo_ratio_limits(); 2318 2319 if (has_ivt_turbo_ratio_limit(family, model)) 2320 dump_ivt_turbo_ratio_limits(); 2321 2322 if (has_nhm_turbo_ratio_limit(family, model)) 2323 dump_nhm_turbo_ratio_limits(); 2324 2325 if (has_knl_turbo_ratio_limit(family, model)) 2326 dump_knl_turbo_ratio_limits(); 2327 2328 if (has_config_tdp(family, model)) 2329 dump_config_tdp(); 2330 2331 dump_nhm_cst_cfg(); 2332 } 2333 2334 2335 /* 2336 * print_epb() 2337 * Decode the ENERGY_PERF_BIAS MSR 2338 */ 2339 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2340 { 2341 unsigned long long msr; 2342 char *epb_string; 2343 int cpu; 2344 2345 if (!has_epb) 2346 return 0; 2347 2348 cpu = t->cpu_id; 2349 2350 /* EPB is per-package */ 2351 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2352 return 0; 2353 2354 if (cpu_migrate(cpu)) { 2355 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2356 return -1; 2357 } 2358 2359 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2360 return 0; 2361 2362 switch (msr & 0xF) { 2363 case ENERGY_PERF_BIAS_PERFORMANCE: 2364 epb_string = "performance"; 2365 break; 2366 case ENERGY_PERF_BIAS_NORMAL: 2367 epb_string = "balanced"; 2368 break; 2369 case ENERGY_PERF_BIAS_POWERSAVE: 2370 epb_string = "powersave"; 2371 break; 2372 default: 2373 epb_string = "custom"; 2374 break; 2375 } 2376 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2377 2378 return 0; 2379 } 2380 /* 2381 * print_hwp() 2382 * Decode the MSR_HWP_CAPABILITIES 2383 */ 2384 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2385 { 2386 unsigned long long msr; 2387 int cpu; 2388 2389 if (!has_hwp) 2390 return 0; 2391 2392 cpu = t->cpu_id; 2393 2394 /* MSR_HWP_CAPABILITIES is per-package */ 2395 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2396 return 0; 2397 2398 if (cpu_migrate(cpu)) { 2399 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2400 return -1; 2401 } 2402 2403 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2404 return 0; 2405 2406 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2407 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2408 2409 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2410 if ((msr & (1 << 0)) == 0) 2411 return 0; 2412 2413 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2414 return 0; 2415 2416 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2417 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2418 cpu, msr, 2419 (unsigned int)HWP_HIGHEST_PERF(msr), 2420 (unsigned int)HWP_GUARANTEED_PERF(msr), 2421 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2422 (unsigned int)HWP_LOWEST_PERF(msr)); 2423 2424 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2425 return 0; 2426 2427 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2428 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2429 cpu, msr, 2430 (unsigned int)(((msr) >> 0) & 0xff), 2431 (unsigned int)(((msr) >> 8) & 0xff), 2432 (unsigned int)(((msr) >> 16) & 0xff), 2433 (unsigned int)(((msr) >> 24) & 0xff), 2434 (unsigned int)(((msr) >> 32) & 0xff3), 2435 (unsigned int)(((msr) >> 42) & 0x1)); 2436 2437 if (has_hwp_pkg) { 2438 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2439 return 0; 2440 2441 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2442 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2443 cpu, msr, 2444 (unsigned int)(((msr) >> 0) & 0xff), 2445 (unsigned int)(((msr) >> 8) & 0xff), 2446 (unsigned int)(((msr) >> 16) & 0xff), 2447 (unsigned int)(((msr) >> 24) & 0xff), 2448 (unsigned int)(((msr) >> 32) & 0xff3)); 2449 } 2450 if (has_hwp_notify) { 2451 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2452 return 0; 2453 2454 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2455 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2456 cpu, msr, 2457 ((msr) & 0x1) ? "EN" : "Dis", 2458 ((msr) & 0x2) ? "EN" : "Dis"); 2459 } 2460 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2461 return 0; 2462 2463 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2464 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2465 cpu, msr, 2466 ((msr) & 0x1) ? "" : "No-", 2467 ((msr) & 0x2) ? "" : "No-"); 2468 2469 return 0; 2470 } 2471 2472 /* 2473 * print_perf_limit() 2474 */ 2475 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2476 { 2477 unsigned long long msr; 2478 int cpu; 2479 2480 cpu = t->cpu_id; 2481 2482 /* per-package */ 2483 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2484 return 0; 2485 2486 if (cpu_migrate(cpu)) { 2487 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2488 return -1; 2489 } 2490 2491 if (do_core_perf_limit_reasons) { 2492 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2493 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2494 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2495 (msr & 1 << 15) ? "bit15, " : "", 2496 (msr & 1 << 14) ? "bit14, " : "", 2497 (msr & 1 << 13) ? "Transitions, " : "", 2498 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2499 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2500 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2501 (msr & 1 << 9) ? "CorePwr, " : "", 2502 (msr & 1 << 8) ? "Amps, " : "", 2503 (msr & 1 << 6) ? "VR-Therm, " : "", 2504 (msr & 1 << 5) ? "Auto-HWP, " : "", 2505 (msr & 1 << 4) ? "Graphics, " : "", 2506 (msr & 1 << 2) ? "bit2, " : "", 2507 (msr & 1 << 1) ? "ThermStatus, " : "", 2508 (msr & 1 << 0) ? "PROCHOT, " : ""); 2509 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2510 (msr & 1 << 31) ? "bit31, " : "", 2511 (msr & 1 << 30) ? "bit30, " : "", 2512 (msr & 1 << 29) ? "Transitions, " : "", 2513 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2514 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2515 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2516 (msr & 1 << 25) ? "CorePwr, " : "", 2517 (msr & 1 << 24) ? "Amps, " : "", 2518 (msr & 1 << 22) ? "VR-Therm, " : "", 2519 (msr & 1 << 21) ? "Auto-HWP, " : "", 2520 (msr & 1 << 20) ? "Graphics, " : "", 2521 (msr & 1 << 18) ? "bit18, " : "", 2522 (msr & 1 << 17) ? "ThermStatus, " : "", 2523 (msr & 1 << 16) ? "PROCHOT, " : ""); 2524 2525 } 2526 if (do_gfx_perf_limit_reasons) { 2527 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2528 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2529 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2530 (msr & 1 << 0) ? "PROCHOT, " : "", 2531 (msr & 1 << 1) ? "ThermStatus, " : "", 2532 (msr & 1 << 4) ? "Graphics, " : "", 2533 (msr & 1 << 6) ? "VR-Therm, " : "", 2534 (msr & 1 << 8) ? "Amps, " : "", 2535 (msr & 1 << 9) ? "GFXPwr, " : "", 2536 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2537 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2538 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2539 (msr & 1 << 16) ? "PROCHOT, " : "", 2540 (msr & 1 << 17) ? "ThermStatus, " : "", 2541 (msr & 1 << 20) ? "Graphics, " : "", 2542 (msr & 1 << 22) ? "VR-Therm, " : "", 2543 (msr & 1 << 24) ? "Amps, " : "", 2544 (msr & 1 << 25) ? "GFXPwr, " : "", 2545 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2546 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2547 } 2548 if (do_ring_perf_limit_reasons) { 2549 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2550 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2551 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2552 (msr & 1 << 0) ? "PROCHOT, " : "", 2553 (msr & 1 << 1) ? "ThermStatus, " : "", 2554 (msr & 1 << 6) ? "VR-Therm, " : "", 2555 (msr & 1 << 8) ? "Amps, " : "", 2556 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2557 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2558 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2559 (msr & 1 << 16) ? "PROCHOT, " : "", 2560 (msr & 1 << 17) ? "ThermStatus, " : "", 2561 (msr & 1 << 22) ? "VR-Therm, " : "", 2562 (msr & 1 << 24) ? "Amps, " : "", 2563 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2564 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2565 } 2566 return 0; 2567 } 2568 2569 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2570 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2571 2572 double get_tdp(int model) 2573 { 2574 unsigned long long msr; 2575 2576 if (do_rapl & RAPL_PKG_POWER_INFO) 2577 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2578 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2579 2580 switch (model) { 2581 case 0x37: 2582 case 0x4D: 2583 return 30.0; 2584 default: 2585 return 135.0; 2586 } 2587 } 2588 2589 /* 2590 * rapl_dram_energy_units_probe() 2591 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2592 */ 2593 static double 2594 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2595 { 2596 /* only called for genuine_intel, family 6 */ 2597 2598 switch (model) { 2599 case 0x3F: /* HSX */ 2600 case 0x4F: /* BDX */ 2601 case 0x56: /* BDX-DE */ 2602 case 0x57: /* KNL */ 2603 return (rapl_dram_energy_units = 15.3 / 1000000); 2604 default: 2605 return (rapl_energy_units); 2606 } 2607 } 2608 2609 2610 /* 2611 * rapl_probe() 2612 * 2613 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2614 */ 2615 void rapl_probe(unsigned int family, unsigned int model) 2616 { 2617 unsigned long long msr; 2618 unsigned int time_unit; 2619 double tdp; 2620 2621 if (!genuine_intel) 2622 return; 2623 2624 if (family != 6) 2625 return; 2626 2627 switch (model) { 2628 case 0x2A: 2629 case 0x3A: 2630 case 0x3C: /* HSW */ 2631 case 0x45: /* HSW */ 2632 case 0x46: /* HSW */ 2633 case 0x3D: /* BDW */ 2634 case 0x47: /* BDW */ 2635 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 2636 break; 2637 case 0x5C: /* BXT */ 2638 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 2639 break; 2640 case 0x4E: /* SKL */ 2641 case 0x5E: /* SKL */ 2642 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2643 break; 2644 case 0x3F: /* HSX */ 2645 case 0x4F: /* BDX */ 2646 case 0x56: /* BDX-DE */ 2647 case 0x55: /* SKX */ 2648 case 0x57: /* KNL */ 2649 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2650 break; 2651 case 0x2D: 2652 case 0x3E: 2653 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 2654 break; 2655 case 0x37: /* BYT */ 2656 case 0x4D: /* AVN */ 2657 do_rapl = RAPL_PKG | RAPL_CORES ; 2658 break; 2659 default: 2660 return; 2661 } 2662 2663 /* units on package 0, verify later other packages match */ 2664 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 2665 return; 2666 2667 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 2668 if (model == 0x37) 2669 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 2670 else 2671 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 2672 2673 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 2674 2675 time_unit = msr >> 16 & 0xF; 2676 if (time_unit == 0) 2677 time_unit = 0xA; 2678 2679 rapl_time_units = 1.0 / (1 << (time_unit)); 2680 2681 tdp = get_tdp(model); 2682 2683 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 2684 if (debug) 2685 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 2686 2687 return; 2688 } 2689 2690 void perf_limit_reasons_probe(int family, int model) 2691 { 2692 if (!genuine_intel) 2693 return; 2694 2695 if (family != 6) 2696 return; 2697 2698 switch (model) { 2699 case 0x3C: /* HSW */ 2700 case 0x45: /* HSW */ 2701 case 0x46: /* HSW */ 2702 do_gfx_perf_limit_reasons = 1; 2703 case 0x3F: /* HSX */ 2704 do_core_perf_limit_reasons = 1; 2705 do_ring_perf_limit_reasons = 1; 2706 default: 2707 return; 2708 } 2709 } 2710 2711 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2712 { 2713 unsigned long long msr; 2714 unsigned int dts; 2715 int cpu; 2716 2717 if (!(do_dts || do_ptm)) 2718 return 0; 2719 2720 cpu = t->cpu_id; 2721 2722 /* DTS is per-core, no need to print for each thread */ 2723 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2724 return 0; 2725 2726 if (cpu_migrate(cpu)) { 2727 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2728 return -1; 2729 } 2730 2731 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 2732 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2733 return 0; 2734 2735 dts = (msr >> 16) & 0x7F; 2736 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 2737 cpu, msr, tcc_activation_temp - dts); 2738 2739 #ifdef THERM_DEBUG 2740 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 2741 return 0; 2742 2743 dts = (msr >> 16) & 0x7F; 2744 dts2 = (msr >> 8) & 0x7F; 2745 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2746 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2747 #endif 2748 } 2749 2750 2751 if (do_dts) { 2752 unsigned int resolution; 2753 2754 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2755 return 0; 2756 2757 dts = (msr >> 16) & 0x7F; 2758 resolution = (msr >> 27) & 0xF; 2759 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 2760 cpu, msr, tcc_activation_temp - dts, resolution); 2761 2762 #ifdef THERM_DEBUG 2763 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 2764 return 0; 2765 2766 dts = (msr >> 16) & 0x7F; 2767 dts2 = (msr >> 8) & 0x7F; 2768 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2769 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2770 #endif 2771 } 2772 2773 return 0; 2774 } 2775 2776 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 2777 { 2778 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 2779 cpu, label, 2780 ((msr >> 15) & 1) ? "EN" : "DIS", 2781 ((msr >> 0) & 0x7FFF) * rapl_power_units, 2782 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 2783 (((msr >> 16) & 1) ? "EN" : "DIS")); 2784 2785 return; 2786 } 2787 2788 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2789 { 2790 unsigned long long msr; 2791 int cpu; 2792 2793 if (!do_rapl) 2794 return 0; 2795 2796 /* RAPL counters are per package, so print only for 1st thread/package */ 2797 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2798 return 0; 2799 2800 cpu = t->cpu_id; 2801 if (cpu_migrate(cpu)) { 2802 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2803 return -1; 2804 } 2805 2806 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 2807 return -1; 2808 2809 if (debug) { 2810 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 2811 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 2812 rapl_power_units, rapl_energy_units, rapl_time_units); 2813 } 2814 if (do_rapl & RAPL_PKG_POWER_INFO) { 2815 2816 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 2817 return -5; 2818 2819 2820 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 2821 cpu, msr, 2822 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2823 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2824 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2825 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 2826 2827 } 2828 if (do_rapl & RAPL_PKG) { 2829 2830 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 2831 return -9; 2832 2833 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 2834 cpu, msr, (msr >> 63) & 1 ? "": "UN"); 2835 2836 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 2837 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 2838 cpu, 2839 ((msr >> 47) & 1) ? "EN" : "DIS", 2840 ((msr >> 32) & 0x7FFF) * rapl_power_units, 2841 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 2842 ((msr >> 48) & 1) ? "EN" : "DIS"); 2843 } 2844 2845 if (do_rapl & RAPL_DRAM_POWER_INFO) { 2846 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 2847 return -6; 2848 2849 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 2850 cpu, msr, 2851 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2852 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2853 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2854 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 2855 } 2856 if (do_rapl & RAPL_DRAM) { 2857 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 2858 return -9; 2859 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 2860 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2861 2862 print_power_limit_msr(cpu, msr, "DRAM Limit"); 2863 } 2864 if (do_rapl & RAPL_CORE_POLICY) { 2865 if (debug) { 2866 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 2867 return -7; 2868 2869 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 2870 } 2871 } 2872 if (do_rapl & RAPL_CORES) { 2873 if (debug) { 2874 2875 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 2876 return -9; 2877 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 2878 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2879 print_power_limit_msr(cpu, msr, "Cores Limit"); 2880 } 2881 } 2882 if (do_rapl & RAPL_GFX) { 2883 if (debug) { 2884 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 2885 return -8; 2886 2887 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 2888 2889 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 2890 return -9; 2891 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 2892 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2893 print_power_limit_msr(cpu, msr, "GFX Limit"); 2894 } 2895 } 2896 return 0; 2897 } 2898 2899 /* 2900 * SNB adds support for additional MSRs: 2901 * 2902 * MSR_PKG_C7_RESIDENCY 0x000003fa 2903 * MSR_CORE_C7_RESIDENCY 0x000003fe 2904 * MSR_PKG_C2_RESIDENCY 0x0000060d 2905 */ 2906 2907 int has_snb_msrs(unsigned int family, unsigned int model) 2908 { 2909 if (!genuine_intel) 2910 return 0; 2911 2912 switch (model) { 2913 case 0x2A: 2914 case 0x2D: 2915 case 0x3A: /* IVB */ 2916 case 0x3E: /* IVB Xeon */ 2917 case 0x3C: /* HSW */ 2918 case 0x3F: /* HSW */ 2919 case 0x45: /* HSW */ 2920 case 0x46: /* HSW */ 2921 case 0x3D: /* BDW */ 2922 case 0x47: /* BDW */ 2923 case 0x4F: /* BDX */ 2924 case 0x56: /* BDX-DE */ 2925 case 0x4E: /* SKL */ 2926 case 0x5E: /* SKL */ 2927 case 0x55: /* SKX */ 2928 case 0x5C: /* BXT */ 2929 return 1; 2930 } 2931 return 0; 2932 } 2933 2934 /* 2935 * HSW adds support for additional MSRs: 2936 * 2937 * MSR_PKG_C8_RESIDENCY 0x00000630 2938 * MSR_PKG_C9_RESIDENCY 0x00000631 2939 * MSR_PKG_C10_RESIDENCY 0x00000632 2940 * 2941 * MSR_PKGC8_IRTL 0x00000633 2942 * MSR_PKGC9_IRTL 0x00000634 2943 * MSR_PKGC10_IRTL 0x00000635 2944 * 2945 */ 2946 int has_hsw_msrs(unsigned int family, unsigned int model) 2947 { 2948 if (!genuine_intel) 2949 return 0; 2950 2951 switch (model) { 2952 case 0x45: /* HSW */ 2953 case 0x3D: /* BDW */ 2954 case 0x4E: /* SKL */ 2955 case 0x5E: /* SKL */ 2956 case 0x5C: /* BXT */ 2957 return 1; 2958 } 2959 return 0; 2960 } 2961 2962 /* 2963 * SKL adds support for additional MSRS: 2964 * 2965 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 2966 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 2967 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 2968 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 2969 */ 2970 int has_skl_msrs(unsigned int family, unsigned int model) 2971 { 2972 if (!genuine_intel) 2973 return 0; 2974 2975 switch (model) { 2976 case 0x4E: /* SKL */ 2977 case 0x5E: /* SKL */ 2978 return 1; 2979 } 2980 return 0; 2981 } 2982 2983 2984 2985 int is_slm(unsigned int family, unsigned int model) 2986 { 2987 if (!genuine_intel) 2988 return 0; 2989 switch (model) { 2990 case 0x37: /* BYT */ 2991 case 0x4D: /* AVN */ 2992 return 1; 2993 } 2994 return 0; 2995 } 2996 2997 int is_knl(unsigned int family, unsigned int model) 2998 { 2999 if (!genuine_intel) 3000 return 0; 3001 switch (model) { 3002 case 0x57: /* KNL */ 3003 return 1; 3004 } 3005 return 0; 3006 } 3007 3008 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3009 { 3010 if (is_knl(family, model)) 3011 return 1024; 3012 return 1; 3013 } 3014 3015 #define SLM_BCLK_FREQS 5 3016 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3017 3018 double slm_bclk(void) 3019 { 3020 unsigned long long msr = 3; 3021 unsigned int i; 3022 double freq; 3023 3024 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3025 fprintf(outf, "SLM BCLK: unknown\n"); 3026 3027 i = msr & 0xf; 3028 if (i >= SLM_BCLK_FREQS) { 3029 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3030 msr = 3; 3031 } 3032 freq = slm_freq_table[i]; 3033 3034 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3035 3036 return freq; 3037 } 3038 3039 double discover_bclk(unsigned int family, unsigned int model) 3040 { 3041 if (has_snb_msrs(family, model) || is_knl(family, model)) 3042 return 100.00; 3043 else if (is_slm(family, model)) 3044 return slm_bclk(); 3045 else 3046 return 133.33; 3047 } 3048 3049 /* 3050 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3051 * the Thermal Control Circuit (TCC) activates. 3052 * This is usually equal to tjMax. 3053 * 3054 * Older processors do not have this MSR, so there we guess, 3055 * but also allow cmdline over-ride with -T. 3056 * 3057 * Several MSR temperature values are in units of degrees-C 3058 * below this value, including the Digital Thermal Sensor (DTS), 3059 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3060 */ 3061 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3062 { 3063 unsigned long long msr; 3064 unsigned int target_c_local; 3065 int cpu; 3066 3067 /* tcc_activation_temp is used only for dts or ptm */ 3068 if (!(do_dts || do_ptm)) 3069 return 0; 3070 3071 /* this is a per-package concept */ 3072 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3073 return 0; 3074 3075 cpu = t->cpu_id; 3076 if (cpu_migrate(cpu)) { 3077 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3078 return -1; 3079 } 3080 3081 if (tcc_activation_temp_override != 0) { 3082 tcc_activation_temp = tcc_activation_temp_override; 3083 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3084 cpu, tcc_activation_temp); 3085 return 0; 3086 } 3087 3088 /* Temperature Target MSR is Nehalem and newer only */ 3089 if (!do_nhm_platform_info) 3090 goto guess; 3091 3092 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3093 goto guess; 3094 3095 target_c_local = (msr >> 16) & 0xFF; 3096 3097 if (debug) 3098 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3099 cpu, msr, target_c_local); 3100 3101 if (!target_c_local) 3102 goto guess; 3103 3104 tcc_activation_temp = target_c_local; 3105 3106 return 0; 3107 3108 guess: 3109 tcc_activation_temp = TJMAX_DEFAULT; 3110 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3111 cpu, tcc_activation_temp); 3112 3113 return 0; 3114 } 3115 3116 void decode_feature_control_msr(void) 3117 { 3118 unsigned long long msr; 3119 3120 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3121 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3122 base_cpu, msr, 3123 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3124 msr & (1 << 18) ? "SGX" : ""); 3125 } 3126 3127 void decode_misc_enable_msr(void) 3128 { 3129 unsigned long long msr; 3130 3131 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3132 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", 3133 base_cpu, msr, 3134 msr & (1 << 3) ? "TCC" : "", 3135 msr & (1 << 16) ? "EIST" : "", 3136 msr & (1 << 18) ? "MONITOR" : ""); 3137 } 3138 3139 /* 3140 * Decode MSR_MISC_PWR_MGMT 3141 * 3142 * Decode the bits according to the Nehalem documentation 3143 * bit[0] seems to continue to have same meaning going forward 3144 * bit[1] less so... 3145 */ 3146 void decode_misc_pwr_mgmt_msr(void) 3147 { 3148 unsigned long long msr; 3149 3150 if (!do_nhm_platform_info) 3151 return; 3152 3153 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3154 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n", 3155 base_cpu, msr, 3156 msr & (1 << 0) ? "DIS" : "EN", 3157 msr & (1 << 1) ? "EN" : "DIS"); 3158 } 3159 3160 void process_cpuid() 3161 { 3162 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3163 unsigned int fms, family, model, stepping; 3164 3165 eax = ebx = ecx = edx = 0; 3166 3167 __cpuid(0, max_level, ebx, ecx, edx); 3168 3169 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3170 genuine_intel = 1; 3171 3172 if (debug) 3173 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3174 (char *)&ebx, (char *)&edx, (char *)&ecx); 3175 3176 __cpuid(1, fms, ebx, ecx, edx); 3177 family = (fms >> 8) & 0xf; 3178 model = (fms >> 4) & 0xf; 3179 stepping = fms & 0xf; 3180 if (family == 6 || family == 0xf) 3181 model += ((fms >> 16) & 0xf) << 4; 3182 3183 if (debug) { 3184 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3185 max_level, family, model, stepping, family, model, stepping); 3186 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3187 ecx & (1 << 0) ? "SSE3" : "-", 3188 ecx & (1 << 3) ? "MONITOR" : "-", 3189 ecx & (1 << 6) ? "SMX" : "-", 3190 ecx & (1 << 7) ? "EIST" : "-", 3191 ecx & (1 << 8) ? "TM2" : "-", 3192 edx & (1 << 4) ? "TSC" : "-", 3193 edx & (1 << 5) ? "MSR" : "-", 3194 edx & (1 << 22) ? "ACPI-TM" : "-", 3195 edx & (1 << 29) ? "TM" : "-"); 3196 } 3197 3198 if (!(edx & (1 << 5))) 3199 errx(1, "CPUID: no MSR"); 3200 3201 /* 3202 * check max extended function levels of CPUID. 3203 * This is needed to check for invariant TSC. 3204 * This check is valid for both Intel and AMD. 3205 */ 3206 ebx = ecx = edx = 0; 3207 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3208 3209 if (max_extended_level >= 0x80000007) { 3210 3211 /* 3212 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3213 * this check is valid for both Intel and AMD 3214 */ 3215 __cpuid(0x80000007, eax, ebx, ecx, edx); 3216 has_invariant_tsc = edx & (1 << 8); 3217 } 3218 3219 /* 3220 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3221 * this check is valid for both Intel and AMD 3222 */ 3223 3224 __cpuid(0x6, eax, ebx, ecx, edx); 3225 has_aperf = ecx & (1 << 0); 3226 do_dts = eax & (1 << 0); 3227 do_ptm = eax & (1 << 6); 3228 has_hwp = eax & (1 << 7); 3229 has_hwp_notify = eax & (1 << 8); 3230 has_hwp_activity_window = eax & (1 << 9); 3231 has_hwp_epp = eax & (1 << 10); 3232 has_hwp_pkg = eax & (1 << 11); 3233 has_epb = ecx & (1 << 3); 3234 3235 if (debug) 3236 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, " 3237 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3238 has_aperf ? "" : "No-", 3239 do_dts ? "" : "No-", 3240 do_ptm ? "" : "No-", 3241 has_hwp ? "" : "No-", 3242 has_hwp_notify ? "" : "No-", 3243 has_hwp_activity_window ? "" : "No-", 3244 has_hwp_epp ? "" : "No-", 3245 has_hwp_pkg ? "" : "No-", 3246 has_epb ? "" : "No-"); 3247 3248 if (debug) 3249 decode_misc_enable_msr(); 3250 3251 if (max_level >= 0x7 && debug) { 3252 int has_sgx; 3253 3254 ecx = 0; 3255 3256 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3257 3258 has_sgx = ebx & (1 << 2); 3259 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3260 3261 if (has_sgx) 3262 decode_feature_control_msr(); 3263 } 3264 3265 if (max_level >= 0x15) { 3266 unsigned int eax_crystal; 3267 unsigned int ebx_tsc; 3268 3269 /* 3270 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3271 */ 3272 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3273 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3274 3275 if (ebx_tsc != 0) { 3276 3277 if (debug && (ebx != 0)) 3278 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3279 eax_crystal, ebx_tsc, crystal_hz); 3280 3281 if (crystal_hz == 0) 3282 switch(model) { 3283 case 0x4E: /* SKL */ 3284 case 0x5E: /* SKL */ 3285 crystal_hz = 24000000; /* 24.0 MHz */ 3286 break; 3287 case 0x55: /* SKX */ 3288 crystal_hz = 25000000; /* 25.0 MHz */ 3289 break; 3290 case 0x5C: /* BXT */ 3291 crystal_hz = 19200000; /* 19.2 MHz */ 3292 break; 3293 default: 3294 crystal_hz = 0; 3295 } 3296 3297 if (crystal_hz) { 3298 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3299 if (debug) 3300 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3301 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3302 } 3303 } 3304 } 3305 if (max_level >= 0x16) { 3306 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3307 3308 /* 3309 * CPUID 16H Base MHz, Max MHz, Bus MHz 3310 */ 3311 base_mhz = max_mhz = bus_mhz = edx = 0; 3312 3313 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3314 if (debug) 3315 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3316 base_mhz, max_mhz, bus_mhz); 3317 } 3318 3319 if (has_aperf) 3320 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3321 3322 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model); 3323 do_snb_cstates = has_snb_msrs(family, model); 3324 do_irtl_snb = has_snb_msrs(family, model); 3325 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); 3326 do_pc3 = (pkg_cstate_limit >= PCL__3); 3327 do_pc6 = (pkg_cstate_limit >= PCL__6); 3328 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); 3329 do_c8_c9_c10 = has_hsw_msrs(family, model); 3330 do_irtl_hsw = has_hsw_msrs(family, model); 3331 do_skl_residency = has_skl_msrs(family, model); 3332 do_slm_cstates = is_slm(family, model); 3333 do_knl_cstates = is_knl(family, model); 3334 3335 if (debug) 3336 decode_misc_pwr_mgmt_msr(); 3337 3338 rapl_probe(family, model); 3339 perf_limit_reasons_probe(family, model); 3340 3341 if (debug) 3342 dump_cstate_pstate_config_info(family, model); 3343 3344 if (has_skl_msrs(family, model)) 3345 calculate_tsc_tweak(); 3346 3347 do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK); 3348 3349 do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK); 3350 3351 return; 3352 } 3353 3354 void help() 3355 { 3356 fprintf(outf, 3357 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3358 "\n" 3359 "Turbostat forks the specified COMMAND and prints statistics\n" 3360 "when COMMAND completes.\n" 3361 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3362 "to print statistics, until interrupted.\n" 3363 "--debug run in \"debug\" mode\n" 3364 "--interval sec Override default 5-second measurement interval\n" 3365 "--help print this help message\n" 3366 "--counter msr print 32-bit counter at address \"msr\"\n" 3367 "--Counter msr print 64-bit Counter at address \"msr\"\n" 3368 "--out file create or truncate \"file\" for all output\n" 3369 "--msr msr print 32-bit value at address \"msr\"\n" 3370 "--MSR msr print 64-bit Value at address \"msr\"\n" 3371 "--version print version information\n" 3372 "\n" 3373 "For more help, run \"man turbostat\"\n"); 3374 } 3375 3376 3377 /* 3378 * in /dev/cpu/ return success for names that are numbers 3379 * ie. filter out ".", "..", "microcode". 3380 */ 3381 int dir_filter(const struct dirent *dirp) 3382 { 3383 if (isdigit(dirp->d_name[0])) 3384 return 1; 3385 else 3386 return 0; 3387 } 3388 3389 int open_dev_cpu_msr(int dummy1) 3390 { 3391 return 0; 3392 } 3393 3394 void topology_probe() 3395 { 3396 int i; 3397 int max_core_id = 0; 3398 int max_package_id = 0; 3399 int max_siblings = 0; 3400 struct cpu_topology { 3401 int core_id; 3402 int physical_package_id; 3403 } *cpus; 3404 3405 /* Initialize num_cpus, max_cpu_num */ 3406 topo.num_cpus = 0; 3407 topo.max_cpu_num = 0; 3408 for_all_proc_cpus(count_cpus); 3409 if (!summary_only && topo.num_cpus > 1) 3410 show_cpu = 1; 3411 3412 if (debug > 1) 3413 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3414 3415 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3416 if (cpus == NULL) 3417 err(1, "calloc cpus"); 3418 3419 /* 3420 * Allocate and initialize cpu_present_set 3421 */ 3422 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3423 if (cpu_present_set == NULL) 3424 err(3, "CPU_ALLOC"); 3425 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3426 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3427 for_all_proc_cpus(mark_cpu_present); 3428 3429 /* 3430 * Allocate and initialize cpu_affinity_set 3431 */ 3432 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3433 if (cpu_affinity_set == NULL) 3434 err(3, "CPU_ALLOC"); 3435 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3436 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3437 3438 3439 /* 3440 * For online cpus 3441 * find max_core_id, max_package_id 3442 */ 3443 for (i = 0; i <= topo.max_cpu_num; ++i) { 3444 int siblings; 3445 3446 if (cpu_is_not_present(i)) { 3447 if (debug > 1) 3448 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3449 continue; 3450 } 3451 cpus[i].core_id = get_core_id(i); 3452 if (cpus[i].core_id > max_core_id) 3453 max_core_id = cpus[i].core_id; 3454 3455 cpus[i].physical_package_id = get_physical_package_id(i); 3456 if (cpus[i].physical_package_id > max_package_id) 3457 max_package_id = cpus[i].physical_package_id; 3458 3459 siblings = get_num_ht_siblings(i); 3460 if (siblings > max_siblings) 3461 max_siblings = siblings; 3462 if (debug > 1) 3463 fprintf(outf, "cpu %d pkg %d core %d\n", 3464 i, cpus[i].physical_package_id, cpus[i].core_id); 3465 } 3466 topo.num_cores_per_pkg = max_core_id + 1; 3467 if (debug > 1) 3468 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 3469 max_core_id, topo.num_cores_per_pkg); 3470 if (debug && !summary_only && topo.num_cores_per_pkg > 1) 3471 show_core = 1; 3472 3473 topo.num_packages = max_package_id + 1; 3474 if (debug > 1) 3475 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 3476 max_package_id, topo.num_packages); 3477 if (debug && !summary_only && topo.num_packages > 1) 3478 show_pkg = 1; 3479 3480 topo.num_threads_per_core = max_siblings; 3481 if (debug > 1) 3482 fprintf(outf, "max_siblings %d\n", max_siblings); 3483 3484 free(cpus); 3485 } 3486 3487 void 3488 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 3489 { 3490 int i; 3491 3492 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 3493 topo.num_packages, sizeof(struct thread_data)); 3494 if (*t == NULL) 3495 goto error; 3496 3497 for (i = 0; i < topo.num_threads_per_core * 3498 topo.num_cores_per_pkg * topo.num_packages; i++) 3499 (*t)[i].cpu_id = -1; 3500 3501 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 3502 sizeof(struct core_data)); 3503 if (*c == NULL) 3504 goto error; 3505 3506 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 3507 (*c)[i].core_id = -1; 3508 3509 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 3510 if (*p == NULL) 3511 goto error; 3512 3513 for (i = 0; i < topo.num_packages; i++) 3514 (*p)[i].package_id = i; 3515 3516 return; 3517 error: 3518 err(1, "calloc counters"); 3519 } 3520 /* 3521 * init_counter() 3522 * 3523 * set cpu_id, core_num, pkg_num 3524 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 3525 * 3526 * increment topo.num_cores when 1st core in pkg seen 3527 */ 3528 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 3529 struct pkg_data *pkg_base, int thread_num, int core_num, 3530 int pkg_num, int cpu_id) 3531 { 3532 struct thread_data *t; 3533 struct core_data *c; 3534 struct pkg_data *p; 3535 3536 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 3537 c = GET_CORE(core_base, core_num, pkg_num); 3538 p = GET_PKG(pkg_base, pkg_num); 3539 3540 t->cpu_id = cpu_id; 3541 if (thread_num == 0) { 3542 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 3543 if (cpu_is_first_core_in_package(cpu_id)) 3544 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 3545 } 3546 3547 c->core_id = core_num; 3548 p->package_id = pkg_num; 3549 } 3550 3551 3552 int initialize_counters(int cpu_id) 3553 { 3554 int my_thread_id, my_core_id, my_package_id; 3555 3556 my_package_id = get_physical_package_id(cpu_id); 3557 my_core_id = get_core_id(cpu_id); 3558 my_thread_id = get_cpu_position_in_core(cpu_id); 3559 if (!my_thread_id) 3560 topo.num_cores++; 3561 3562 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3563 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3564 return 0; 3565 } 3566 3567 void allocate_output_buffer() 3568 { 3569 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 3570 outp = output_buffer; 3571 if (outp == NULL) 3572 err(-1, "calloc output buffer"); 3573 } 3574 void allocate_fd_percpu(void) 3575 { 3576 fd_percpu = calloc(topo.max_cpu_num, sizeof(int)); 3577 if (fd_percpu == NULL) 3578 err(-1, "calloc fd_percpu"); 3579 } 3580 void allocate_irq_buffers(void) 3581 { 3582 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 3583 if (irq_column_2_cpu == NULL) 3584 err(-1, "calloc %d", topo.num_cpus); 3585 3586 irqs_per_cpu = calloc(topo.max_cpu_num, sizeof(int)); 3587 if (irqs_per_cpu == NULL) 3588 err(-1, "calloc %d", topo.max_cpu_num); 3589 } 3590 void setup_all_buffers(void) 3591 { 3592 topology_probe(); 3593 allocate_irq_buffers(); 3594 allocate_fd_percpu(); 3595 allocate_counters(&thread_even, &core_even, &package_even); 3596 allocate_counters(&thread_odd, &core_odd, &package_odd); 3597 allocate_output_buffer(); 3598 for_all_proc_cpus(initialize_counters); 3599 } 3600 3601 void set_base_cpu(void) 3602 { 3603 base_cpu = sched_getcpu(); 3604 if (base_cpu < 0) 3605 err(-ENODEV, "No valid cpus found"); 3606 3607 if (debug > 1) 3608 fprintf(outf, "base_cpu = %d\n", base_cpu); 3609 } 3610 3611 void turbostat_init() 3612 { 3613 setup_all_buffers(); 3614 set_base_cpu(); 3615 check_dev_msr(); 3616 check_permissions(); 3617 process_cpuid(); 3618 3619 3620 if (debug) 3621 for_all_cpus(print_hwp, ODD_COUNTERS); 3622 3623 if (debug) 3624 for_all_cpus(print_epb, ODD_COUNTERS); 3625 3626 if (debug) 3627 for_all_cpus(print_perf_limit, ODD_COUNTERS); 3628 3629 if (debug) 3630 for_all_cpus(print_rapl, ODD_COUNTERS); 3631 3632 for_all_cpus(set_temperature_target, ODD_COUNTERS); 3633 3634 if (debug) 3635 for_all_cpus(print_thermal, ODD_COUNTERS); 3636 3637 if (debug && do_irtl_snb) 3638 print_irtl(); 3639 } 3640 3641 int fork_it(char **argv) 3642 { 3643 pid_t child_pid; 3644 int status; 3645 3646 status = for_all_cpus(get_counters, EVEN_COUNTERS); 3647 if (status) 3648 exit(status); 3649 /* clear affinity side-effect of get_counters() */ 3650 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 3651 gettimeofday(&tv_even, (struct timezone *)NULL); 3652 3653 child_pid = fork(); 3654 if (!child_pid) { 3655 /* child */ 3656 execvp(argv[0], argv); 3657 } else { 3658 3659 /* parent */ 3660 if (child_pid == -1) 3661 err(1, "fork"); 3662 3663 signal(SIGINT, SIG_IGN); 3664 signal(SIGQUIT, SIG_IGN); 3665 if (waitpid(child_pid, &status, 0) == -1) 3666 err(status, "waitpid"); 3667 } 3668 /* 3669 * n.b. fork_it() does not check for errors from for_all_cpus() 3670 * because re-starting is problematic when forking 3671 */ 3672 for_all_cpus(get_counters, ODD_COUNTERS); 3673 gettimeofday(&tv_odd, (struct timezone *)NULL); 3674 timersub(&tv_odd, &tv_even, &tv_delta); 3675 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); 3676 compute_average(EVEN_COUNTERS); 3677 format_all_counters(EVEN_COUNTERS); 3678 3679 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 3680 3681 flush_output_stderr(); 3682 3683 return status; 3684 } 3685 3686 int get_and_dump_counters(void) 3687 { 3688 int status; 3689 3690 status = for_all_cpus(get_counters, ODD_COUNTERS); 3691 if (status) 3692 return status; 3693 3694 status = for_all_cpus(dump_counters, ODD_COUNTERS); 3695 if (status) 3696 return status; 3697 3698 flush_output_stdout(); 3699 3700 return status; 3701 } 3702 3703 void print_version() { 3704 fprintf(outf, "turbostat version 4.12 5 Apr 2016" 3705 " - Len Brown <lenb@kernel.org>\n"); 3706 } 3707 3708 void cmdline(int argc, char **argv) 3709 { 3710 int opt; 3711 int option_index = 0; 3712 static struct option long_options[] = { 3713 {"Counter", required_argument, 0, 'C'}, 3714 {"counter", required_argument, 0, 'c'}, 3715 {"Dump", no_argument, 0, 'D'}, 3716 {"debug", no_argument, 0, 'd'}, 3717 {"interval", required_argument, 0, 'i'}, 3718 {"help", no_argument, 0, 'h'}, 3719 {"Joules", no_argument, 0, 'J'}, 3720 {"MSR", required_argument, 0, 'M'}, 3721 {"msr", required_argument, 0, 'm'}, 3722 {"out", required_argument, 0, 'o'}, 3723 {"Package", no_argument, 0, 'p'}, 3724 {"processor", no_argument, 0, 'p'}, 3725 {"Summary", no_argument, 0, 'S'}, 3726 {"TCC", required_argument, 0, 'T'}, 3727 {"version", no_argument, 0, 'v' }, 3728 {0, 0, 0, 0 } 3729 }; 3730 3731 progname = argv[0]; 3732 3733 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", 3734 long_options, &option_index)) != -1) { 3735 switch (opt) { 3736 case 'C': 3737 sscanf(optarg, "%x", &extra_delta_offset64); 3738 break; 3739 case 'c': 3740 sscanf(optarg, "%x", &extra_delta_offset32); 3741 break; 3742 case 'D': 3743 dump_only++; 3744 break; 3745 case 'd': 3746 debug++; 3747 break; 3748 case 'h': 3749 default: 3750 help(); 3751 exit(1); 3752 case 'i': 3753 { 3754 double interval = strtod(optarg, NULL); 3755 3756 if (interval < 0.001) { 3757 fprintf(outf, "interval %f seconds is too small\n", 3758 interval); 3759 exit(2); 3760 } 3761 3762 interval_ts.tv_sec = interval; 3763 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 3764 } 3765 break; 3766 case 'J': 3767 rapl_joules++; 3768 break; 3769 case 'M': 3770 sscanf(optarg, "%x", &extra_msr_offset64); 3771 break; 3772 case 'm': 3773 sscanf(optarg, "%x", &extra_msr_offset32); 3774 break; 3775 case 'o': 3776 outf = fopen_or_die(optarg, "w"); 3777 break; 3778 case 'P': 3779 show_pkg_only++; 3780 break; 3781 case 'p': 3782 show_core_only++; 3783 break; 3784 case 'S': 3785 summary_only++; 3786 break; 3787 case 'T': 3788 tcc_activation_temp_override = atoi(optarg); 3789 break; 3790 case 'v': 3791 print_version(); 3792 exit(0); 3793 break; 3794 } 3795 } 3796 } 3797 3798 int main(int argc, char **argv) 3799 { 3800 outf = stderr; 3801 3802 cmdline(argc, argv); 3803 3804 if (debug) 3805 print_version(); 3806 3807 turbostat_init(); 3808 3809 /* dump counters and exit */ 3810 if (dump_only) 3811 return get_and_dump_counters(); 3812 3813 /* 3814 * if any params left, it must be a command to fork 3815 */ 3816 if (argc - optind) 3817 return fork_it(argv + optind); 3818 else 3819 turbostat_loop(); 3820 3821 return 0; 3822 } 3823