1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include <stdarg.h> 25 #include <stdio.h> 26 #include <err.h> 27 #include <unistd.h> 28 #include <sys/types.h> 29 #include <sys/wait.h> 30 #include <sys/stat.h> 31 #include <sys/resource.h> 32 #include <fcntl.h> 33 #include <signal.h> 34 #include <sys/time.h> 35 #include <stdlib.h> 36 #include <getopt.h> 37 #include <dirent.h> 38 #include <string.h> 39 #include <ctype.h> 40 #include <sched.h> 41 #include <time.h> 42 #include <cpuid.h> 43 #include <linux/capability.h> 44 #include <errno.h> 45 46 char *proc_stat = "/proc/stat"; 47 FILE *outf; 48 int *fd_percpu; 49 struct timespec interval_ts = {5, 0}; 50 unsigned int debug; 51 unsigned int rapl_joules; 52 unsigned int summary_only; 53 unsigned int dump_only; 54 unsigned int do_nhm_cstates; 55 unsigned int do_snb_cstates; 56 unsigned int do_knl_cstates; 57 unsigned int do_pc2; 58 unsigned int do_pc3; 59 unsigned int do_pc6; 60 unsigned int do_pc7; 61 unsigned int do_c8_c9_c10; 62 unsigned int do_skl_residency; 63 unsigned int do_slm_cstates; 64 unsigned int use_c1_residency_msr; 65 unsigned int has_aperf; 66 unsigned int has_epb; 67 unsigned int do_irtl_snb; 68 unsigned int do_irtl_hsw; 69 unsigned int units = 1000000; /* MHz etc */ 70 unsigned int genuine_intel; 71 unsigned int has_invariant_tsc; 72 unsigned int do_nhm_platform_info; 73 unsigned int extra_msr_offset32; 74 unsigned int extra_msr_offset64; 75 unsigned int extra_delta_offset32; 76 unsigned int extra_delta_offset64; 77 unsigned int aperf_mperf_multiplier = 1; 78 int do_irq = 1; 79 int do_smi; 80 double bclk; 81 double base_hz; 82 unsigned int has_base_hz; 83 double tsc_tweak = 1.0; 84 unsigned int show_pkg; 85 unsigned int show_core; 86 unsigned int show_cpu; 87 unsigned int show_pkg_only; 88 unsigned int show_core_only; 89 char *output_buffer, *outp; 90 unsigned int do_rapl; 91 unsigned int do_dts; 92 unsigned int do_ptm; 93 unsigned int do_gfx_rc6_ms; 94 unsigned long long gfx_cur_rc6_ms; 95 unsigned int do_gfx_mhz; 96 unsigned int gfx_cur_mhz; 97 unsigned int tcc_activation_temp; 98 unsigned int tcc_activation_temp_override; 99 double rapl_power_units, rapl_time_units; 100 double rapl_dram_energy_units, rapl_energy_units; 101 double rapl_joule_counter_range; 102 unsigned int do_core_perf_limit_reasons; 103 unsigned int do_gfx_perf_limit_reasons; 104 unsigned int do_ring_perf_limit_reasons; 105 unsigned int crystal_hz; 106 unsigned long long tsc_hz; 107 int base_cpu; 108 double discover_bclk(unsigned int family, unsigned int model); 109 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 110 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 111 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 112 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 113 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 114 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 115 116 #define RAPL_PKG (1 << 0) 117 /* 0x610 MSR_PKG_POWER_LIMIT */ 118 /* 0x611 MSR_PKG_ENERGY_STATUS */ 119 #define RAPL_PKG_PERF_STATUS (1 << 1) 120 /* 0x613 MSR_PKG_PERF_STATUS */ 121 #define RAPL_PKG_POWER_INFO (1 << 2) 122 /* 0x614 MSR_PKG_POWER_INFO */ 123 124 #define RAPL_DRAM (1 << 3) 125 /* 0x618 MSR_DRAM_POWER_LIMIT */ 126 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 127 #define RAPL_DRAM_PERF_STATUS (1 << 4) 128 /* 0x61b MSR_DRAM_PERF_STATUS */ 129 #define RAPL_DRAM_POWER_INFO (1 << 5) 130 /* 0x61c MSR_DRAM_POWER_INFO */ 131 132 #define RAPL_CORES_POWER_LIMIT (1 << 6) 133 /* 0x638 MSR_PP0_POWER_LIMIT */ 134 #define RAPL_CORE_POLICY (1 << 7) 135 /* 0x63a MSR_PP0_POLICY */ 136 137 #define RAPL_GFX (1 << 8) 138 /* 0x640 MSR_PP1_POWER_LIMIT */ 139 /* 0x641 MSR_PP1_ENERGY_STATUS */ 140 /* 0x642 MSR_PP1_POLICY */ 141 142 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 143 /* 0x639 MSR_PP0_ENERGY_STATUS */ 144 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 145 #define TJMAX_DEFAULT 100 146 147 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 148 149 int backwards_count; 150 char *progname; 151 152 cpu_set_t *cpu_present_set, *cpu_affinity_set; 153 size_t cpu_present_setsize, cpu_affinity_setsize; 154 155 struct thread_data { 156 unsigned long long tsc; 157 unsigned long long aperf; 158 unsigned long long mperf; 159 unsigned long long c1; 160 unsigned long long extra_msr64; 161 unsigned long long extra_delta64; 162 unsigned long long extra_msr32; 163 unsigned long long extra_delta32; 164 unsigned int irq_count; 165 unsigned int smi_count; 166 unsigned int cpu_id; 167 unsigned int flags; 168 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 169 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 170 } *thread_even, *thread_odd; 171 172 struct core_data { 173 unsigned long long c3; 174 unsigned long long c6; 175 unsigned long long c7; 176 unsigned int core_temp_c; 177 unsigned int core_id; 178 } *core_even, *core_odd; 179 180 struct pkg_data { 181 unsigned long long pc2; 182 unsigned long long pc3; 183 unsigned long long pc6; 184 unsigned long long pc7; 185 unsigned long long pc8; 186 unsigned long long pc9; 187 unsigned long long pc10; 188 unsigned long long pkg_wtd_core_c0; 189 unsigned long long pkg_any_core_c0; 190 unsigned long long pkg_any_gfxe_c0; 191 unsigned long long pkg_both_core_gfxe_c0; 192 long long gfx_rc6_ms; 193 unsigned int gfx_mhz; 194 unsigned int package_id; 195 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 196 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 197 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 198 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 199 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 200 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 201 unsigned int pkg_temp_c; 202 203 } *package_even, *package_odd; 204 205 #define ODD_COUNTERS thread_odd, core_odd, package_odd 206 #define EVEN_COUNTERS thread_even, core_even, package_even 207 208 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 209 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 210 topo.num_threads_per_core + \ 211 (core_no) * topo.num_threads_per_core + (thread_no)) 212 #define GET_CORE(core_base, core_no, pkg_no) \ 213 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 214 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 215 216 struct system_summary { 217 struct thread_data threads; 218 struct core_data cores; 219 struct pkg_data packages; 220 } sum, average; 221 222 223 struct topo_params { 224 int num_packages; 225 int num_cpus; 226 int num_cores; 227 int max_cpu_num; 228 int num_cores_per_pkg; 229 int num_threads_per_core; 230 } topo; 231 232 struct timeval tv_even, tv_odd, tv_delta; 233 234 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 235 int *irqs_per_cpu; /* indexed by cpu_num */ 236 237 void setup_all_buffers(void); 238 239 int cpu_is_not_present(int cpu) 240 { 241 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 242 } 243 /* 244 * run func(thread, core, package) in topology order 245 * skip non-present cpus 246 */ 247 248 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 249 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 250 { 251 int retval, pkg_no, core_no, thread_no; 252 253 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 254 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 255 for (thread_no = 0; thread_no < 256 topo.num_threads_per_core; ++thread_no) { 257 struct thread_data *t; 258 struct core_data *c; 259 struct pkg_data *p; 260 261 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 262 263 if (cpu_is_not_present(t->cpu_id)) 264 continue; 265 266 c = GET_CORE(core_base, core_no, pkg_no); 267 p = GET_PKG(pkg_base, pkg_no); 268 269 retval = func(t, c, p); 270 if (retval) 271 return retval; 272 } 273 } 274 } 275 return 0; 276 } 277 278 int cpu_migrate(int cpu) 279 { 280 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 281 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 282 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 283 return -1; 284 else 285 return 0; 286 } 287 int get_msr_fd(int cpu) 288 { 289 char pathname[32]; 290 int fd; 291 292 fd = fd_percpu[cpu]; 293 294 if (fd) 295 return fd; 296 297 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 298 fd = open(pathname, O_RDONLY); 299 if (fd < 0) 300 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 301 302 fd_percpu[cpu] = fd; 303 304 return fd; 305 } 306 307 int get_msr(int cpu, off_t offset, unsigned long long *msr) 308 { 309 ssize_t retval; 310 311 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 312 313 if (retval != sizeof *msr) 314 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset); 315 316 return 0; 317 } 318 319 /* 320 * Example Format w/ field column widths: 321 * 322 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt 323 * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 324 */ 325 326 void print_header(void) 327 { 328 if (show_pkg) 329 outp += sprintf(outp, "\tPackage"); 330 if (show_core) 331 outp += sprintf(outp, "\tCore"); 332 if (show_cpu) 333 outp += sprintf(outp, "\tCPU"); 334 if (has_aperf) 335 outp += sprintf(outp, "\tAvg_MHz"); 336 if (has_aperf) 337 outp += sprintf(outp, "\tBusy%%"); 338 if (has_aperf) 339 outp += sprintf(outp, "\tBzy_MHz"); 340 outp += sprintf(outp, "\tTSC_MHz"); 341 342 if (extra_delta_offset32) 343 outp += sprintf(outp, "\tcount 0x%03X", extra_delta_offset32); 344 if (extra_delta_offset64) 345 outp += sprintf(outp, "\tCOUNT 0x%03X", extra_delta_offset64); 346 if (extra_msr_offset32) 347 outp += sprintf(outp, "\tMSR 0x%03X", extra_msr_offset32); 348 if (extra_msr_offset64) 349 outp += sprintf(outp, "\tMSR 0x%03X", extra_msr_offset64); 350 351 if (!debug) 352 goto done; 353 354 if (do_irq) 355 outp += sprintf(outp, "\tIRQ"); 356 if (do_smi) 357 outp += sprintf(outp, "\tSMI"); 358 359 if (do_nhm_cstates) 360 outp += sprintf(outp, "\tCPU%%c1"); 361 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 362 outp += sprintf(outp, "\tCPU%%c3"); 363 if (do_nhm_cstates) 364 outp += sprintf(outp, "\tCPU%%c6"); 365 if (do_snb_cstates) 366 outp += sprintf(outp, "\tCPU%%c7"); 367 368 if (do_dts) 369 outp += sprintf(outp, "\tCoreTmp"); 370 if (do_ptm) 371 outp += sprintf(outp, "\tPkgTmp"); 372 373 if (do_gfx_rc6_ms) 374 outp += sprintf(outp, "\tGFX%%rc6"); 375 376 if (do_gfx_mhz) 377 outp += sprintf(outp, "\tGFXMHz"); 378 379 if (do_skl_residency) { 380 outp += sprintf(outp, "\tTotl%%C0"); 381 outp += sprintf(outp, "\tAny%%C0"); 382 outp += sprintf(outp, "\tGFX%%C0"); 383 outp += sprintf(outp, "\tCPUGFX%%"); 384 } 385 386 if (do_pc2) 387 outp += sprintf(outp, "\tPkg%%pc2"); 388 if (do_pc3) 389 outp += sprintf(outp, "\tPkg%%pc3"); 390 if (do_pc6) 391 outp += sprintf(outp, "\tPkg%%pc6"); 392 if (do_pc7) 393 outp += sprintf(outp, "\tPkg%%pc7"); 394 if (do_c8_c9_c10) { 395 outp += sprintf(outp, "\tPkg%%pc8"); 396 outp += sprintf(outp, "\tPkg%%pc9"); 397 outp += sprintf(outp, "\tPk%%pc10"); 398 } 399 400 if (do_rapl && !rapl_joules) { 401 if (do_rapl & RAPL_PKG) 402 outp += sprintf(outp, "\tPkgWatt"); 403 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 404 outp += sprintf(outp, "\tCorWatt"); 405 if (do_rapl & RAPL_GFX) 406 outp += sprintf(outp, "\tGFXWatt"); 407 if (do_rapl & RAPL_DRAM) 408 outp += sprintf(outp, "\tRAMWatt"); 409 if (do_rapl & RAPL_PKG_PERF_STATUS) 410 outp += sprintf(outp, "\tPKG_%%"); 411 if (do_rapl & RAPL_DRAM_PERF_STATUS) 412 outp += sprintf(outp, "\tRAM_%%"); 413 } else if (do_rapl && rapl_joules) { 414 if (do_rapl & RAPL_PKG) 415 outp += sprintf(outp, "\tPkg_J"); 416 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 417 outp += sprintf(outp, "\tCor_J"); 418 if (do_rapl & RAPL_GFX) 419 outp += sprintf(outp, "\tGFX_J"); 420 if (do_rapl & RAPL_DRAM) 421 outp += sprintf(outp, "\tRAM_J"); 422 if (do_rapl & RAPL_PKG_PERF_STATUS) 423 outp += sprintf(outp, "\tPKG_%%"); 424 if (do_rapl & RAPL_DRAM_PERF_STATUS) 425 outp += sprintf(outp, "\tRAM_%%"); 426 } 427 done: 428 outp += sprintf(outp, "\n"); 429 } 430 431 int dump_counters(struct thread_data *t, struct core_data *c, 432 struct pkg_data *p) 433 { 434 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 435 436 if (t) { 437 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 438 t->cpu_id, t->flags); 439 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 440 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 441 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 442 outp += sprintf(outp, "c1: %016llX\n", t->c1); 443 outp += sprintf(outp, "msr0x%x: %08llX\n", 444 extra_delta_offset32, t->extra_delta32); 445 outp += sprintf(outp, "msr0x%x: %016llX\n", 446 extra_delta_offset64, t->extra_delta64); 447 outp += sprintf(outp, "msr0x%x: %08llX\n", 448 extra_msr_offset32, t->extra_msr32); 449 outp += sprintf(outp, "msr0x%x: %016llX\n", 450 extra_msr_offset64, t->extra_msr64); 451 if (do_irq) 452 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 453 if (do_smi) 454 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 455 } 456 457 if (c) { 458 outp += sprintf(outp, "core: %d\n", c->core_id); 459 outp += sprintf(outp, "c3: %016llX\n", c->c3); 460 outp += sprintf(outp, "c6: %016llX\n", c->c6); 461 outp += sprintf(outp, "c7: %016llX\n", c->c7); 462 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 463 } 464 465 if (p) { 466 outp += sprintf(outp, "package: %d\n", p->package_id); 467 468 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 469 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 470 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 471 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 472 473 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 474 if (do_pc3) 475 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 476 if (do_pc6) 477 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 478 if (do_pc7) 479 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 480 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 481 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 482 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 483 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 484 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 485 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 486 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 487 outp += sprintf(outp, "Throttle PKG: %0X\n", 488 p->rapl_pkg_perf_status); 489 outp += sprintf(outp, "Throttle RAM: %0X\n", 490 p->rapl_dram_perf_status); 491 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 492 } 493 494 outp += sprintf(outp, "\n"); 495 496 return 0; 497 } 498 499 /* 500 * column formatting convention & formats 501 */ 502 int format_counters(struct thread_data *t, struct core_data *c, 503 struct pkg_data *p) 504 { 505 double interval_float; 506 char *fmt8; 507 508 /* if showing only 1st thread in core and this isn't one, bail out */ 509 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 510 return 0; 511 512 /* if showing only 1st thread in pkg and this isn't one, bail out */ 513 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 514 return 0; 515 516 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 517 518 /* topo columns, print blanks on 1st (average) line */ 519 if (t == &average.threads) { 520 if (show_pkg) 521 outp += sprintf(outp, "\t-"); 522 if (show_core) 523 outp += sprintf(outp, "\t-"); 524 if (show_cpu) 525 outp += sprintf(outp, "\t-"); 526 } else { 527 if (show_pkg) { 528 if (p) 529 outp += sprintf(outp, "\t%d", p->package_id); 530 else 531 outp += sprintf(outp, "\t-"); 532 } 533 if (show_core) { 534 if (c) 535 outp += sprintf(outp, "\t%d", c->core_id); 536 else 537 outp += sprintf(outp, "\t-"); 538 } 539 if (show_cpu) 540 outp += sprintf(outp, "\t%d", t->cpu_id); 541 } 542 543 /* Avg_MHz */ 544 if (has_aperf) 545 outp += sprintf(outp, "\t%.0f", 546 1.0 / units * t->aperf / interval_float); 547 548 /* Busy% */ 549 if (has_aperf) 550 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); 551 552 /* Bzy_MHz */ 553 if (has_aperf) { 554 if (has_base_hz) 555 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); 556 else 557 outp += sprintf(outp, "\t%.0f", 558 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); 559 } 560 561 /* TSC_MHz */ 562 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); 563 564 /* delta */ 565 if (extra_delta_offset32) 566 outp += sprintf(outp, "\t%11llu", t->extra_delta32); 567 568 /* DELTA */ 569 if (extra_delta_offset64) 570 outp += sprintf(outp, "\t%11llu", t->extra_delta64); 571 /* msr */ 572 if (extra_msr_offset32) 573 outp += sprintf(outp, "\t0x%08llx", t->extra_msr32); 574 575 /* MSR */ 576 if (extra_msr_offset64) 577 outp += sprintf(outp, "\t0x%016llx", t->extra_msr64); 578 579 if (!debug) 580 goto done; 581 582 /* IRQ */ 583 if (do_irq) 584 outp += sprintf(outp, "\t%d", t->irq_count); 585 586 /* SMI */ 587 if (do_smi) 588 outp += sprintf(outp, "\t%d", t->smi_count); 589 590 if (do_nhm_cstates) 591 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc); 592 593 /* print per-core data only for 1st thread in core */ 594 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 595 goto done; 596 597 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 598 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc); 599 if (do_nhm_cstates) 600 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc); 601 if (do_snb_cstates) 602 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc); 603 604 if (do_dts) 605 outp += sprintf(outp, "\t%d", c->core_temp_c); 606 607 /* print per-package data only for 1st core in package */ 608 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 609 goto done; 610 611 /* PkgTmp */ 612 if (do_ptm) 613 outp += sprintf(outp, "\t%d", p->pkg_temp_c); 614 615 /* GFXrc6 */ 616 if (do_gfx_rc6_ms) { 617 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 618 outp += sprintf(outp, "\t**.**"); 619 } else { 620 outp += sprintf(outp, "\t%.2f", 621 p->gfx_rc6_ms / 10.0 / interval_float); 622 } 623 } 624 625 /* GFXMHz */ 626 if (do_gfx_mhz) 627 outp += sprintf(outp, "\t%d", p->gfx_mhz); 628 629 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 630 if (do_skl_residency) { 631 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); 632 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc); 633 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); 634 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); 635 } 636 637 if (do_pc2) 638 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc); 639 if (do_pc3) 640 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc); 641 if (do_pc6) 642 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc); 643 if (do_pc7) 644 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc); 645 if (do_c8_c9_c10) { 646 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc); 647 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc); 648 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc); 649 } 650 651 /* 652 * If measurement interval exceeds minimum RAPL Joule Counter range, 653 * indicate that results are suspect by printing "**" in fraction place. 654 */ 655 if (interval_float < rapl_joule_counter_range) 656 fmt8 = "\t%.2f"; 657 else 658 fmt8 = "%6.0f**"; 659 660 if (do_rapl && !rapl_joules) { 661 if (do_rapl & RAPL_PKG) 662 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 663 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 664 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 665 if (do_rapl & RAPL_GFX) 666 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 667 if (do_rapl & RAPL_DRAM) 668 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 669 if (do_rapl & RAPL_PKG_PERF_STATUS) 670 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 671 if (do_rapl & RAPL_DRAM_PERF_STATUS) 672 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 673 } else if (do_rapl && rapl_joules) { 674 if (do_rapl & RAPL_PKG) 675 outp += sprintf(outp, fmt8, 676 p->energy_pkg * rapl_energy_units); 677 if (do_rapl & RAPL_CORES) 678 outp += sprintf(outp, fmt8, 679 p->energy_cores * rapl_energy_units); 680 if (do_rapl & RAPL_GFX) 681 outp += sprintf(outp, fmt8, 682 p->energy_gfx * rapl_energy_units); 683 if (do_rapl & RAPL_DRAM) 684 outp += sprintf(outp, fmt8, 685 p->energy_dram * rapl_dram_energy_units); 686 if (do_rapl & RAPL_PKG_PERF_STATUS) 687 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 688 if (do_rapl & RAPL_DRAM_PERF_STATUS) 689 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 690 } 691 done: 692 outp += sprintf(outp, "\n"); 693 694 return 0; 695 } 696 697 void flush_output_stdout(void) 698 { 699 FILE *filep; 700 701 if (outf == stderr) 702 filep = stdout; 703 else 704 filep = outf; 705 706 fputs(output_buffer, filep); 707 fflush(filep); 708 709 outp = output_buffer; 710 } 711 void flush_output_stderr(void) 712 { 713 fputs(output_buffer, outf); 714 fflush(outf); 715 outp = output_buffer; 716 } 717 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 718 { 719 static int printed; 720 721 if (!printed || !summary_only) 722 print_header(); 723 724 if (topo.num_cpus > 1) 725 format_counters(&average.threads, &average.cores, 726 &average.packages); 727 728 printed = 1; 729 730 if (summary_only) 731 return; 732 733 for_all_cpus(format_counters, t, c, p); 734 } 735 736 #define DELTA_WRAP32(new, old) \ 737 if (new > old) { \ 738 old = new - old; \ 739 } else { \ 740 old = 0x100000000 + new - old; \ 741 } 742 743 int 744 delta_package(struct pkg_data *new, struct pkg_data *old) 745 { 746 747 if (do_skl_residency) { 748 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 749 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 750 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 751 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 752 } 753 old->pc2 = new->pc2 - old->pc2; 754 if (do_pc3) 755 old->pc3 = new->pc3 - old->pc3; 756 if (do_pc6) 757 old->pc6 = new->pc6 - old->pc6; 758 if (do_pc7) 759 old->pc7 = new->pc7 - old->pc7; 760 old->pc8 = new->pc8 - old->pc8; 761 old->pc9 = new->pc9 - old->pc9; 762 old->pc10 = new->pc10 - old->pc10; 763 old->pkg_temp_c = new->pkg_temp_c; 764 765 /* flag an error when rc6 counter resets/wraps */ 766 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 767 old->gfx_rc6_ms = -1; 768 else 769 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 770 771 old->gfx_mhz = new->gfx_mhz; 772 773 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 774 DELTA_WRAP32(new->energy_cores, old->energy_cores); 775 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 776 DELTA_WRAP32(new->energy_dram, old->energy_dram); 777 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 778 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 779 780 return 0; 781 } 782 783 void 784 delta_core(struct core_data *new, struct core_data *old) 785 { 786 old->c3 = new->c3 - old->c3; 787 old->c6 = new->c6 - old->c6; 788 old->c7 = new->c7 - old->c7; 789 old->core_temp_c = new->core_temp_c; 790 } 791 792 /* 793 * old = new - old 794 */ 795 int 796 delta_thread(struct thread_data *new, struct thread_data *old, 797 struct core_data *core_delta) 798 { 799 old->tsc = new->tsc - old->tsc; 800 801 /* check for TSC < 1 Mcycles over interval */ 802 if (old->tsc < (1000 * 1000)) 803 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 804 "You can disable all c-states by booting with \"idle=poll\"\n" 805 "or just the deep ones with \"processor.max_cstate=1\""); 806 807 old->c1 = new->c1 - old->c1; 808 809 if (has_aperf) { 810 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 811 old->aperf = new->aperf - old->aperf; 812 old->mperf = new->mperf - old->mperf; 813 } else { 814 return -1; 815 } 816 } 817 818 819 if (use_c1_residency_msr) { 820 /* 821 * Some models have a dedicated C1 residency MSR, 822 * which should be more accurate than the derivation below. 823 */ 824 } else { 825 /* 826 * As counter collection is not atomic, 827 * it is possible for mperf's non-halted cycles + idle states 828 * to exceed TSC's all cycles: show c1 = 0% in that case. 829 */ 830 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 831 old->c1 = 0; 832 else { 833 /* normal case, derive c1 */ 834 old->c1 = old->tsc - old->mperf - core_delta->c3 835 - core_delta->c6 - core_delta->c7; 836 } 837 } 838 839 if (old->mperf == 0) { 840 if (debug > 1) 841 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 842 old->mperf = 1; /* divide by 0 protection */ 843 } 844 845 old->extra_delta32 = new->extra_delta32 - old->extra_delta32; 846 old->extra_delta32 &= 0xFFFFFFFF; 847 848 old->extra_delta64 = new->extra_delta64 - old->extra_delta64; 849 850 /* 851 * Extra MSR is just a snapshot, simply copy latest w/o subtracting 852 */ 853 old->extra_msr32 = new->extra_msr32; 854 old->extra_msr64 = new->extra_msr64; 855 856 if (do_irq) 857 old->irq_count = new->irq_count - old->irq_count; 858 859 if (do_smi) 860 old->smi_count = new->smi_count - old->smi_count; 861 862 return 0; 863 } 864 865 int delta_cpu(struct thread_data *t, struct core_data *c, 866 struct pkg_data *p, struct thread_data *t2, 867 struct core_data *c2, struct pkg_data *p2) 868 { 869 int retval = 0; 870 871 /* calculate core delta only for 1st thread in core */ 872 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 873 delta_core(c, c2); 874 875 /* always calculate thread delta */ 876 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 877 if (retval) 878 return retval; 879 880 /* calculate package delta only for 1st core in package */ 881 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 882 retval = delta_package(p, p2); 883 884 return retval; 885 } 886 887 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 888 { 889 t->tsc = 0; 890 t->aperf = 0; 891 t->mperf = 0; 892 t->c1 = 0; 893 894 t->extra_delta32 = 0; 895 t->extra_delta64 = 0; 896 897 t->irq_count = 0; 898 t->smi_count = 0; 899 900 /* tells format_counters to dump all fields from this set */ 901 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 902 903 c->c3 = 0; 904 c->c6 = 0; 905 c->c7 = 0; 906 c->core_temp_c = 0; 907 908 p->pkg_wtd_core_c0 = 0; 909 p->pkg_any_core_c0 = 0; 910 p->pkg_any_gfxe_c0 = 0; 911 p->pkg_both_core_gfxe_c0 = 0; 912 913 p->pc2 = 0; 914 if (do_pc3) 915 p->pc3 = 0; 916 if (do_pc6) 917 p->pc6 = 0; 918 if (do_pc7) 919 p->pc7 = 0; 920 p->pc8 = 0; 921 p->pc9 = 0; 922 p->pc10 = 0; 923 924 p->energy_pkg = 0; 925 p->energy_dram = 0; 926 p->energy_cores = 0; 927 p->energy_gfx = 0; 928 p->rapl_pkg_perf_status = 0; 929 p->rapl_dram_perf_status = 0; 930 p->pkg_temp_c = 0; 931 932 p->gfx_rc6_ms = 0; 933 p->gfx_mhz = 0; 934 } 935 int sum_counters(struct thread_data *t, struct core_data *c, 936 struct pkg_data *p) 937 { 938 average.threads.tsc += t->tsc; 939 average.threads.aperf += t->aperf; 940 average.threads.mperf += t->mperf; 941 average.threads.c1 += t->c1; 942 943 average.threads.extra_delta32 += t->extra_delta32; 944 average.threads.extra_delta64 += t->extra_delta64; 945 946 average.threads.irq_count += t->irq_count; 947 average.threads.smi_count += t->smi_count; 948 949 /* sum per-core values only for 1st thread in core */ 950 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 951 return 0; 952 953 average.cores.c3 += c->c3; 954 average.cores.c6 += c->c6; 955 average.cores.c7 += c->c7; 956 957 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 958 959 /* sum per-pkg values only for 1st core in pkg */ 960 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 961 return 0; 962 963 if (do_skl_residency) { 964 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 965 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 966 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 967 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 968 } 969 970 average.packages.pc2 += p->pc2; 971 if (do_pc3) 972 average.packages.pc3 += p->pc3; 973 if (do_pc6) 974 average.packages.pc6 += p->pc6; 975 if (do_pc7) 976 average.packages.pc7 += p->pc7; 977 average.packages.pc8 += p->pc8; 978 average.packages.pc9 += p->pc9; 979 average.packages.pc10 += p->pc10; 980 981 average.packages.energy_pkg += p->energy_pkg; 982 average.packages.energy_dram += p->energy_dram; 983 average.packages.energy_cores += p->energy_cores; 984 average.packages.energy_gfx += p->energy_gfx; 985 986 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 987 average.packages.gfx_mhz = p->gfx_mhz; 988 989 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 990 991 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 992 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 993 return 0; 994 } 995 /* 996 * sum the counters for all cpus in the system 997 * compute the weighted average 998 */ 999 void compute_average(struct thread_data *t, struct core_data *c, 1000 struct pkg_data *p) 1001 { 1002 clear_counters(&average.threads, &average.cores, &average.packages); 1003 1004 for_all_cpus(sum_counters, t, c, p); 1005 1006 average.threads.tsc /= topo.num_cpus; 1007 average.threads.aperf /= topo.num_cpus; 1008 average.threads.mperf /= topo.num_cpus; 1009 average.threads.c1 /= topo.num_cpus; 1010 1011 average.threads.extra_delta32 /= topo.num_cpus; 1012 average.threads.extra_delta32 &= 0xFFFFFFFF; 1013 1014 average.threads.extra_delta64 /= topo.num_cpus; 1015 1016 average.cores.c3 /= topo.num_cores; 1017 average.cores.c6 /= topo.num_cores; 1018 average.cores.c7 /= topo.num_cores; 1019 1020 if (do_skl_residency) { 1021 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1022 average.packages.pkg_any_core_c0 /= topo.num_packages; 1023 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1024 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1025 } 1026 1027 average.packages.pc2 /= topo.num_packages; 1028 if (do_pc3) 1029 average.packages.pc3 /= topo.num_packages; 1030 if (do_pc6) 1031 average.packages.pc6 /= topo.num_packages; 1032 if (do_pc7) 1033 average.packages.pc7 /= topo.num_packages; 1034 1035 average.packages.pc8 /= topo.num_packages; 1036 average.packages.pc9 /= topo.num_packages; 1037 average.packages.pc10 /= topo.num_packages; 1038 } 1039 1040 static unsigned long long rdtsc(void) 1041 { 1042 unsigned int low, high; 1043 1044 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1045 1046 return low | ((unsigned long long)high) << 32; 1047 } 1048 1049 /* 1050 * get_counters(...) 1051 * migrate to cpu 1052 * acquire and record local counters for that cpu 1053 */ 1054 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1055 { 1056 int cpu = t->cpu_id; 1057 unsigned long long msr; 1058 int aperf_mperf_retry_count = 0; 1059 1060 if (cpu_migrate(cpu)) { 1061 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1062 return -1; 1063 } 1064 1065 retry: 1066 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1067 1068 if (has_aperf) { 1069 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1070 1071 /* 1072 * The TSC, APERF and MPERF must be read together for 1073 * APERF/MPERF and MPERF/TSC to give accurate results. 1074 * 1075 * Unfortunately, APERF and MPERF are read by 1076 * individual system call, so delays may occur 1077 * between them. If the time to read them 1078 * varies by a large amount, we re-read them. 1079 */ 1080 1081 /* 1082 * This initial dummy APERF read has been seen to 1083 * reduce jitter in the subsequent reads. 1084 */ 1085 1086 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1087 return -3; 1088 1089 t->tsc = rdtsc(); /* re-read close to APERF */ 1090 1091 tsc_before = t->tsc; 1092 1093 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1094 return -3; 1095 1096 tsc_between = rdtsc(); 1097 1098 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1099 return -4; 1100 1101 tsc_after = rdtsc(); 1102 1103 aperf_time = tsc_between - tsc_before; 1104 mperf_time = tsc_after - tsc_between; 1105 1106 /* 1107 * If the system call latency to read APERF and MPERF 1108 * differ by more than 2x, then try again. 1109 */ 1110 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1111 aperf_mperf_retry_count++; 1112 if (aperf_mperf_retry_count < 5) 1113 goto retry; 1114 else 1115 warnx("cpu%d jitter %lld %lld", 1116 cpu, aperf_time, mperf_time); 1117 } 1118 aperf_mperf_retry_count = 0; 1119 1120 t->aperf = t->aperf * aperf_mperf_multiplier; 1121 t->mperf = t->mperf * aperf_mperf_multiplier; 1122 } 1123 1124 if (do_irq) 1125 t->irq_count = irqs_per_cpu[cpu]; 1126 if (do_smi) { 1127 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1128 return -5; 1129 t->smi_count = msr & 0xFFFFFFFF; 1130 } 1131 if (extra_delta_offset32) { 1132 if (get_msr(cpu, extra_delta_offset32, &msr)) 1133 return -5; 1134 t->extra_delta32 = msr & 0xFFFFFFFF; 1135 } 1136 1137 if (extra_delta_offset64) 1138 if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64)) 1139 return -5; 1140 1141 if (extra_msr_offset32) { 1142 if (get_msr(cpu, extra_msr_offset32, &msr)) 1143 return -5; 1144 t->extra_msr32 = msr & 0xFFFFFFFF; 1145 } 1146 1147 if (extra_msr_offset64) 1148 if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64)) 1149 return -5; 1150 1151 if (use_c1_residency_msr) { 1152 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1153 return -6; 1154 } 1155 1156 /* collect core counters only for 1st thread in core */ 1157 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1158 return 0; 1159 1160 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) { 1161 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1162 return -6; 1163 } 1164 1165 if (do_nhm_cstates && !do_knl_cstates) { 1166 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1167 return -7; 1168 } else if (do_knl_cstates) { 1169 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1170 return -7; 1171 } 1172 1173 if (do_snb_cstates) 1174 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1175 return -8; 1176 1177 if (do_dts) { 1178 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1179 return -9; 1180 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1181 } 1182 1183 1184 /* collect package counters only for 1st core in package */ 1185 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1186 return 0; 1187 1188 if (do_skl_residency) { 1189 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1190 return -10; 1191 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1192 return -11; 1193 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1194 return -12; 1195 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1196 return -13; 1197 } 1198 if (do_pc3) 1199 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1200 return -9; 1201 if (do_pc6) 1202 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1203 return -10; 1204 if (do_pc2) 1205 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1206 return -11; 1207 if (do_pc7) 1208 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1209 return -12; 1210 if (do_c8_c9_c10) { 1211 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1212 return -13; 1213 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1214 return -13; 1215 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1216 return -13; 1217 } 1218 if (do_rapl & RAPL_PKG) { 1219 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1220 return -13; 1221 p->energy_pkg = msr & 0xFFFFFFFF; 1222 } 1223 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1224 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1225 return -14; 1226 p->energy_cores = msr & 0xFFFFFFFF; 1227 } 1228 if (do_rapl & RAPL_DRAM) { 1229 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1230 return -15; 1231 p->energy_dram = msr & 0xFFFFFFFF; 1232 } 1233 if (do_rapl & RAPL_GFX) { 1234 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1235 return -16; 1236 p->energy_gfx = msr & 0xFFFFFFFF; 1237 } 1238 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1239 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1240 return -16; 1241 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1242 } 1243 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1244 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1245 return -16; 1246 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1247 } 1248 if (do_ptm) { 1249 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1250 return -17; 1251 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1252 } 1253 1254 if (do_gfx_rc6_ms) 1255 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1256 1257 if (do_gfx_mhz) 1258 p->gfx_mhz = gfx_cur_mhz; 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1265 * If you change the values, note they are used both in comparisons 1266 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1267 */ 1268 1269 #define PCLUKN 0 /* Unknown */ 1270 #define PCLRSV 1 /* Reserved */ 1271 #define PCL__0 2 /* PC0 */ 1272 #define PCL__1 3 /* PC1 */ 1273 #define PCL__2 4 /* PC2 */ 1274 #define PCL__3 5 /* PC3 */ 1275 #define PCL__4 6 /* PC4 */ 1276 #define PCL__6 7 /* PC6 */ 1277 #define PCL_6N 8 /* PC6 No Retention */ 1278 #define PCL_6R 9 /* PC6 Retention */ 1279 #define PCL__7 10 /* PC7 */ 1280 #define PCL_7S 11 /* PC7 Shrink */ 1281 #define PCL__8 12 /* PC8 */ 1282 #define PCL__9 13 /* PC9 */ 1283 #define PCLUNL 14 /* Unlimited */ 1284 1285 int pkg_cstate_limit = PCLUKN; 1286 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1287 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1288 1289 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1290 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1291 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1292 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1293 int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1294 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1295 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1296 1297 1298 static void 1299 calculate_tsc_tweak() 1300 { 1301 tsc_tweak = base_hz / tsc_hz; 1302 } 1303 1304 static void 1305 dump_nhm_platform_info(void) 1306 { 1307 unsigned long long msr; 1308 unsigned int ratio; 1309 1310 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1311 1312 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1313 1314 ratio = (msr >> 40) & 0xFF; 1315 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", 1316 ratio, bclk, ratio * bclk); 1317 1318 ratio = (msr >> 8) & 0xFF; 1319 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", 1320 ratio, bclk, ratio * bclk); 1321 1322 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1323 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1324 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1325 1326 return; 1327 } 1328 1329 static void 1330 dump_hsw_turbo_ratio_limits(void) 1331 { 1332 unsigned long long msr; 1333 unsigned int ratio; 1334 1335 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1336 1337 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1338 1339 ratio = (msr >> 8) & 0xFF; 1340 if (ratio) 1341 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", 1342 ratio, bclk, ratio * bclk); 1343 1344 ratio = (msr >> 0) & 0xFF; 1345 if (ratio) 1346 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", 1347 ratio, bclk, ratio * bclk); 1348 return; 1349 } 1350 1351 static void 1352 dump_ivt_turbo_ratio_limits(void) 1353 { 1354 unsigned long long msr; 1355 unsigned int ratio; 1356 1357 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1358 1359 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1360 1361 ratio = (msr >> 56) & 0xFF; 1362 if (ratio) 1363 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", 1364 ratio, bclk, ratio * bclk); 1365 1366 ratio = (msr >> 48) & 0xFF; 1367 if (ratio) 1368 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", 1369 ratio, bclk, ratio * bclk); 1370 1371 ratio = (msr >> 40) & 0xFF; 1372 if (ratio) 1373 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", 1374 ratio, bclk, ratio * bclk); 1375 1376 ratio = (msr >> 32) & 0xFF; 1377 if (ratio) 1378 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", 1379 ratio, bclk, ratio * bclk); 1380 1381 ratio = (msr >> 24) & 0xFF; 1382 if (ratio) 1383 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", 1384 ratio, bclk, ratio * bclk); 1385 1386 ratio = (msr >> 16) & 0xFF; 1387 if (ratio) 1388 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", 1389 ratio, bclk, ratio * bclk); 1390 1391 ratio = (msr >> 8) & 0xFF; 1392 if (ratio) 1393 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", 1394 ratio, bclk, ratio * bclk); 1395 1396 ratio = (msr >> 0) & 0xFF; 1397 if (ratio) 1398 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", 1399 ratio, bclk, ratio * bclk); 1400 return; 1401 } 1402 1403 static void 1404 dump_nhm_turbo_ratio_limits(void) 1405 { 1406 unsigned long long msr; 1407 unsigned int ratio; 1408 1409 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1410 1411 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1412 1413 ratio = (msr >> 56) & 0xFF; 1414 if (ratio) 1415 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", 1416 ratio, bclk, ratio * bclk); 1417 1418 ratio = (msr >> 48) & 0xFF; 1419 if (ratio) 1420 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", 1421 ratio, bclk, ratio * bclk); 1422 1423 ratio = (msr >> 40) & 0xFF; 1424 if (ratio) 1425 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", 1426 ratio, bclk, ratio * bclk); 1427 1428 ratio = (msr >> 32) & 0xFF; 1429 if (ratio) 1430 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", 1431 ratio, bclk, ratio * bclk); 1432 1433 ratio = (msr >> 24) & 0xFF; 1434 if (ratio) 1435 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", 1436 ratio, bclk, ratio * bclk); 1437 1438 ratio = (msr >> 16) & 0xFF; 1439 if (ratio) 1440 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", 1441 ratio, bclk, ratio * bclk); 1442 1443 ratio = (msr >> 8) & 0xFF; 1444 if (ratio) 1445 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", 1446 ratio, bclk, ratio * bclk); 1447 1448 ratio = (msr >> 0) & 0xFF; 1449 if (ratio) 1450 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", 1451 ratio, bclk, ratio * bclk); 1452 return; 1453 } 1454 1455 static void 1456 dump_knl_turbo_ratio_limits(void) 1457 { 1458 const unsigned int buckets_no = 7; 1459 1460 unsigned long long msr; 1461 int delta_cores, delta_ratio; 1462 int i, b_nr; 1463 unsigned int cores[buckets_no]; 1464 unsigned int ratio[buckets_no]; 1465 1466 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1467 1468 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1469 base_cpu, msr); 1470 1471 /** 1472 * Turbo encoding in KNL is as follows: 1473 * [0] -- Reserved 1474 * [7:1] -- Base value of number of active cores of bucket 1. 1475 * [15:8] -- Base value of freq ratio of bucket 1. 1476 * [20:16] -- +ve delta of number of active cores of bucket 2. 1477 * i.e. active cores of bucket 2 = 1478 * active cores of bucket 1 + delta 1479 * [23:21] -- Negative delta of freq ratio of bucket 2. 1480 * i.e. freq ratio of bucket 2 = 1481 * freq ratio of bucket 1 - delta 1482 * [28:24]-- +ve delta of number of active cores of bucket 3. 1483 * [31:29]-- -ve delta of freq ratio of bucket 3. 1484 * [36:32]-- +ve delta of number of active cores of bucket 4. 1485 * [39:37]-- -ve delta of freq ratio of bucket 4. 1486 * [44:40]-- +ve delta of number of active cores of bucket 5. 1487 * [47:45]-- -ve delta of freq ratio of bucket 5. 1488 * [52:48]-- +ve delta of number of active cores of bucket 6. 1489 * [55:53]-- -ve delta of freq ratio of bucket 6. 1490 * [60:56]-- +ve delta of number of active cores of bucket 7. 1491 * [63:61]-- -ve delta of freq ratio of bucket 7. 1492 */ 1493 1494 b_nr = 0; 1495 cores[b_nr] = (msr & 0xFF) >> 1; 1496 ratio[b_nr] = (msr >> 8) & 0xFF; 1497 1498 for (i = 16; i < 64; i += 8) { 1499 delta_cores = (msr >> i) & 0x1F; 1500 delta_ratio = (msr >> (i + 5)) & 0x7; 1501 1502 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1503 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1504 b_nr++; 1505 } 1506 1507 for (i = buckets_no - 1; i >= 0; i--) 1508 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1509 fprintf(outf, 1510 "%d * %.0f = %.0f MHz max turbo %d active cores\n", 1511 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1512 } 1513 1514 static void 1515 dump_nhm_cst_cfg(void) 1516 { 1517 unsigned long long msr; 1518 1519 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 1520 1521 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1522 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1523 1524 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr); 1525 1526 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1527 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1528 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1529 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1530 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1531 (msr & (1 << 15)) ? "" : "UN", 1532 (unsigned int)msr & 0xF, 1533 pkg_cstate_limit_strings[pkg_cstate_limit]); 1534 return; 1535 } 1536 1537 static void 1538 dump_config_tdp(void) 1539 { 1540 unsigned long long msr; 1541 1542 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1543 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1544 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1545 1546 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1547 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1548 if (msr) { 1549 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1550 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1551 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1552 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1553 } 1554 fprintf(outf, ")\n"); 1555 1556 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1557 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1558 if (msr) { 1559 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1560 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1561 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1562 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1563 } 1564 fprintf(outf, ")\n"); 1565 1566 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1567 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1568 if ((msr) & 0x3) 1569 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1570 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1571 fprintf(outf, ")\n"); 1572 1573 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1574 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1575 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1576 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1577 fprintf(outf, ")\n"); 1578 } 1579 1580 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1581 1582 void print_irtl(void) 1583 { 1584 unsigned long long msr; 1585 1586 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1587 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1588 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1589 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1590 1591 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1592 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1593 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1594 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1595 1596 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1597 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1598 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1599 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1600 1601 if (!do_irtl_hsw) 1602 return; 1603 1604 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1605 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1606 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1607 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1608 1609 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1610 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1611 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1612 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1613 1614 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1615 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1616 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1617 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1618 1619 } 1620 void free_fd_percpu(void) 1621 { 1622 int i; 1623 1624 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 1625 if (fd_percpu[i] != 0) 1626 close(fd_percpu[i]); 1627 } 1628 1629 free(fd_percpu); 1630 } 1631 1632 void free_all_buffers(void) 1633 { 1634 CPU_FREE(cpu_present_set); 1635 cpu_present_set = NULL; 1636 cpu_present_setsize = 0; 1637 1638 CPU_FREE(cpu_affinity_set); 1639 cpu_affinity_set = NULL; 1640 cpu_affinity_setsize = 0; 1641 1642 free(thread_even); 1643 free(core_even); 1644 free(package_even); 1645 1646 thread_even = NULL; 1647 core_even = NULL; 1648 package_even = NULL; 1649 1650 free(thread_odd); 1651 free(core_odd); 1652 free(package_odd); 1653 1654 thread_odd = NULL; 1655 core_odd = NULL; 1656 package_odd = NULL; 1657 1658 free(output_buffer); 1659 output_buffer = NULL; 1660 outp = NULL; 1661 1662 free_fd_percpu(); 1663 1664 free(irq_column_2_cpu); 1665 free(irqs_per_cpu); 1666 } 1667 1668 /* 1669 * Open a file, and exit on failure 1670 */ 1671 FILE *fopen_or_die(const char *path, const char *mode) 1672 { 1673 FILE *filep = fopen(path, mode); 1674 if (!filep) 1675 err(1, "%s: open failed", path); 1676 return filep; 1677 } 1678 1679 /* 1680 * Parse a file containing a single int. 1681 */ 1682 int parse_int_file(const char *fmt, ...) 1683 { 1684 va_list args; 1685 char path[PATH_MAX]; 1686 FILE *filep; 1687 int value; 1688 1689 va_start(args, fmt); 1690 vsnprintf(path, sizeof(path), fmt, args); 1691 va_end(args); 1692 filep = fopen_or_die(path, "r"); 1693 if (fscanf(filep, "%d", &value) != 1) 1694 err(1, "%s: failed to parse number from file", path); 1695 fclose(filep); 1696 return value; 1697 } 1698 1699 /* 1700 * get_cpu_position_in_core(cpu) 1701 * return the position of the CPU among its HT siblings in the core 1702 * return -1 if the sibling is not in list 1703 */ 1704 int get_cpu_position_in_core(int cpu) 1705 { 1706 char path[64]; 1707 FILE *filep; 1708 int this_cpu; 1709 char character; 1710 int i; 1711 1712 sprintf(path, 1713 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 1714 cpu); 1715 filep = fopen(path, "r"); 1716 if (filep == NULL) { 1717 perror(path); 1718 exit(1); 1719 } 1720 1721 for (i = 0; i < topo.num_threads_per_core; i++) { 1722 fscanf(filep, "%d", &this_cpu); 1723 if (this_cpu == cpu) { 1724 fclose(filep); 1725 return i; 1726 } 1727 1728 /* Account for no separator after last thread*/ 1729 if (i != (topo.num_threads_per_core - 1)) 1730 fscanf(filep, "%c", &character); 1731 } 1732 1733 fclose(filep); 1734 return -1; 1735 } 1736 1737 /* 1738 * cpu_is_first_core_in_package(cpu) 1739 * return 1 if given CPU is 1st core in package 1740 */ 1741 int cpu_is_first_core_in_package(int cpu) 1742 { 1743 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 1744 } 1745 1746 int get_physical_package_id(int cpu) 1747 { 1748 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 1749 } 1750 1751 int get_core_id(int cpu) 1752 { 1753 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 1754 } 1755 1756 int get_num_ht_siblings(int cpu) 1757 { 1758 char path[80]; 1759 FILE *filep; 1760 int sib1; 1761 int matches = 0; 1762 char character; 1763 char str[100]; 1764 char *ch; 1765 1766 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 1767 filep = fopen_or_die(path, "r"); 1768 1769 /* 1770 * file format: 1771 * A ',' separated or '-' separated set of numbers 1772 * (eg 1-2 or 1,3,4,5) 1773 */ 1774 fscanf(filep, "%d%c\n", &sib1, &character); 1775 fseek(filep, 0, SEEK_SET); 1776 fgets(str, 100, filep); 1777 ch = strchr(str, character); 1778 while (ch != NULL) { 1779 matches++; 1780 ch = strchr(ch+1, character); 1781 } 1782 1783 fclose(filep); 1784 return matches+1; 1785 } 1786 1787 /* 1788 * run func(thread, core, package) in topology order 1789 * skip non-present cpus 1790 */ 1791 1792 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 1793 struct pkg_data *, struct thread_data *, struct core_data *, 1794 struct pkg_data *), struct thread_data *thread_base, 1795 struct core_data *core_base, struct pkg_data *pkg_base, 1796 struct thread_data *thread_base2, struct core_data *core_base2, 1797 struct pkg_data *pkg_base2) 1798 { 1799 int retval, pkg_no, core_no, thread_no; 1800 1801 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 1802 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 1803 for (thread_no = 0; thread_no < 1804 topo.num_threads_per_core; ++thread_no) { 1805 struct thread_data *t, *t2; 1806 struct core_data *c, *c2; 1807 struct pkg_data *p, *p2; 1808 1809 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 1810 1811 if (cpu_is_not_present(t->cpu_id)) 1812 continue; 1813 1814 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 1815 1816 c = GET_CORE(core_base, core_no, pkg_no); 1817 c2 = GET_CORE(core_base2, core_no, pkg_no); 1818 1819 p = GET_PKG(pkg_base, pkg_no); 1820 p2 = GET_PKG(pkg_base2, pkg_no); 1821 1822 retval = func(t, c, p, t2, c2, p2); 1823 if (retval) 1824 return retval; 1825 } 1826 } 1827 } 1828 return 0; 1829 } 1830 1831 /* 1832 * run func(cpu) on every cpu in /proc/stat 1833 * return max_cpu number 1834 */ 1835 int for_all_proc_cpus(int (func)(int)) 1836 { 1837 FILE *fp; 1838 int cpu_num; 1839 int retval; 1840 1841 fp = fopen_or_die(proc_stat, "r"); 1842 1843 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 1844 if (retval != 0) 1845 err(1, "%s: failed to parse format", proc_stat); 1846 1847 while (1) { 1848 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 1849 if (retval != 1) 1850 break; 1851 1852 retval = func(cpu_num); 1853 if (retval) { 1854 fclose(fp); 1855 return(retval); 1856 } 1857 } 1858 fclose(fp); 1859 return 0; 1860 } 1861 1862 void re_initialize(void) 1863 { 1864 free_all_buffers(); 1865 setup_all_buffers(); 1866 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 1867 } 1868 1869 1870 /* 1871 * count_cpus() 1872 * remember the last one seen, it will be the max 1873 */ 1874 int count_cpus(int cpu) 1875 { 1876 if (topo.max_cpu_num < cpu) 1877 topo.max_cpu_num = cpu; 1878 1879 topo.num_cpus += 1; 1880 return 0; 1881 } 1882 int mark_cpu_present(int cpu) 1883 { 1884 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 1885 return 0; 1886 } 1887 1888 /* 1889 * snapshot_proc_interrupts() 1890 * 1891 * read and record summary of /proc/interrupts 1892 * 1893 * return 1 if config change requires a restart, else return 0 1894 */ 1895 int snapshot_proc_interrupts(void) 1896 { 1897 static FILE *fp; 1898 int column, retval; 1899 1900 if (fp == NULL) 1901 fp = fopen_or_die("/proc/interrupts", "r"); 1902 else 1903 rewind(fp); 1904 1905 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 1906 for (column = 0; column < topo.num_cpus; ++column) { 1907 int cpu_number; 1908 1909 retval = fscanf(fp, " CPU%d", &cpu_number); 1910 if (retval != 1) 1911 break; 1912 1913 if (cpu_number > topo.max_cpu_num) { 1914 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 1915 return 1; 1916 } 1917 1918 irq_column_2_cpu[column] = cpu_number; 1919 irqs_per_cpu[cpu_number] = 0; 1920 } 1921 1922 /* read /proc/interrupt count lines and sum up irqs per cpu */ 1923 while (1) { 1924 int column; 1925 char buf[64]; 1926 1927 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 1928 if (retval != 1) 1929 break; 1930 1931 /* read the count per cpu */ 1932 for (column = 0; column < topo.num_cpus; ++column) { 1933 1934 int cpu_number, irq_count; 1935 1936 retval = fscanf(fp, " %d", &irq_count); 1937 if (retval != 1) 1938 break; 1939 1940 cpu_number = irq_column_2_cpu[column]; 1941 irqs_per_cpu[cpu_number] += irq_count; 1942 1943 } 1944 1945 while (getc(fp) != '\n') 1946 ; /* flush interrupt description */ 1947 1948 } 1949 return 0; 1950 } 1951 /* 1952 * snapshot_gfx_rc6_ms() 1953 * 1954 * record snapshot of 1955 * /sys/class/drm/card0/power/rc6_residency_ms 1956 * 1957 * return 1 if config change requires a restart, else return 0 1958 */ 1959 int snapshot_gfx_rc6_ms(void) 1960 { 1961 FILE *fp; 1962 int retval; 1963 1964 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 1965 1966 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 1967 if (retval != 1) 1968 err(1, "GFX rc6"); 1969 1970 fclose(fp); 1971 1972 return 0; 1973 } 1974 /* 1975 * snapshot_gfx_mhz() 1976 * 1977 * record snapshot of 1978 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 1979 * 1980 * return 1 if config change requires a restart, else return 0 1981 */ 1982 int snapshot_gfx_mhz(void) 1983 { 1984 static FILE *fp; 1985 int retval; 1986 1987 if (fp == NULL) 1988 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 1989 else 1990 rewind(fp); 1991 1992 retval = fscanf(fp, "%d", &gfx_cur_mhz); 1993 if (retval != 1) 1994 err(1, "GFX MHz"); 1995 1996 return 0; 1997 } 1998 1999 /* 2000 * snapshot /proc and /sys files 2001 * 2002 * return 1 if configuration restart needed, else return 0 2003 */ 2004 int snapshot_proc_sysfs_files(void) 2005 { 2006 if (snapshot_proc_interrupts()) 2007 return 1; 2008 2009 if (do_gfx_rc6_ms) 2010 snapshot_gfx_rc6_ms(); 2011 2012 if (do_gfx_mhz) 2013 snapshot_gfx_mhz(); 2014 2015 return 0; 2016 } 2017 2018 void turbostat_loop() 2019 { 2020 int retval; 2021 int restarted = 0; 2022 2023 restart: 2024 restarted++; 2025 2026 snapshot_proc_sysfs_files(); 2027 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2028 if (retval < -1) { 2029 exit(retval); 2030 } else if (retval == -1) { 2031 if (restarted > 1) { 2032 exit(retval); 2033 } 2034 re_initialize(); 2035 goto restart; 2036 } 2037 restarted = 0; 2038 gettimeofday(&tv_even, (struct timezone *)NULL); 2039 2040 while (1) { 2041 if (for_all_proc_cpus(cpu_is_not_present)) { 2042 re_initialize(); 2043 goto restart; 2044 } 2045 nanosleep(&interval_ts, NULL); 2046 if (snapshot_proc_sysfs_files()) 2047 goto restart; 2048 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2049 if (retval < -1) { 2050 exit(retval); 2051 } else if (retval == -1) { 2052 re_initialize(); 2053 goto restart; 2054 } 2055 gettimeofday(&tv_odd, (struct timezone *)NULL); 2056 timersub(&tv_odd, &tv_even, &tv_delta); 2057 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2058 re_initialize(); 2059 goto restart; 2060 } 2061 compute_average(EVEN_COUNTERS); 2062 format_all_counters(EVEN_COUNTERS); 2063 flush_output_stdout(); 2064 nanosleep(&interval_ts, NULL); 2065 if (snapshot_proc_sysfs_files()) 2066 goto restart; 2067 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2068 if (retval < -1) { 2069 exit(retval); 2070 } else if (retval == -1) { 2071 re_initialize(); 2072 goto restart; 2073 } 2074 gettimeofday(&tv_even, (struct timezone *)NULL); 2075 timersub(&tv_even, &tv_odd, &tv_delta); 2076 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 2077 re_initialize(); 2078 goto restart; 2079 } 2080 compute_average(ODD_COUNTERS); 2081 format_all_counters(ODD_COUNTERS); 2082 flush_output_stdout(); 2083 } 2084 } 2085 2086 void check_dev_msr() 2087 { 2088 struct stat sb; 2089 char pathname[32]; 2090 2091 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2092 if (stat(pathname, &sb)) 2093 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2094 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2095 } 2096 2097 void check_permissions() 2098 { 2099 struct __user_cap_header_struct cap_header_data; 2100 cap_user_header_t cap_header = &cap_header_data; 2101 struct __user_cap_data_struct cap_data_data; 2102 cap_user_data_t cap_data = &cap_data_data; 2103 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2104 int do_exit = 0; 2105 char pathname[32]; 2106 2107 /* check for CAP_SYS_RAWIO */ 2108 cap_header->pid = getpid(); 2109 cap_header->version = _LINUX_CAPABILITY_VERSION; 2110 if (capget(cap_header, cap_data) < 0) 2111 err(-6, "capget(2) failed"); 2112 2113 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2114 do_exit++; 2115 warnx("capget(CAP_SYS_RAWIO) failed," 2116 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2117 } 2118 2119 /* test file permissions */ 2120 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2121 if (euidaccess(pathname, R_OK)) { 2122 do_exit++; 2123 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2124 } 2125 2126 /* if all else fails, thell them to be root */ 2127 if (do_exit) 2128 if (getuid() != 0) 2129 warnx("... or simply run as root"); 2130 2131 if (do_exit) 2132 exit(-6); 2133 } 2134 2135 /* 2136 * NHM adds support for additional MSRs: 2137 * 2138 * MSR_SMI_COUNT 0x00000034 2139 * 2140 * MSR_PLATFORM_INFO 0x000000ce 2141 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 2142 * 2143 * MSR_PKG_C3_RESIDENCY 0x000003f8 2144 * MSR_PKG_C6_RESIDENCY 0x000003f9 2145 * MSR_CORE_C3_RESIDENCY 0x000003fc 2146 * MSR_CORE_C6_RESIDENCY 0x000003fd 2147 * 2148 * Side effect: 2149 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL 2150 */ 2151 int probe_nhm_msrs(unsigned int family, unsigned int model) 2152 { 2153 unsigned long long msr; 2154 unsigned int base_ratio; 2155 int *pkg_cstate_limits; 2156 2157 if (!genuine_intel) 2158 return 0; 2159 2160 if (family != 6) 2161 return 0; 2162 2163 bclk = discover_bclk(family, model); 2164 2165 switch (model) { 2166 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2167 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2168 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2169 case 0x25: /* Westmere Client - Clarkdale, Arrandale */ 2170 case 0x2C: /* Westmere EP - Gulftown */ 2171 case 0x2E: /* Nehalem-EX Xeon - Beckton */ 2172 case 0x2F: /* Westmere-EX Xeon - Eagleton */ 2173 pkg_cstate_limits = nhm_pkg_cstate_limits; 2174 break; 2175 case 0x2A: /* SNB */ 2176 case 0x2D: /* SNB Xeon */ 2177 case 0x3A: /* IVB */ 2178 case 0x3E: /* IVB Xeon */ 2179 pkg_cstate_limits = snb_pkg_cstate_limits; 2180 break; 2181 case 0x3C: /* HSW */ 2182 case 0x3F: /* HSX */ 2183 case 0x45: /* HSW */ 2184 case 0x46: /* HSW */ 2185 case 0x3D: /* BDW */ 2186 case 0x47: /* BDW */ 2187 case 0x4F: /* BDX */ 2188 case 0x56: /* BDX-DE */ 2189 case 0x4E: /* SKL */ 2190 case 0x5E: /* SKL */ 2191 case 0x8E: /* KBL */ 2192 case 0x9E: /* KBL */ 2193 case 0x55: /* SKX */ 2194 pkg_cstate_limits = hsw_pkg_cstate_limits; 2195 break; 2196 case 0x37: /* BYT */ 2197 case 0x4D: /* AVN */ 2198 pkg_cstate_limits = slv_pkg_cstate_limits; 2199 break; 2200 case 0x4C: /* AMT */ 2201 pkg_cstate_limits = amt_pkg_cstate_limits; 2202 break; 2203 case 0x57: /* PHI */ 2204 pkg_cstate_limits = phi_pkg_cstate_limits; 2205 break; 2206 case 0x5C: /* BXT */ 2207 case 0x5F: /* DNV */ 2208 pkg_cstate_limits = bxt_pkg_cstate_limits; 2209 break; 2210 default: 2211 return 0; 2212 } 2213 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 2214 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2215 2216 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2217 base_ratio = (msr >> 8) & 0xFF; 2218 2219 base_hz = base_ratio * bclk * 1000000; 2220 has_base_hz = 1; 2221 return 1; 2222 } 2223 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2224 { 2225 switch (model) { 2226 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2227 case 0x2E: /* Nehalem-EX Xeon - Beckton */ 2228 case 0x2F: /* Westmere-EX Xeon - Eagleton */ 2229 case 0x57: /* PHI - Knights Landing (different MSR definition) */ 2230 return 0; 2231 default: 2232 return 1; 2233 } 2234 } 2235 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2236 { 2237 if (!genuine_intel) 2238 return 0; 2239 2240 if (family != 6) 2241 return 0; 2242 2243 switch (model) { 2244 case 0x3E: /* IVB Xeon */ 2245 case 0x3F: /* HSW Xeon */ 2246 return 1; 2247 default: 2248 return 0; 2249 } 2250 } 2251 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2252 { 2253 if (!genuine_intel) 2254 return 0; 2255 2256 if (family != 6) 2257 return 0; 2258 2259 switch (model) { 2260 case 0x3F: /* HSW Xeon */ 2261 return 1; 2262 default: 2263 return 0; 2264 } 2265 } 2266 2267 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2268 { 2269 if (!genuine_intel) 2270 return 0; 2271 2272 if (family != 6) 2273 return 0; 2274 2275 switch (model) { 2276 case 0x57: /* Knights Landing */ 2277 return 1; 2278 default: 2279 return 0; 2280 } 2281 } 2282 int has_config_tdp(unsigned int family, unsigned int model) 2283 { 2284 if (!genuine_intel) 2285 return 0; 2286 2287 if (family != 6) 2288 return 0; 2289 2290 switch (model) { 2291 case 0x3A: /* IVB */ 2292 case 0x3C: /* HSW */ 2293 case 0x3F: /* HSX */ 2294 case 0x45: /* HSW */ 2295 case 0x46: /* HSW */ 2296 case 0x3D: /* BDW */ 2297 case 0x47: /* BDW */ 2298 case 0x4F: /* BDX */ 2299 case 0x56: /* BDX-DE */ 2300 case 0x4E: /* SKL */ 2301 case 0x5E: /* SKL */ 2302 case 0x8E: /* KBL */ 2303 case 0x9E: /* KBL */ 2304 case 0x55: /* SKX */ 2305 2306 case 0x57: /* Knights Landing */ 2307 return 1; 2308 default: 2309 return 0; 2310 } 2311 } 2312 2313 static void 2314 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 2315 { 2316 if (!do_nhm_platform_info) 2317 return; 2318 2319 dump_nhm_platform_info(); 2320 2321 if (has_hsw_turbo_ratio_limit(family, model)) 2322 dump_hsw_turbo_ratio_limits(); 2323 2324 if (has_ivt_turbo_ratio_limit(family, model)) 2325 dump_ivt_turbo_ratio_limits(); 2326 2327 if (has_nhm_turbo_ratio_limit(family, model)) 2328 dump_nhm_turbo_ratio_limits(); 2329 2330 if (has_knl_turbo_ratio_limit(family, model)) 2331 dump_knl_turbo_ratio_limits(); 2332 2333 if (has_config_tdp(family, model)) 2334 dump_config_tdp(); 2335 2336 dump_nhm_cst_cfg(); 2337 } 2338 2339 2340 /* 2341 * print_epb() 2342 * Decode the ENERGY_PERF_BIAS MSR 2343 */ 2344 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2345 { 2346 unsigned long long msr; 2347 char *epb_string; 2348 int cpu; 2349 2350 if (!has_epb) 2351 return 0; 2352 2353 cpu = t->cpu_id; 2354 2355 /* EPB is per-package */ 2356 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2357 return 0; 2358 2359 if (cpu_migrate(cpu)) { 2360 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2361 return -1; 2362 } 2363 2364 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2365 return 0; 2366 2367 switch (msr & 0xF) { 2368 case ENERGY_PERF_BIAS_PERFORMANCE: 2369 epb_string = "performance"; 2370 break; 2371 case ENERGY_PERF_BIAS_NORMAL: 2372 epb_string = "balanced"; 2373 break; 2374 case ENERGY_PERF_BIAS_POWERSAVE: 2375 epb_string = "powersave"; 2376 break; 2377 default: 2378 epb_string = "custom"; 2379 break; 2380 } 2381 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2382 2383 return 0; 2384 } 2385 /* 2386 * print_hwp() 2387 * Decode the MSR_HWP_CAPABILITIES 2388 */ 2389 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2390 { 2391 unsigned long long msr; 2392 int cpu; 2393 2394 if (!has_hwp) 2395 return 0; 2396 2397 cpu = t->cpu_id; 2398 2399 /* MSR_HWP_CAPABILITIES is per-package */ 2400 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2401 return 0; 2402 2403 if (cpu_migrate(cpu)) { 2404 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2405 return -1; 2406 } 2407 2408 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2409 return 0; 2410 2411 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2412 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2413 2414 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2415 if ((msr & (1 << 0)) == 0) 2416 return 0; 2417 2418 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2419 return 0; 2420 2421 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2422 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2423 cpu, msr, 2424 (unsigned int)HWP_HIGHEST_PERF(msr), 2425 (unsigned int)HWP_GUARANTEED_PERF(msr), 2426 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2427 (unsigned int)HWP_LOWEST_PERF(msr)); 2428 2429 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2430 return 0; 2431 2432 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2433 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2434 cpu, msr, 2435 (unsigned int)(((msr) >> 0) & 0xff), 2436 (unsigned int)(((msr) >> 8) & 0xff), 2437 (unsigned int)(((msr) >> 16) & 0xff), 2438 (unsigned int)(((msr) >> 24) & 0xff), 2439 (unsigned int)(((msr) >> 32) & 0xff3), 2440 (unsigned int)(((msr) >> 42) & 0x1)); 2441 2442 if (has_hwp_pkg) { 2443 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2444 return 0; 2445 2446 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2447 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2448 cpu, msr, 2449 (unsigned int)(((msr) >> 0) & 0xff), 2450 (unsigned int)(((msr) >> 8) & 0xff), 2451 (unsigned int)(((msr) >> 16) & 0xff), 2452 (unsigned int)(((msr) >> 24) & 0xff), 2453 (unsigned int)(((msr) >> 32) & 0xff3)); 2454 } 2455 if (has_hwp_notify) { 2456 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2457 return 0; 2458 2459 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2460 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2461 cpu, msr, 2462 ((msr) & 0x1) ? "EN" : "Dis", 2463 ((msr) & 0x2) ? "EN" : "Dis"); 2464 } 2465 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2466 return 0; 2467 2468 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2469 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2470 cpu, msr, 2471 ((msr) & 0x1) ? "" : "No-", 2472 ((msr) & 0x2) ? "" : "No-"); 2473 2474 return 0; 2475 } 2476 2477 /* 2478 * print_perf_limit() 2479 */ 2480 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2481 { 2482 unsigned long long msr; 2483 int cpu; 2484 2485 cpu = t->cpu_id; 2486 2487 /* per-package */ 2488 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2489 return 0; 2490 2491 if (cpu_migrate(cpu)) { 2492 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2493 return -1; 2494 } 2495 2496 if (do_core_perf_limit_reasons) { 2497 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2498 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2499 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2500 (msr & 1 << 15) ? "bit15, " : "", 2501 (msr & 1 << 14) ? "bit14, " : "", 2502 (msr & 1 << 13) ? "Transitions, " : "", 2503 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2504 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2505 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2506 (msr & 1 << 9) ? "CorePwr, " : "", 2507 (msr & 1 << 8) ? "Amps, " : "", 2508 (msr & 1 << 6) ? "VR-Therm, " : "", 2509 (msr & 1 << 5) ? "Auto-HWP, " : "", 2510 (msr & 1 << 4) ? "Graphics, " : "", 2511 (msr & 1 << 2) ? "bit2, " : "", 2512 (msr & 1 << 1) ? "ThermStatus, " : "", 2513 (msr & 1 << 0) ? "PROCHOT, " : ""); 2514 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2515 (msr & 1 << 31) ? "bit31, " : "", 2516 (msr & 1 << 30) ? "bit30, " : "", 2517 (msr & 1 << 29) ? "Transitions, " : "", 2518 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2519 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2520 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2521 (msr & 1 << 25) ? "CorePwr, " : "", 2522 (msr & 1 << 24) ? "Amps, " : "", 2523 (msr & 1 << 22) ? "VR-Therm, " : "", 2524 (msr & 1 << 21) ? "Auto-HWP, " : "", 2525 (msr & 1 << 20) ? "Graphics, " : "", 2526 (msr & 1 << 18) ? "bit18, " : "", 2527 (msr & 1 << 17) ? "ThermStatus, " : "", 2528 (msr & 1 << 16) ? "PROCHOT, " : ""); 2529 2530 } 2531 if (do_gfx_perf_limit_reasons) { 2532 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2533 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2534 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2535 (msr & 1 << 0) ? "PROCHOT, " : "", 2536 (msr & 1 << 1) ? "ThermStatus, " : "", 2537 (msr & 1 << 4) ? "Graphics, " : "", 2538 (msr & 1 << 6) ? "VR-Therm, " : "", 2539 (msr & 1 << 8) ? "Amps, " : "", 2540 (msr & 1 << 9) ? "GFXPwr, " : "", 2541 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2542 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2543 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2544 (msr & 1 << 16) ? "PROCHOT, " : "", 2545 (msr & 1 << 17) ? "ThermStatus, " : "", 2546 (msr & 1 << 20) ? "Graphics, " : "", 2547 (msr & 1 << 22) ? "VR-Therm, " : "", 2548 (msr & 1 << 24) ? "Amps, " : "", 2549 (msr & 1 << 25) ? "GFXPwr, " : "", 2550 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2551 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2552 } 2553 if (do_ring_perf_limit_reasons) { 2554 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2555 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2556 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2557 (msr & 1 << 0) ? "PROCHOT, " : "", 2558 (msr & 1 << 1) ? "ThermStatus, " : "", 2559 (msr & 1 << 6) ? "VR-Therm, " : "", 2560 (msr & 1 << 8) ? "Amps, " : "", 2561 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2562 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2563 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2564 (msr & 1 << 16) ? "PROCHOT, " : "", 2565 (msr & 1 << 17) ? "ThermStatus, " : "", 2566 (msr & 1 << 22) ? "VR-Therm, " : "", 2567 (msr & 1 << 24) ? "Amps, " : "", 2568 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2569 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2570 } 2571 return 0; 2572 } 2573 2574 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2575 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2576 2577 double get_tdp(unsigned int model) 2578 { 2579 unsigned long long msr; 2580 2581 if (do_rapl & RAPL_PKG_POWER_INFO) 2582 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2583 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2584 2585 switch (model) { 2586 case 0x37: 2587 case 0x4D: 2588 return 30.0; 2589 default: 2590 return 135.0; 2591 } 2592 } 2593 2594 /* 2595 * rapl_dram_energy_units_probe() 2596 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2597 */ 2598 static double 2599 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2600 { 2601 /* only called for genuine_intel, family 6 */ 2602 2603 switch (model) { 2604 case 0x3F: /* HSX */ 2605 case 0x4F: /* BDX */ 2606 case 0x56: /* BDX-DE */ 2607 case 0x57: /* KNL */ 2608 return (rapl_dram_energy_units = 15.3 / 1000000); 2609 default: 2610 return (rapl_energy_units); 2611 } 2612 } 2613 2614 2615 /* 2616 * rapl_probe() 2617 * 2618 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2619 */ 2620 void rapl_probe(unsigned int family, unsigned int model) 2621 { 2622 unsigned long long msr; 2623 unsigned int time_unit; 2624 double tdp; 2625 2626 if (!genuine_intel) 2627 return; 2628 2629 if (family != 6) 2630 return; 2631 2632 switch (model) { 2633 case 0x2A: 2634 case 0x3A: 2635 case 0x3C: /* HSW */ 2636 case 0x45: /* HSW */ 2637 case 0x46: /* HSW */ 2638 case 0x3D: /* BDW */ 2639 case 0x47: /* BDW */ 2640 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 2641 break; 2642 case 0x5C: /* BXT */ 2643 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 2644 break; 2645 case 0x4E: /* SKL */ 2646 case 0x5E: /* SKL */ 2647 case 0x8E: /* KBL */ 2648 case 0x9E: /* KBL */ 2649 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2650 break; 2651 case 0x3F: /* HSX */ 2652 case 0x4F: /* BDX */ 2653 case 0x56: /* BDX-DE */ 2654 case 0x55: /* SKX */ 2655 case 0x57: /* KNL */ 2656 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2657 break; 2658 case 0x2D: 2659 case 0x3E: 2660 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 2661 break; 2662 case 0x37: /* BYT */ 2663 case 0x4D: /* AVN */ 2664 do_rapl = RAPL_PKG | RAPL_CORES; 2665 break; 2666 case 0x5f: /* DNV */ 2667 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 2668 break; 2669 default: 2670 return; 2671 } 2672 2673 /* units on package 0, verify later other packages match */ 2674 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 2675 return; 2676 2677 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 2678 if (model == 0x37) 2679 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 2680 else 2681 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 2682 2683 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 2684 2685 time_unit = msr >> 16 & 0xF; 2686 if (time_unit == 0) 2687 time_unit = 0xA; 2688 2689 rapl_time_units = 1.0 / (1 << (time_unit)); 2690 2691 tdp = get_tdp(model); 2692 2693 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 2694 if (debug) 2695 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 2696 2697 return; 2698 } 2699 2700 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 2701 { 2702 if (!genuine_intel) 2703 return; 2704 2705 if (family != 6) 2706 return; 2707 2708 switch (model) { 2709 case 0x3C: /* HSW */ 2710 case 0x45: /* HSW */ 2711 case 0x46: /* HSW */ 2712 do_gfx_perf_limit_reasons = 1; 2713 case 0x3F: /* HSX */ 2714 do_core_perf_limit_reasons = 1; 2715 do_ring_perf_limit_reasons = 1; 2716 default: 2717 return; 2718 } 2719 } 2720 2721 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2722 { 2723 unsigned long long msr; 2724 unsigned int dts; 2725 int cpu; 2726 2727 if (!(do_dts || do_ptm)) 2728 return 0; 2729 2730 cpu = t->cpu_id; 2731 2732 /* DTS is per-core, no need to print for each thread */ 2733 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2734 return 0; 2735 2736 if (cpu_migrate(cpu)) { 2737 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2738 return -1; 2739 } 2740 2741 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 2742 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2743 return 0; 2744 2745 dts = (msr >> 16) & 0x7F; 2746 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 2747 cpu, msr, tcc_activation_temp - dts); 2748 2749 #ifdef THERM_DEBUG 2750 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 2751 return 0; 2752 2753 dts = (msr >> 16) & 0x7F; 2754 dts2 = (msr >> 8) & 0x7F; 2755 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2756 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2757 #endif 2758 } 2759 2760 2761 if (do_dts) { 2762 unsigned int resolution; 2763 2764 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2765 return 0; 2766 2767 dts = (msr >> 16) & 0x7F; 2768 resolution = (msr >> 27) & 0xF; 2769 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 2770 cpu, msr, tcc_activation_temp - dts, resolution); 2771 2772 #ifdef THERM_DEBUG 2773 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 2774 return 0; 2775 2776 dts = (msr >> 16) & 0x7F; 2777 dts2 = (msr >> 8) & 0x7F; 2778 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2779 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2780 #endif 2781 } 2782 2783 return 0; 2784 } 2785 2786 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 2787 { 2788 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 2789 cpu, label, 2790 ((msr >> 15) & 1) ? "EN" : "DIS", 2791 ((msr >> 0) & 0x7FFF) * rapl_power_units, 2792 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 2793 (((msr >> 16) & 1) ? "EN" : "DIS")); 2794 2795 return; 2796 } 2797 2798 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2799 { 2800 unsigned long long msr; 2801 int cpu; 2802 2803 if (!do_rapl) 2804 return 0; 2805 2806 /* RAPL counters are per package, so print only for 1st thread/package */ 2807 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2808 return 0; 2809 2810 cpu = t->cpu_id; 2811 if (cpu_migrate(cpu)) { 2812 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2813 return -1; 2814 } 2815 2816 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 2817 return -1; 2818 2819 if (debug) { 2820 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 2821 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 2822 rapl_power_units, rapl_energy_units, rapl_time_units); 2823 } 2824 if (do_rapl & RAPL_PKG_POWER_INFO) { 2825 2826 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 2827 return -5; 2828 2829 2830 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 2831 cpu, msr, 2832 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2833 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2834 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2835 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 2836 2837 } 2838 if (do_rapl & RAPL_PKG) { 2839 2840 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 2841 return -9; 2842 2843 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 2844 cpu, msr, (msr >> 63) & 1 ? "": "UN"); 2845 2846 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 2847 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 2848 cpu, 2849 ((msr >> 47) & 1) ? "EN" : "DIS", 2850 ((msr >> 32) & 0x7FFF) * rapl_power_units, 2851 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 2852 ((msr >> 48) & 1) ? "EN" : "DIS"); 2853 } 2854 2855 if (do_rapl & RAPL_DRAM_POWER_INFO) { 2856 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 2857 return -6; 2858 2859 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 2860 cpu, msr, 2861 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2862 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2863 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2864 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 2865 } 2866 if (do_rapl & RAPL_DRAM) { 2867 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 2868 return -9; 2869 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 2870 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2871 2872 print_power_limit_msr(cpu, msr, "DRAM Limit"); 2873 } 2874 if (do_rapl & RAPL_CORE_POLICY) { 2875 if (debug) { 2876 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 2877 return -7; 2878 2879 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 2880 } 2881 } 2882 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 2883 if (debug) { 2884 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 2885 return -9; 2886 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 2887 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2888 print_power_limit_msr(cpu, msr, "Cores Limit"); 2889 } 2890 } 2891 if (do_rapl & RAPL_GFX) { 2892 if (debug) { 2893 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 2894 return -8; 2895 2896 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 2897 2898 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 2899 return -9; 2900 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 2901 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 2902 print_power_limit_msr(cpu, msr, "GFX Limit"); 2903 } 2904 } 2905 return 0; 2906 } 2907 2908 /* 2909 * SNB adds support for additional MSRs: 2910 * 2911 * MSR_PKG_C7_RESIDENCY 0x000003fa 2912 * MSR_CORE_C7_RESIDENCY 0x000003fe 2913 * MSR_PKG_C2_RESIDENCY 0x0000060d 2914 */ 2915 2916 int has_snb_msrs(unsigned int family, unsigned int model) 2917 { 2918 if (!genuine_intel) 2919 return 0; 2920 2921 switch (model) { 2922 case 0x2A: 2923 case 0x2D: 2924 case 0x3A: /* IVB */ 2925 case 0x3E: /* IVB Xeon */ 2926 case 0x3C: /* HSW */ 2927 case 0x3F: /* HSW */ 2928 case 0x45: /* HSW */ 2929 case 0x46: /* HSW */ 2930 case 0x3D: /* BDW */ 2931 case 0x47: /* BDW */ 2932 case 0x4F: /* BDX */ 2933 case 0x56: /* BDX-DE */ 2934 case 0x4E: /* SKL */ 2935 case 0x5E: /* SKL */ 2936 case 0x8E: /* KBL */ 2937 case 0x9E: /* KBL */ 2938 case 0x55: /* SKX */ 2939 case 0x5C: /* BXT */ 2940 return 1; 2941 } 2942 return 0; 2943 } 2944 2945 /* 2946 * HSW adds support for additional MSRs: 2947 * 2948 * MSR_PKG_C8_RESIDENCY 0x00000630 2949 * MSR_PKG_C9_RESIDENCY 0x00000631 2950 * MSR_PKG_C10_RESIDENCY 0x00000632 2951 * 2952 * MSR_PKGC8_IRTL 0x00000633 2953 * MSR_PKGC9_IRTL 0x00000634 2954 * MSR_PKGC10_IRTL 0x00000635 2955 * 2956 */ 2957 int has_hsw_msrs(unsigned int family, unsigned int model) 2958 { 2959 if (!genuine_intel) 2960 return 0; 2961 2962 switch (model) { 2963 case 0x45: /* HSW */ 2964 case 0x3D: /* BDW */ 2965 case 0x4E: /* SKL */ 2966 case 0x5E: /* SKL */ 2967 case 0x8E: /* KBL */ 2968 case 0x9E: /* KBL */ 2969 case 0x5C: /* BXT */ 2970 return 1; 2971 } 2972 return 0; 2973 } 2974 2975 /* 2976 * SKL adds support for additional MSRS: 2977 * 2978 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 2979 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 2980 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 2981 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 2982 */ 2983 int has_skl_msrs(unsigned int family, unsigned int model) 2984 { 2985 if (!genuine_intel) 2986 return 0; 2987 2988 switch (model) { 2989 case 0x4E: /* SKL */ 2990 case 0x5E: /* SKL */ 2991 case 0x8E: /* KBL */ 2992 case 0x9E: /* KBL */ 2993 return 1; 2994 } 2995 return 0; 2996 } 2997 2998 2999 3000 int is_slm(unsigned int family, unsigned int model) 3001 { 3002 if (!genuine_intel) 3003 return 0; 3004 switch (model) { 3005 case 0x37: /* BYT */ 3006 case 0x4D: /* AVN */ 3007 return 1; 3008 } 3009 return 0; 3010 } 3011 3012 int is_knl(unsigned int family, unsigned int model) 3013 { 3014 if (!genuine_intel) 3015 return 0; 3016 switch (model) { 3017 case 0x57: /* KNL */ 3018 return 1; 3019 } 3020 return 0; 3021 } 3022 3023 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3024 { 3025 if (is_knl(family, model)) 3026 return 1024; 3027 return 1; 3028 } 3029 3030 #define SLM_BCLK_FREQS 5 3031 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3032 3033 double slm_bclk(void) 3034 { 3035 unsigned long long msr = 3; 3036 unsigned int i; 3037 double freq; 3038 3039 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3040 fprintf(outf, "SLM BCLK: unknown\n"); 3041 3042 i = msr & 0xf; 3043 if (i >= SLM_BCLK_FREQS) { 3044 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3045 i = 3; 3046 } 3047 freq = slm_freq_table[i]; 3048 3049 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3050 3051 return freq; 3052 } 3053 3054 double discover_bclk(unsigned int family, unsigned int model) 3055 { 3056 if (has_snb_msrs(family, model) || is_knl(family, model)) 3057 return 100.00; 3058 else if (is_slm(family, model)) 3059 return slm_bclk(); 3060 else 3061 return 133.33; 3062 } 3063 3064 /* 3065 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3066 * the Thermal Control Circuit (TCC) activates. 3067 * This is usually equal to tjMax. 3068 * 3069 * Older processors do not have this MSR, so there we guess, 3070 * but also allow cmdline over-ride with -T. 3071 * 3072 * Several MSR temperature values are in units of degrees-C 3073 * below this value, including the Digital Thermal Sensor (DTS), 3074 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3075 */ 3076 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3077 { 3078 unsigned long long msr; 3079 unsigned int target_c_local; 3080 int cpu; 3081 3082 /* tcc_activation_temp is used only for dts or ptm */ 3083 if (!(do_dts || do_ptm)) 3084 return 0; 3085 3086 /* this is a per-package concept */ 3087 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3088 return 0; 3089 3090 cpu = t->cpu_id; 3091 if (cpu_migrate(cpu)) { 3092 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3093 return -1; 3094 } 3095 3096 if (tcc_activation_temp_override != 0) { 3097 tcc_activation_temp = tcc_activation_temp_override; 3098 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3099 cpu, tcc_activation_temp); 3100 return 0; 3101 } 3102 3103 /* Temperature Target MSR is Nehalem and newer only */ 3104 if (!do_nhm_platform_info) 3105 goto guess; 3106 3107 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3108 goto guess; 3109 3110 target_c_local = (msr >> 16) & 0xFF; 3111 3112 if (debug) 3113 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3114 cpu, msr, target_c_local); 3115 3116 if (!target_c_local) 3117 goto guess; 3118 3119 tcc_activation_temp = target_c_local; 3120 3121 return 0; 3122 3123 guess: 3124 tcc_activation_temp = TJMAX_DEFAULT; 3125 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3126 cpu, tcc_activation_temp); 3127 3128 return 0; 3129 } 3130 3131 void decode_feature_control_msr(void) 3132 { 3133 unsigned long long msr; 3134 3135 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3136 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3137 base_cpu, msr, 3138 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3139 msr & (1 << 18) ? "SGX" : ""); 3140 } 3141 3142 void decode_misc_enable_msr(void) 3143 { 3144 unsigned long long msr; 3145 3146 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3147 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", 3148 base_cpu, msr, 3149 msr & (1 << 3) ? "TCC" : "", 3150 msr & (1 << 16) ? "EIST" : "", 3151 msr & (1 << 18) ? "MONITOR" : ""); 3152 } 3153 3154 /* 3155 * Decode MSR_MISC_PWR_MGMT 3156 * 3157 * Decode the bits according to the Nehalem documentation 3158 * bit[0] seems to continue to have same meaning going forward 3159 * bit[1] less so... 3160 */ 3161 void decode_misc_pwr_mgmt_msr(void) 3162 { 3163 unsigned long long msr; 3164 3165 if (!do_nhm_platform_info) 3166 return; 3167 3168 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3169 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n", 3170 base_cpu, msr, 3171 msr & (1 << 0) ? "DIS" : "EN", 3172 msr & (1 << 1) ? "EN" : "DIS"); 3173 } 3174 3175 void process_cpuid() 3176 { 3177 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3178 unsigned int fms, family, model, stepping; 3179 3180 eax = ebx = ecx = edx = 0; 3181 3182 __cpuid(0, max_level, ebx, ecx, edx); 3183 3184 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3185 genuine_intel = 1; 3186 3187 if (debug) 3188 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3189 (char *)&ebx, (char *)&edx, (char *)&ecx); 3190 3191 __cpuid(1, fms, ebx, ecx, edx); 3192 family = (fms >> 8) & 0xf; 3193 model = (fms >> 4) & 0xf; 3194 stepping = fms & 0xf; 3195 if (family == 6 || family == 0xf) 3196 model += ((fms >> 16) & 0xf) << 4; 3197 3198 if (debug) { 3199 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3200 max_level, family, model, stepping, family, model, stepping); 3201 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3202 ecx & (1 << 0) ? "SSE3" : "-", 3203 ecx & (1 << 3) ? "MONITOR" : "-", 3204 ecx & (1 << 6) ? "SMX" : "-", 3205 ecx & (1 << 7) ? "EIST" : "-", 3206 ecx & (1 << 8) ? "TM2" : "-", 3207 edx & (1 << 4) ? "TSC" : "-", 3208 edx & (1 << 5) ? "MSR" : "-", 3209 edx & (1 << 22) ? "ACPI-TM" : "-", 3210 edx & (1 << 29) ? "TM" : "-"); 3211 } 3212 3213 if (!(edx & (1 << 5))) 3214 errx(1, "CPUID: no MSR"); 3215 3216 /* 3217 * check max extended function levels of CPUID. 3218 * This is needed to check for invariant TSC. 3219 * This check is valid for both Intel and AMD. 3220 */ 3221 ebx = ecx = edx = 0; 3222 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3223 3224 if (max_extended_level >= 0x80000007) { 3225 3226 /* 3227 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3228 * this check is valid for both Intel and AMD 3229 */ 3230 __cpuid(0x80000007, eax, ebx, ecx, edx); 3231 has_invariant_tsc = edx & (1 << 8); 3232 } 3233 3234 /* 3235 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3236 * this check is valid for both Intel and AMD 3237 */ 3238 3239 __cpuid(0x6, eax, ebx, ecx, edx); 3240 has_aperf = ecx & (1 << 0); 3241 do_dts = eax & (1 << 0); 3242 do_ptm = eax & (1 << 6); 3243 has_hwp = eax & (1 << 7); 3244 has_hwp_notify = eax & (1 << 8); 3245 has_hwp_activity_window = eax & (1 << 9); 3246 has_hwp_epp = eax & (1 << 10); 3247 has_hwp_pkg = eax & (1 << 11); 3248 has_epb = ecx & (1 << 3); 3249 3250 if (debug) 3251 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, " 3252 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3253 has_aperf ? "" : "No-", 3254 do_dts ? "" : "No-", 3255 do_ptm ? "" : "No-", 3256 has_hwp ? "" : "No-", 3257 has_hwp_notify ? "" : "No-", 3258 has_hwp_activity_window ? "" : "No-", 3259 has_hwp_epp ? "" : "No-", 3260 has_hwp_pkg ? "" : "No-", 3261 has_epb ? "" : "No-"); 3262 3263 if (debug) 3264 decode_misc_enable_msr(); 3265 3266 if (max_level >= 0x7 && debug) { 3267 int has_sgx; 3268 3269 ecx = 0; 3270 3271 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3272 3273 has_sgx = ebx & (1 << 2); 3274 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3275 3276 if (has_sgx) 3277 decode_feature_control_msr(); 3278 } 3279 3280 if (max_level >= 0x15) { 3281 unsigned int eax_crystal; 3282 unsigned int ebx_tsc; 3283 3284 /* 3285 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3286 */ 3287 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3288 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3289 3290 if (ebx_tsc != 0) { 3291 3292 if (debug && (ebx != 0)) 3293 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3294 eax_crystal, ebx_tsc, crystal_hz); 3295 3296 if (crystal_hz == 0) 3297 switch(model) { 3298 case 0x4E: /* SKL */ 3299 case 0x5E: /* SKL */ 3300 case 0x8E: /* KBL */ 3301 case 0x9E: /* KBL */ 3302 crystal_hz = 24000000; /* 24.0 MHz */ 3303 break; 3304 case 0x55: /* SKX */ 3305 crystal_hz = 25000000; /* 25.0 MHz */ 3306 break; 3307 case 0x5C: /* BXT */ 3308 case 0x5F: /* DNV */ 3309 crystal_hz = 19200000; /* 19.2 MHz */ 3310 break; 3311 default: 3312 crystal_hz = 0; 3313 } 3314 3315 if (crystal_hz) { 3316 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3317 if (debug) 3318 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3319 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3320 } 3321 } 3322 } 3323 if (max_level >= 0x16) { 3324 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3325 3326 /* 3327 * CPUID 16H Base MHz, Max MHz, Bus MHz 3328 */ 3329 base_mhz = max_mhz = bus_mhz = edx = 0; 3330 3331 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3332 if (debug) 3333 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3334 base_mhz, max_mhz, bus_mhz); 3335 } 3336 3337 if (has_aperf) 3338 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3339 3340 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model); 3341 do_snb_cstates = has_snb_msrs(family, model); 3342 do_irtl_snb = has_snb_msrs(family, model); 3343 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); 3344 do_pc3 = (pkg_cstate_limit >= PCL__3); 3345 do_pc6 = (pkg_cstate_limit >= PCL__6); 3346 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); 3347 do_c8_c9_c10 = has_hsw_msrs(family, model); 3348 do_irtl_hsw = has_hsw_msrs(family, model); 3349 do_skl_residency = has_skl_msrs(family, model); 3350 do_slm_cstates = is_slm(family, model); 3351 do_knl_cstates = is_knl(family, model); 3352 3353 if (debug) 3354 decode_misc_pwr_mgmt_msr(); 3355 3356 rapl_probe(family, model); 3357 perf_limit_reasons_probe(family, model); 3358 3359 if (debug) 3360 dump_cstate_pstate_config_info(family, model); 3361 3362 if (has_skl_msrs(family, model)) 3363 calculate_tsc_tweak(); 3364 3365 do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK); 3366 3367 do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK); 3368 3369 return; 3370 } 3371 3372 void help() 3373 { 3374 fprintf(outf, 3375 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3376 "\n" 3377 "Turbostat forks the specified COMMAND and prints statistics\n" 3378 "when COMMAND completes.\n" 3379 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3380 "to print statistics, until interrupted.\n" 3381 "--debug run in \"debug\" mode\n" 3382 "--interval sec Override default 5-second measurement interval\n" 3383 "--help print this help message\n" 3384 "--counter msr print 32-bit counter at address \"msr\"\n" 3385 "--Counter msr print 64-bit Counter at address \"msr\"\n" 3386 "--out file create or truncate \"file\" for all output\n" 3387 "--msr msr print 32-bit value at address \"msr\"\n" 3388 "--MSR msr print 64-bit Value at address \"msr\"\n" 3389 "--version print version information\n" 3390 "\n" 3391 "For more help, run \"man turbostat\"\n"); 3392 } 3393 3394 3395 /* 3396 * in /dev/cpu/ return success for names that are numbers 3397 * ie. filter out ".", "..", "microcode". 3398 */ 3399 int dir_filter(const struct dirent *dirp) 3400 { 3401 if (isdigit(dirp->d_name[0])) 3402 return 1; 3403 else 3404 return 0; 3405 } 3406 3407 int open_dev_cpu_msr(int dummy1) 3408 { 3409 return 0; 3410 } 3411 3412 void topology_probe() 3413 { 3414 int i; 3415 int max_core_id = 0; 3416 int max_package_id = 0; 3417 int max_siblings = 0; 3418 struct cpu_topology { 3419 int core_id; 3420 int physical_package_id; 3421 } *cpus; 3422 3423 /* Initialize num_cpus, max_cpu_num */ 3424 topo.num_cpus = 0; 3425 topo.max_cpu_num = 0; 3426 for_all_proc_cpus(count_cpus); 3427 if (!summary_only && topo.num_cpus > 1) 3428 show_cpu = 1; 3429 3430 if (debug > 1) 3431 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3432 3433 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3434 if (cpus == NULL) 3435 err(1, "calloc cpus"); 3436 3437 /* 3438 * Allocate and initialize cpu_present_set 3439 */ 3440 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3441 if (cpu_present_set == NULL) 3442 err(3, "CPU_ALLOC"); 3443 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3444 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3445 for_all_proc_cpus(mark_cpu_present); 3446 3447 /* 3448 * Allocate and initialize cpu_affinity_set 3449 */ 3450 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3451 if (cpu_affinity_set == NULL) 3452 err(3, "CPU_ALLOC"); 3453 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3454 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3455 3456 3457 /* 3458 * For online cpus 3459 * find max_core_id, max_package_id 3460 */ 3461 for (i = 0; i <= topo.max_cpu_num; ++i) { 3462 int siblings; 3463 3464 if (cpu_is_not_present(i)) { 3465 if (debug > 1) 3466 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3467 continue; 3468 } 3469 cpus[i].core_id = get_core_id(i); 3470 if (cpus[i].core_id > max_core_id) 3471 max_core_id = cpus[i].core_id; 3472 3473 cpus[i].physical_package_id = get_physical_package_id(i); 3474 if (cpus[i].physical_package_id > max_package_id) 3475 max_package_id = cpus[i].physical_package_id; 3476 3477 siblings = get_num_ht_siblings(i); 3478 if (siblings > max_siblings) 3479 max_siblings = siblings; 3480 if (debug > 1) 3481 fprintf(outf, "cpu %d pkg %d core %d\n", 3482 i, cpus[i].physical_package_id, cpus[i].core_id); 3483 } 3484 topo.num_cores_per_pkg = max_core_id + 1; 3485 if (debug > 1) 3486 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 3487 max_core_id, topo.num_cores_per_pkg); 3488 if (debug && !summary_only && topo.num_cores_per_pkg > 1) 3489 show_core = 1; 3490 3491 topo.num_packages = max_package_id + 1; 3492 if (debug > 1) 3493 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 3494 max_package_id, topo.num_packages); 3495 if (debug && !summary_only && topo.num_packages > 1) 3496 show_pkg = 1; 3497 3498 topo.num_threads_per_core = max_siblings; 3499 if (debug > 1) 3500 fprintf(outf, "max_siblings %d\n", max_siblings); 3501 3502 free(cpus); 3503 } 3504 3505 void 3506 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 3507 { 3508 int i; 3509 3510 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 3511 topo.num_packages, sizeof(struct thread_data)); 3512 if (*t == NULL) 3513 goto error; 3514 3515 for (i = 0; i < topo.num_threads_per_core * 3516 topo.num_cores_per_pkg * topo.num_packages; i++) 3517 (*t)[i].cpu_id = -1; 3518 3519 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 3520 sizeof(struct core_data)); 3521 if (*c == NULL) 3522 goto error; 3523 3524 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 3525 (*c)[i].core_id = -1; 3526 3527 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 3528 if (*p == NULL) 3529 goto error; 3530 3531 for (i = 0; i < topo.num_packages; i++) 3532 (*p)[i].package_id = i; 3533 3534 return; 3535 error: 3536 err(1, "calloc counters"); 3537 } 3538 /* 3539 * init_counter() 3540 * 3541 * set cpu_id, core_num, pkg_num 3542 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 3543 * 3544 * increment topo.num_cores when 1st core in pkg seen 3545 */ 3546 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 3547 struct pkg_data *pkg_base, int thread_num, int core_num, 3548 int pkg_num, int cpu_id) 3549 { 3550 struct thread_data *t; 3551 struct core_data *c; 3552 struct pkg_data *p; 3553 3554 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 3555 c = GET_CORE(core_base, core_num, pkg_num); 3556 p = GET_PKG(pkg_base, pkg_num); 3557 3558 t->cpu_id = cpu_id; 3559 if (thread_num == 0) { 3560 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 3561 if (cpu_is_first_core_in_package(cpu_id)) 3562 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 3563 } 3564 3565 c->core_id = core_num; 3566 p->package_id = pkg_num; 3567 } 3568 3569 3570 int initialize_counters(int cpu_id) 3571 { 3572 int my_thread_id, my_core_id, my_package_id; 3573 3574 my_package_id = get_physical_package_id(cpu_id); 3575 my_core_id = get_core_id(cpu_id); 3576 my_thread_id = get_cpu_position_in_core(cpu_id); 3577 if (!my_thread_id) 3578 topo.num_cores++; 3579 3580 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3581 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3582 return 0; 3583 } 3584 3585 void allocate_output_buffer() 3586 { 3587 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 3588 outp = output_buffer; 3589 if (outp == NULL) 3590 err(-1, "calloc output buffer"); 3591 } 3592 void allocate_fd_percpu(void) 3593 { 3594 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3595 if (fd_percpu == NULL) 3596 err(-1, "calloc fd_percpu"); 3597 } 3598 void allocate_irq_buffers(void) 3599 { 3600 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 3601 if (irq_column_2_cpu == NULL) 3602 err(-1, "calloc %d", topo.num_cpus); 3603 3604 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3605 if (irqs_per_cpu == NULL) 3606 err(-1, "calloc %d", topo.max_cpu_num + 1); 3607 } 3608 void setup_all_buffers(void) 3609 { 3610 topology_probe(); 3611 allocate_irq_buffers(); 3612 allocate_fd_percpu(); 3613 allocate_counters(&thread_even, &core_even, &package_even); 3614 allocate_counters(&thread_odd, &core_odd, &package_odd); 3615 allocate_output_buffer(); 3616 for_all_proc_cpus(initialize_counters); 3617 } 3618 3619 void set_base_cpu(void) 3620 { 3621 base_cpu = sched_getcpu(); 3622 if (base_cpu < 0) 3623 err(-ENODEV, "No valid cpus found"); 3624 3625 if (debug > 1) 3626 fprintf(outf, "base_cpu = %d\n", base_cpu); 3627 } 3628 3629 void turbostat_init() 3630 { 3631 setup_all_buffers(); 3632 set_base_cpu(); 3633 check_dev_msr(); 3634 check_permissions(); 3635 process_cpuid(); 3636 3637 3638 if (debug) 3639 for_all_cpus(print_hwp, ODD_COUNTERS); 3640 3641 if (debug) 3642 for_all_cpus(print_epb, ODD_COUNTERS); 3643 3644 if (debug) 3645 for_all_cpus(print_perf_limit, ODD_COUNTERS); 3646 3647 if (debug) 3648 for_all_cpus(print_rapl, ODD_COUNTERS); 3649 3650 for_all_cpus(set_temperature_target, ODD_COUNTERS); 3651 3652 if (debug) 3653 for_all_cpus(print_thermal, ODD_COUNTERS); 3654 3655 if (debug && do_irtl_snb) 3656 print_irtl(); 3657 } 3658 3659 int fork_it(char **argv) 3660 { 3661 pid_t child_pid; 3662 int status; 3663 3664 status = for_all_cpus(get_counters, EVEN_COUNTERS); 3665 if (status) 3666 exit(status); 3667 /* clear affinity side-effect of get_counters() */ 3668 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 3669 gettimeofday(&tv_even, (struct timezone *)NULL); 3670 3671 child_pid = fork(); 3672 if (!child_pid) { 3673 /* child */ 3674 execvp(argv[0], argv); 3675 } else { 3676 3677 /* parent */ 3678 if (child_pid == -1) 3679 err(1, "fork"); 3680 3681 signal(SIGINT, SIG_IGN); 3682 signal(SIGQUIT, SIG_IGN); 3683 if (waitpid(child_pid, &status, 0) == -1) 3684 err(status, "waitpid"); 3685 } 3686 /* 3687 * n.b. fork_it() does not check for errors from for_all_cpus() 3688 * because re-starting is problematic when forking 3689 */ 3690 for_all_cpus(get_counters, ODD_COUNTERS); 3691 gettimeofday(&tv_odd, (struct timezone *)NULL); 3692 timersub(&tv_odd, &tv_even, &tv_delta); 3693 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 3694 fprintf(outf, "%s: Counter reset detected\n", progname); 3695 else { 3696 compute_average(EVEN_COUNTERS); 3697 format_all_counters(EVEN_COUNTERS); 3698 } 3699 3700 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 3701 3702 flush_output_stderr(); 3703 3704 return status; 3705 } 3706 3707 int get_and_dump_counters(void) 3708 { 3709 int status; 3710 3711 status = for_all_cpus(get_counters, ODD_COUNTERS); 3712 if (status) 3713 return status; 3714 3715 status = for_all_cpus(dump_counters, ODD_COUNTERS); 3716 if (status) 3717 return status; 3718 3719 flush_output_stdout(); 3720 3721 return status; 3722 } 3723 3724 void print_version() { 3725 fprintf(outf, "turbostat version 4.14 22 Apr 2016" 3726 " - Len Brown <lenb@kernel.org>\n"); 3727 } 3728 3729 void cmdline(int argc, char **argv) 3730 { 3731 int opt; 3732 int option_index = 0; 3733 static struct option long_options[] = { 3734 {"Counter", required_argument, 0, 'C'}, 3735 {"counter", required_argument, 0, 'c'}, 3736 {"Dump", no_argument, 0, 'D'}, 3737 {"debug", no_argument, 0, 'd'}, 3738 {"interval", required_argument, 0, 'i'}, 3739 {"help", no_argument, 0, 'h'}, 3740 {"Joules", no_argument, 0, 'J'}, 3741 {"MSR", required_argument, 0, 'M'}, 3742 {"msr", required_argument, 0, 'm'}, 3743 {"out", required_argument, 0, 'o'}, 3744 {"Package", no_argument, 0, 'p'}, 3745 {"processor", no_argument, 0, 'p'}, 3746 {"Summary", no_argument, 0, 'S'}, 3747 {"TCC", required_argument, 0, 'T'}, 3748 {"version", no_argument, 0, 'v' }, 3749 {0, 0, 0, 0 } 3750 }; 3751 3752 progname = argv[0]; 3753 3754 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", 3755 long_options, &option_index)) != -1) { 3756 switch (opt) { 3757 case 'C': 3758 sscanf(optarg, "%x", &extra_delta_offset64); 3759 break; 3760 case 'c': 3761 sscanf(optarg, "%x", &extra_delta_offset32); 3762 break; 3763 case 'D': 3764 dump_only++; 3765 break; 3766 case 'd': 3767 debug++; 3768 break; 3769 case 'h': 3770 default: 3771 help(); 3772 exit(1); 3773 case 'i': 3774 { 3775 double interval = strtod(optarg, NULL); 3776 3777 if (interval < 0.001) { 3778 fprintf(outf, "interval %f seconds is too small\n", 3779 interval); 3780 exit(2); 3781 } 3782 3783 interval_ts.tv_sec = interval; 3784 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 3785 } 3786 break; 3787 case 'J': 3788 rapl_joules++; 3789 break; 3790 case 'M': 3791 sscanf(optarg, "%x", &extra_msr_offset64); 3792 break; 3793 case 'm': 3794 sscanf(optarg, "%x", &extra_msr_offset32); 3795 break; 3796 case 'o': 3797 outf = fopen_or_die(optarg, "w"); 3798 break; 3799 case 'P': 3800 show_pkg_only++; 3801 break; 3802 case 'p': 3803 show_core_only++; 3804 break; 3805 case 'S': 3806 summary_only++; 3807 break; 3808 case 'T': 3809 tcc_activation_temp_override = atoi(optarg); 3810 break; 3811 case 'v': 3812 print_version(); 3813 exit(0); 3814 break; 3815 } 3816 } 3817 } 3818 3819 int main(int argc, char **argv) 3820 { 3821 outf = stderr; 3822 3823 cmdline(argc, argv); 3824 3825 if (debug) 3826 print_version(); 3827 3828 turbostat_init(); 3829 3830 /* dump counters and exit */ 3831 if (dump_only) 3832 return get_and_dump_counters(); 3833 3834 /* 3835 * if any params left, it must be a command to fork 3836 */ 3837 if (argc - optind) 3838 return fork_it(argv + optind); 3839 else 3840 turbostat_loop(); 3841 3842 return 0; 3843 } 3844