arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller

[ Upstream commit 67e4656f4487b95a39e45884c99235f62ebfaa47 ]

Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor

arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller

[ Upstream commit 67e4656f4487b95a39e45884c99235f62ebfaa47 ]

Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor
code of Trinket DTSI from Xiaomi Laurel device, to fix dtbs_check
warnings:

sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'interrupt-names' is a required property
sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'oneOf' conditional failed, one must be fixed:
'interrupts' is a required property
'interrupts-extended' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20231111164229.63803-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: qcom: sm6125: Pad APPS IOMMU address to 8 characters

[ Upstream commit 310cdafc4a56827d1aeda7cc297939034adb8f99 ]

APPS IOMMU is the only node in sm6125.dtsi that doesn't have its
addres

arm64: dts: qcom: sm6125: Pad APPS IOMMU address to 8 characters

[ Upstream commit 310cdafc4a56827d1aeda7cc297939034adb8f99 ]

APPS IOMMU is the only node in sm6125.dtsi that doesn't have its
address padded to 8 hexadecimals; fix this by prepending a 0.

Fixes: 8ddb4bc3d3b5 ("arm64: dts: qcom: sm6125: Configure APPS SMMU")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-2-a3f287dd6c07@somainline.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms

Rather than having the RPM GLINK channels as the only child of a dummy
top-level rpm-glink node, switch to representing the RPM as remoteproc

arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms

Rather than having the RPM GLINK channels as the only child of a dummy
top-level rpm-glink node, switch to representing the RPM as remoteproc
like all the other remoteprocs (modem DSP, ...).

This allows assigning additional subdevices to it like the MPM
interrupt-controller or rpm-master-stats.

Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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arm64: dts: qcom: sm6125: add unit address to soc node

"soc" node is supposed to have unit address:

Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-

arm64: dts: qcom: sm6125: add unit address to soc node

"soc" node is supposed to have unit address:

Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420063610.11068-7-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: add missing cache properties

Add required cache-level and cache-unified properties to fix warnings
like:

qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
qdu1

arm64: dts: qcom: add missing cache properties

Add required cache-level and cache-unified properties to fix warnings
like:

qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: sm6125: Add UFS nodes

Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Signed-off-by: Bjorn Andersson <

arm64: dts: qcom: sm6125: Add UFS nodes

Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306170817.3806-5-they@mint.lgbt

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arm64: dts: qcom: sm6125: add compatible fallback to mailbox

SM6125 mailbox is compatible with MSM8994.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Ande

arm64: dts: qcom: sm6125: add compatible fallback to mailbox

SM6125 mailbox is compatible with MSM8994.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-9-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: drop incorrect cell-index from SPMI

The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:

sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated

arm64: dts: qcom: drop incorrect cell-index from SPMI

The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:

sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four S

arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5
I2C Serial Engines.

[Marijn: Add iommus, reword patch description, reorder all properties,
sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
to 3]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-3-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines

Add pin setup for SPI/I2C Serial Engines that are supported under the
Qualcomm Universal Peripheral found on SM6125.

[Un-nes

arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines

Add pin setup for SPI/I2C Serial Engines that are supported under the
Qualcomm Universal Peripheral found on SM6125.

[Un-nest pins, remove duplicate pins= properties, follow new node naming
conventions, fix qup_14 -> qup14 function typo]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-2-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Add GPI DMA nodes

Add nodes for GPI DMA hosts on SM6125.

[Marijn: reorder properties, use sdm845 fallback compatible, disable by
default, use 3 instead of 5 dma cells]

S

arm64: dts: qcom: sm6125: Add GPI DMA nodes

Add nodes for GPI DMA hosts on SM6125.

[Marijn: reorder properties, use sdm845 fallback compatible, disable by
default, use 3 instead of 5 dma cells]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222194600.139854-3-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Add IOMMU context to DWC3

Add an IOMMU context to the USB DWC3 controller, required to get USB
functionality upon enablement of apps_smmu.

Signed-off-by: AngeloGioacchino

arm64: dts: qcom: sm6125: Add IOMMU context to DWC3

Add an IOMMU context to the USB DWC3 controller, required to get USB
functionality upon enablement of apps_smmu.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-5-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2 nodes

When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream ma

arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2 nodes

When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream mapping for (among
which) the SDHCI hardware and breaking its ADMA feature. This feature
can be disabled with:

sdhci.debug_quirks=0x40

But it is of course desired to have this feature enabled and working
through the SMMU.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-4-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Configure APPS SMMU

Add a node for the APPS SMMU, to which various devices such as USB and
storage nodes are connected.

[Marijn: add the new, generic, "qcom,smmu-500" comp

arm64: dts: qcom: sm6125: Configure APPS SMMU

Add a node for the APPS SMMU, to which various devices such as USB and
storage nodes are connected.

[Marijn: add the new, generic, "qcom,smmu-500" compatible, add patch
description, reorder # properties]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-3-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Reorder HSUSB PHY clocks to match bindings

Reorder the clocks and corresponding names to match the QUSB2 phy
schema, fixing the following CHECK_DTBS errors:

arch/arm64

arm64: dts: qcom: sm6125: Reorder HSUSB PHY clocks to match bindings

Reorder the clocks and corresponding names to match the QUSB2 phy
schema, fixing the following CHECK_DTBS errors:

arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:0: 'cfg_ahb' was expected
From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:1: 'ref' was expected
From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml

Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216213343.1140143-1-marijn.suijten@somainline.org

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arm64: dts: qcom: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Ca

arm64: dts: qcom: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).

To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com

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arm64: dts: qcom: sm6125: Enable Command Queue Engine (CQE) for SDHCI 1

Downstream sources confirm sm6125 supports CQE, and after fixing the
reg name for this range [1] this feature probes and enabl

arm64: dts: qcom: sm6125: Enable Command Queue Engine (CQE) for SDHCI 1

Downstream sources confirm sm6125 supports CQE, and after fixing the
reg name for this range [1] this feature probes and enables correctly:

[ 0.391950] sdhci_msm 4744000.mmc: mmc0: CQE init: success

[1]: https://lore.kernel.org/all/20221026163646.37433-1-krzysztof.kozlowski@linaro.org/

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107214702.311271-1-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: fix SDHCI CQE reg names

SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
registers is cqhci, not core.

Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add supp

arm64: dts: qcom: sm6125: fix SDHCI CQE reg names

SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
registers is cqhci, not core.

Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Sony Xperia 10 II
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026163646.37433-1-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema

DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.

arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema

DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220930192954.242546-11-krzysztof.kozlowski@linaro.org

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arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema

DT schema expects TLMM pin configuration nodes to be named with '-state'
suffix and their optional children with '-pins' suffix.

arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema

DT schema expects TLMM pin configuration nodes to be named with '-state'
suffix and their optional children with '-pins' suffix.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220912061746.6311-35-krzysztof.kozlowski@linaro.org

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Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"

This reverts commit afcbe252e9c19161e4d4c95f33faaf592f1de086.

The commit in question caused my sc7280-herobrine-herobrine-r1 board
not to

Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"

This reverts commit afcbe252e9c19161e4d4c95f33faaf592f1de086.

The commit in question caused my sc7280-herobrine-herobrine-r1 board
not to boot anymore. This shouldn't be too surprising since the driver
is relying on the name "cqhci".

The issue seems to be that someone decided to change the names of
things when the binding moved from .txt to .yaml. We should go back to
the names that the bindings have historically specified.

For some history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci
memory ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc:
sdhci-msm: Add CQE reg map").

Fixes: afcbe252e9c1 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid

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arm64: dts: qcom: sm6125: Add DLL/DDR configuration on SDHCI 1/2

These config values have been extracted from CodeLinaro's most recent
trinket/sm6125 tag:
https://git.codelinaro.org/clo/la/kernel/ms

arm64: dts: qcom: sm6125: Add DLL/DDR configuration on SDHCI 1/2

These config values have been extracted from CodeLinaro's most recent
trinket/sm6125 tag:
https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/LA.UM.9.11.r1-05600-NICOBAR.QSSI12.0/arch/arm64/boot/dts/qcom/trinket.dtsi

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220508100336.127176-3-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Append -state suffix to pinctrl nodes

According to qcom,sm6125-pinctrl.yaml all nodes inside the tlmm must be
suffixed by -state:

qcom/sm6125-sony-xperia-seine-pdx201.

arm64: dts: qcom: sm6125: Append -state suffix to pinctrl nodes

According to qcom,sm6125-pinctrl.yaml all nodes inside the tlmm must be
suffixed by -state:

qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: 'sdc2-off', 'sdc2-on' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'

The label names have been updated to match, going from sdc2_state_X to
sdc2_X_state.

Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220508100336.127176-2-marijn.suijten@somainline.org

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arm64: dts: qcom: sm6125: Move sdc2 pinctrl from seine-pdx201 to sm6125

Both the sdc2-on and sdc2-off pinctrl nodes are used by the
sdhci@4784000 node in sm6125.dtsi. Surprisingly sdc2-off is defin

arm64: dts: qcom: sm6125: Move sdc2 pinctrl from seine-pdx201 to sm6125

Both the sdc2-on and sdc2-off pinctrl nodes are used by the
sdhci@4784000 node in sm6125.dtsi. Surprisingly sdc2-off is defined in
sm6125, yet its sdc2-on counterpart is only defined in board-specific DT
for the Sony Seine PDX201 board/device resulting in an "undefined label
&sdc2_state_on" error if sm6125.dtsi were included elsewhere.
This sm6125 base dtsi should not rely on externally defined labels; the
properties referencing it should then also be written externally.
Since the sdc2-on pin configuration is board-independent just like
sdc2-off, move it from seine-pdx201.dts into sm6125.dtsi.

The SDCard-detect pin (gpio98) is however board-specific, and remains as
an overwrite in seine-pdx201.dts for both the on and off state.

As a drive-by cleanup, reorder bias- and drive-strength properties.

Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220508100336.127176-1-marijn.suijten@somainline.org

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arm64: dts: qcom: Fix 'reg-names' for sdhci nodes

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'r

arm64: dts: qcom: Fix 'reg-names' for sdhci nodes

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'reg-names' as various possible combinations
are possible for different qcom SoC dts files.

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-6-bhupesh.sharma@linaro.org

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