1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32000>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo260"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 capacity-dmips-mhz = <1024>; 45 next-level-cache = <&L2_0>; 46 L2_0: l2-cache { 47 compatible = "cache"; 48 cache-level = <2>; 49 }; 50 }; 51 52 CPU1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo260"; 55 reg = <0x0 0x1>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <1024>; 58 next-level-cache = <&L2_0>; 59 }; 60 61 CPU2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo260"; 64 reg = <0x0 0x2>; 65 enable-method = "psci"; 66 capacity-dmips-mhz = <1024>; 67 next-level-cache = <&L2_0>; 68 }; 69 70 CPU3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo260"; 73 reg = <0x0 0x3>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <1024>; 76 next-level-cache = <&L2_0>; 77 }; 78 79 CPU4: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo260"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <1638>; 85 next-level-cache = <&L2_1>; 86 L2_1: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 }; 90 }; 91 92 CPU5: cpu@101 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo260"; 95 reg = <0x0 0x101>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1638>; 98 next-level-cache = <&L2_1>; 99 }; 100 101 CPU6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x102>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1638>; 107 next-level-cache = <&L2_1>; 108 }; 109 110 CPU7: cpu@103 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo260"; 113 reg = <0x0 0x103>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <1638>; 116 next-level-cache = <&L2_1>; 117 }; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&CPU0>; 123 }; 124 125 core1 { 126 cpu = <&CPU1>; 127 }; 128 129 core2 { 130 cpu = <&CPU2>; 131 }; 132 133 core3 { 134 cpu = <&CPU3>; 135 }; 136 }; 137 138 cluster1 { 139 core0 { 140 cpu = <&CPU4>; 141 }; 142 143 core1 { 144 cpu = <&CPU5>; 145 }; 146 147 core2 { 148 cpu = <&CPU6>; 149 }; 150 151 core3 { 152 cpu = <&CPU7>; 153 }; 154 }; 155 }; 156 }; 157 158 firmware { 159 scm: scm { 160 compatible = "qcom,scm-sm6125", "qcom,scm"; 161 #reset-cells = <1>; 162 }; 163 }; 164 165 memory@40000000 { 166 /* We expect the bootloader to fill in the size */ 167 reg = <0x0 0x40000000 0x0 0x0>; 168 device_type = "memory"; 169 }; 170 171 pmu { 172 compatible = "arm,armv8-pmuv3"; 173 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 psci { 177 compatible = "arm,psci-1.0"; 178 method = "smc"; 179 }; 180 181 reserved_memory: reserved-memory { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges; 185 186 hyp_mem: memory@45700000 { 187 reg = <0x0 0x45700000 0x0 0x600000>; 188 no-map; 189 }; 190 191 xbl_aop_mem: memory@45e00000 { 192 reg = <0x0 0x45e00000 0x0 0x140000>; 193 no-map; 194 }; 195 196 sec_apps_mem: memory@45fff000 { 197 reg = <0x0 0x45fff000 0x0 0x1000>; 198 no-map; 199 }; 200 201 smem_mem: memory@46000000 { 202 reg = <0x0 0x46000000 0x0 0x200000>; 203 no-map; 204 }; 205 206 reserved_mem1: memory@46200000 { 207 reg = <0x0 0x46200000 0x0 0x2d00000>; 208 no-map; 209 }; 210 211 camera_mem: memory@4ab00000 { 212 reg = <0x0 0x4ab00000 0x0 0x500000>; 213 no-map; 214 }; 215 216 modem_mem: memory@4b000000 { 217 reg = <0x0 0x4b000000 0x0 0x7e00000>; 218 no-map; 219 }; 220 221 venus_mem: memory@52e00000 { 222 reg = <0x0 0x52e00000 0x0 0x500000>; 223 no-map; 224 }; 225 226 wlan_msa_mem: memory@53300000 { 227 reg = <0x0 0x53300000 0x0 0x200000>; 228 no-map; 229 }; 230 231 cdsp_mem: memory@53500000 { 232 reg = <0x0 0x53500000 0x0 0x1e00000>; 233 no-map; 234 }; 235 236 adsp_pil_mem: memory@55300000 { 237 reg = <0x0 0x55300000 0x0 0x1e00000>; 238 no-map; 239 }; 240 241 ipa_fw_mem: memory@57100000 { 242 reg = <0x0 0x57100000 0x0 0x10000>; 243 no-map; 244 }; 245 246 ipa_gsi_mem: memory@57110000 { 247 reg = <0x0 0x57110000 0x0 0x5000>; 248 no-map; 249 }; 250 251 gpu_mem: memory@57115000 { 252 reg = <0x0 0x57115000 0x0 0x2000>; 253 no-map; 254 }; 255 256 cont_splash_mem: memory@5c000000 { 257 reg = <0x0 0x5c000000 0x0 0x00f00000>; 258 no-map; 259 }; 260 261 dfps_data_mem: memory@5cf00000 { 262 reg = <0x0 0x5cf00000 0x0 0x0100000>; 263 no-map; 264 }; 265 266 cdsp_sec_mem: memory@5f800000 { 267 reg = <0x0 0x5f800000 0x0 0x1e00000>; 268 no-map; 269 }; 270 271 qseecom_mem: memory@5e400000 { 272 reg = <0x0 0x5e400000 0x0 0x1400000>; 273 no-map; 274 }; 275 276 sdsp_mem: memory@f3000000 { 277 reg = <0x0 0xf3000000 0x0 0x400000>; 278 no-map; 279 }; 280 281 adsp_mem: memory@f3400000 { 282 reg = <0x0 0xf3400000 0x0 0x800000>; 283 no-map; 284 }; 285 286 qseecom_ta_mem: memory@13fc00000 { 287 reg = <0x1 0x3fc00000 0x0 0x400000>; 288 no-map; 289 }; 290 }; 291 292 rpm-glink { 293 compatible = "qcom,glink-rpm"; 294 295 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 296 qcom,rpm-msg-ram = <&rpm_msg_ram>; 297 mboxes = <&apcs_glb 0>; 298 299 rpm_requests: rpm-requests { 300 compatible = "qcom,rpm-sm6125"; 301 qcom,glink-channels = "rpm_requests"; 302 303 rpmcc: clock-controller { 304 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 305 #clock-cells = <1>; 306 }; 307 308 rpmpd: power-controller { 309 compatible = "qcom,sm6125-rpmpd"; 310 #power-domain-cells = <1>; 311 operating-points-v2 = <&rpmpd_opp_table>; 312 313 rpmpd_opp_table: opp-table { 314 compatible = "operating-points-v2"; 315 316 rpmpd_opp_ret: opp1 { 317 opp-level = <RPM_SMD_LEVEL_RETENTION>; 318 }; 319 320 rpmpd_opp_ret_plus: opp2 { 321 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 322 }; 323 324 rpmpd_opp_min_svs: opp3 { 325 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 326 }; 327 328 rpmpd_opp_low_svs: opp4 { 329 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 330 }; 331 332 rpmpd_opp_svs: opp5 { 333 opp-level = <RPM_SMD_LEVEL_SVS>; 334 }; 335 336 rpmpd_opp_svs_plus: opp6 { 337 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 338 }; 339 340 rpmpd_opp_nom: opp7 { 341 opp-level = <RPM_SMD_LEVEL_NOM>; 342 }; 343 344 rpmpd_opp_nom_plus: opp8 { 345 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 346 }; 347 348 rpmpd_opp_turbo: opp9 { 349 opp-level = <RPM_SMD_LEVEL_TURBO>; 350 }; 351 352 rpmpd_opp_turbo_no_cpr: opp10 { 353 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 354 }; 355 }; 356 }; 357 }; 358 }; 359 360 smem: smem { 361 compatible = "qcom,smem"; 362 memory-region = <&smem_mem>; 363 hwlocks = <&tcsr_mutex 3>; 364 }; 365 366 soc { 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges = <0x00 0x00 0x00 0xffffffff>; 370 compatible = "simple-bus"; 371 372 tcsr_mutex: hwlock@340000 { 373 compatible = "qcom,tcsr-mutex"; 374 reg = <0x00340000 0x20000>; 375 #hwlock-cells = <1>; 376 }; 377 378 tlmm: pinctrl@500000 { 379 compatible = "qcom,sm6125-tlmm"; 380 reg = <0x00500000 0x400000>, 381 <0x00900000 0x400000>, 382 <0x00d00000 0x400000>; 383 reg-names = "west", "south", "east"; 384 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 385 gpio-controller; 386 gpio-ranges = <&tlmm 0 0 134>; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 391 sdc2_off_state: sdc2-off-state { 392 clk-pins { 393 pins = "sdc2_clk"; 394 drive-strength = <2>; 395 bias-disable; 396 }; 397 398 cmd-pins { 399 pins = "sdc2_cmd"; 400 drive-strength = <2>; 401 bias-pull-up; 402 }; 403 404 data-pins { 405 pins = "sdc2_data"; 406 drive-strength = <2>; 407 bias-pull-up; 408 }; 409 }; 410 411 sdc2_on_state: sdc2-on-state { 412 clk-pins { 413 pins = "sdc2_clk"; 414 drive-strength = <16>; 415 bias-disable; 416 }; 417 418 cmd-pins { 419 pins = "sdc2_cmd"; 420 drive-strength = <10>; 421 bias-pull-up; 422 }; 423 424 data-pins { 425 pins = "sdc2_data"; 426 drive-strength = <10>; 427 bias-pull-up; 428 }; 429 }; 430 }; 431 432 gcc: clock-controller@1400000 { 433 compatible = "qcom,gcc-sm6125"; 434 reg = <0x01400000 0x1f0000>; 435 #clock-cells = <1>; 436 #reset-cells = <1>; 437 #power-domain-cells = <1>; 438 clock-names = "bi_tcxo", "sleep_clk"; 439 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 440 }; 441 442 hsusb_phy1: phy@1613000 { 443 compatible = "qcom,msm8996-qusb2-phy"; 444 reg = <0x01613000 0x180>; 445 #phy-cells = <0>; 446 447 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 448 <&rpmcc RPM_SMD_XO_CLK_SRC>; 449 clock-names = "cfg_ahb", "ref"; 450 451 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 452 status = "disabled"; 453 }; 454 455 rpm_msg_ram: sram@45f0000 { 456 compatible = "qcom,rpm-msg-ram"; 457 reg = <0x045f0000 0x7000>; 458 }; 459 460 sdhc_1: mmc@4744000 { 461 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 462 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 463 reg-names = "hc", "cqhci"; 464 465 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "hc_irq", "pwr_irq"; 468 469 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 470 <&gcc GCC_SDCC1_APPS_CLK>, 471 <&xo_board>; 472 clock-names = "iface", "core", "xo"; 473 iommus = <&apps_smmu 0x160 0x0>; 474 475 power-domains = <&rpmpd SM6125_VDDCX>; 476 477 qcom,dll-config = <0x000f642c>; 478 qcom,ddr-config = <0x80040873>; 479 480 bus-width = <8>; 481 non-removable; 482 supports-cqe; 483 484 status = "disabled"; 485 }; 486 487 sdhc_2: mmc@4784000 { 488 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 489 reg = <0x04784000 0x1000>; 490 reg-names = "hc"; 491 492 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "hc_irq", "pwr_irq"; 495 496 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 497 <&gcc GCC_SDCC2_APPS_CLK>, 498 <&xo_board>; 499 clock-names = "iface", "core", "xo"; 500 iommus = <&apps_smmu 0x180 0x0>; 501 502 pinctrl-0 = <&sdc2_on_state>; 503 pinctrl-1 = <&sdc2_off_state>; 504 pinctrl-names = "default", "sleep"; 505 506 power-domains = <&rpmpd SM6125_VDDCX>; 507 508 qcom,dll-config = <0x0007642c>; 509 qcom,ddr-config = <0x80040873>; 510 511 bus-width = <4>; 512 status = "disabled"; 513 }; 514 515 usb3: usb@4ef8800 { 516 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 517 reg = <0x04ef8800 0x400>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 522 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 523 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 524 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 525 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 526 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 527 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 528 clock-names = "cfg_noc", 529 "core", 530 "iface", 531 "sleep", 532 "mock_utmi", 533 "xo"; 534 535 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 536 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 537 assigned-clock-rates = <19200000>, <66666667>; 538 539 power-domains = <&gcc USB30_PRIM_GDSC>; 540 qcom,select-utmi-as-pipe-clk; 541 status = "disabled"; 542 543 usb3_dwc3: usb@4e00000 { 544 compatible = "snps,dwc3"; 545 reg = <0x04e00000 0xcd00>; 546 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 547 iommus = <&apps_smmu 0x100 0x0>; 548 phys = <&hsusb_phy1>; 549 phy-names = "usb2-phy"; 550 snps,dis_u2_susphy_quirk; 551 snps,dis_enblslpm_quirk; 552 maximum-speed = "high-speed"; 553 dr_mode = "peripheral"; 554 }; 555 }; 556 557 sram@4690000 { 558 compatible = "qcom,rpm-stats"; 559 reg = <0x04690000 0x10000>; 560 }; 561 562 spmi_bus: spmi@1c40000 { 563 compatible = "qcom,spmi-pmic-arb"; 564 reg = <0x01c40000 0x1100>, 565 <0x01e00000 0x2000000>, 566 <0x03e00000 0x100000>, 567 <0x03f00000 0xa0000>, 568 <0x01c0a000 0x26000>; 569 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 570 interrupt-names = "periph_irq"; 571 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 572 qcom,ee = <0>; 573 qcom,channel = <0>; 574 #address-cells = <2>; 575 #size-cells = <0>; 576 interrupt-controller; 577 #interrupt-cells = <4>; 578 cell-index = <0>; 579 }; 580 581 apps_smmu: iommu@c600000 { 582 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 583 reg = <0xc600000 0x80000>; 584 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 649 650 #global-interrupts = <1>; 651 #iommu-cells = <2>; 652 }; 653 654 apcs_glb: mailbox@f111000 { 655 compatible = "qcom,sm6125-apcs-hmss-global"; 656 reg = <0x0f111000 0x1000>; 657 658 #mbox-cells = <1>; 659 }; 660 661 timer@f120000 { 662 compatible = "arm,armv7-timer-mem"; 663 #address-cells = <1>; 664 #size-cells = <1>; 665 ranges; 666 reg = <0x0f120000 0x1000>; 667 clock-frequency = <19200000>; 668 669 frame@f121000 { 670 frame-number = <0>; 671 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 673 reg = <0x0f121000 0x1000>, 674 <0x0f122000 0x1000>; 675 }; 676 677 frame@f123000 { 678 frame-number = <1>; 679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 680 reg = <0x0f123000 0x1000>; 681 status = "disabled"; 682 }; 683 684 frame@f124000 { 685 frame-number = <2>; 686 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 687 reg = <0x0f124000 0x1000>; 688 status = "disabled"; 689 }; 690 691 frame@f125000 { 692 frame-number = <3>; 693 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 694 reg = <0x0f125000 0x1000>; 695 status = "disabled"; 696 }; 697 698 frame@f126000 { 699 frame-number = <4>; 700 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 701 reg = <0x0f126000 0x1000>; 702 status = "disabled"; 703 }; 704 705 frame@f127000 { 706 frame-number = <5>; 707 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 708 reg = <0x0f127000 0x1000>; 709 status = "disabled"; 710 }; 711 712 frame@f128000 { 713 frame-number = <6>; 714 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 715 reg = <0x0f128000 0x1000>; 716 status = "disabled"; 717 }; 718 }; 719 720 intc: interrupt-controller@f200000 { 721 compatible = "arm,gic-v3"; 722 reg = <0x0f200000 0x20000>, 723 <0x0f300000 0x100000>; 724 #interrupt-cells = <3>; 725 interrupt-controller; 726 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 727 }; 728 }; 729 730 timer { 731 compatible = "arm,armv8-timer"; 732 interrupts = <GIC_PPI 1 0xf08 733 GIC_PPI 2 0xf08 734 GIC_PPI 3 0xf08 735 GIC_PPI 0 0xf08>; 736 clock-frequency = <19200000>; 737 }; 738}; 739